Hi Alistair,
On Sat, Aug 24, 2019 at 1:29 AM Alistair Francis wrote:
>
> On Thu, Aug 22, 2019 at 10:15 PM Bin Meng wrote:
> >
> > As of today, the QEMU 'sifive_u' machine is a special target that does
> > not boot the upstream OpenSBI/U-Boot firmware images built for the real
> > SiFive HiFive
I give my thought.
Paolo may add more.
> -Original Message-
> From: Kinney, Michael D
> Sent: Friday, August 23, 2019 11:25 PM
> To: Yao, Jiewen ; Paolo Bonzini
> ; Laszlo Ersek ;
> r...@edk2.groups.io; Kinney, Michael D
> Cc: Alex Williamson ; de...@edk2.groups.io;
> qemu devel list ;
On Wed, Aug 21, 2019 at 9:36 AM Georg Kotheimer
wrote:
>
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target
On Thu, Aug 22, 2019 at 10:35 PM Bin Meng wrote:
>
> Add PRCI mmio base address and size mappings to sifive_u machine,
> and generate the corresponding device tree node.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
> Changes in v5:
> - create sifive_u_prci
On Thu, Aug 22, 2019 at 10:21 PM Bin Meng wrote:
>
> This adds a simple PRCI model for FU540 (sifive_u). It has different
> register layout from the existing PRCI model for FE310 (sifive_e).
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v5:
> - change to use defines instead of enums
> -
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 11 +++
target/riscv/cpu_helper.c | 4 ++--
target/riscv/op_helper.c | 2 +-
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 06ee551ebe..39e1c130df 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -447,6 +447,9 @@ static void
Respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when performing
floating point operations when V=0.
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c
23.08.2019. 08.13, "Markus Armbruster" је написао/ла:
>
> Philippe Mathieu-Daudé writes:
>
> > Trivial cleanup of .mailmap to have a nice 'git shortlog' output.
> >
> > Philippe Mathieu-Daudé (3):
> > mailmap: Reorder by sections
> > mailmap: Update philmd email address
> > mailmap: Add
Mark both sstatus and vsstatus as dirty (3).
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8ac72c6470..19771904f4 100644
--- a/target/riscv/translate.c
+++
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 6 ++
target/riscv/cpu.h| 7 +++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 7 +++
target/riscv/csr.c| 23 +++
target/riscv/op_helper.c | 4
6 files
On Fri, Aug 23, 2019 at 11:21:50AM -0500, Eric Blake wrote:
>On 8/19/19 9:08 AM, Wei Yang wrote:
>> On Mon, Aug 19, 2019 at 12:26:32PM +0100, Dr. David Alan Gilbert wrote:
>>> * Wei Yang (richardw.y...@linux.intel.com) wrote:
>
>Typo in the subject line: migrtion should be migration
>
No
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9aa6906acd..8b9871f9ea 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@
Signed-off-by: Alistair Francis
---
target/riscv/op_helper.c | 66
1 file changed, 54 insertions(+), 12 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index beb34e705b..5bcf5d2ff7 100644
--- a/target/riscv/op_helper.c
+++
The qemu_log_mask(CPU_LOG_MMU,... calls trigger false positive
checkpatch errors which are being ignored.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 94 +++
1 file changed, 86 insertions(+), 8 deletions(-)
diff --git
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 39 ++-
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 098873c83e..9aa6906acd 100644
--- a/target/riscv/cpu_helper.c
+++
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 11
target/riscv/csr.c | 119
2 files changed, 130 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 204d9d9a79..78067901a2 100644
---
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 96 +++
1 file changed, 86 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8b9871f9ea..188d5cb39f 100644
--- a/target/riscv/cpu_helper.c
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 4 +--
target/riscv/cpu_helper.c | 71 +--
target/riscv/csr.c| 4 +--
3 files changed, 65 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode| 23 ++-
.../riscv/insn_trans/trans_privileged.inc.c | 40 +++
2 files changed, 54 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
Dump the Hypervisor registers and the current Hypervisor state.
While we are editing this code let's also dump stvec and scause.
Signed-off-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff
When the PLIC generates an interrupt ensure we always set it for the SIP
CSR that corresponds to the HS (V=0) register.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_plic.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 68 ++
1 file changed, 68 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 471f23a1d0..388775d45a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -98,6 +98,20
Signed-off-by: Alistair Francis
---
target/riscv/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d150551bc9..beb34e705b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -130,9
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 5 +
1 file changed, 5
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h | 6 ++
target/riscv/cpu_helper.c | 23 +++
3 files changed, 31 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0ef1ecb0e0..3a95c41428 100644
---
Signed-off-by: Alistair Francis
---
target/riscv/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index adeddb85f6..8ac72c6470 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -810,7 +810,15 @@
To handle the new Hypervisor CSR register swapping let's use pointers.
We only need to convert the MIE and MSTATUS CSRs. With the exception of
MIP all of the other CSRs that swap with virtulsation changes are S-Mode
only, so we can just do a lazy switch. This because more challenging for
the
As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip
is 32-bit as well.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3a95c41428..4c342e7a79 100644
This patch series adds the RISC-V Hypervisor extension v0.4. This is the
latest draft spec of the Hypervisor extension.
The Hypervisor extension is disabled by default, so this series should
result in no changes to anyone using QEMU unless they enable the
extension. The extention can be enabled
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 24 ---
target/riscv/cpu_bits.h | 7
target/riscv/cpu_helper.c | 88 +++
3 files changed, 113 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d4368128..afb3e8579e 100644
--- a/target/riscv/cpu_helper.c
+++
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f767ad24be..471f23a1d0 100644
---
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 4
target/riscv/cpu_bits.h | 6 ++
target/riscv/cpu_helper.c | 23 +++
3 files changed, 33 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7f54fb8c87..0ef1ecb0e0 100644
---
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 124ed33ee4..7f54fb8c87 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
#define RVC RV('C')
#define RVS RV('S')
On 8/21/19 9:28 AM, Georg Kotheimer wrote:
The size of the FPU registers depends solely on the floating point
extensions supported by the target architecture.
However, in the previous implementation the floating point register
size was derived from whether the target architecture is 32-bit or
On 8/23/19 11:36 AM, Tony Nguyen wrote:
> The fast path is taken when TLB_FLAGS_MASK is all zero.
>
> TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,
> there are no other side effects.
>
> Signed-off-by: Tony Nguyen
> Reviewed-by: Richard Henderson
> ---
>
The current approach to capture the Python version is fragile, as it
was demonstrated by a very specific build of Python 3 on Fedora 29
that, under non-interactive shells would print multiline version
information.
The (badly) stripped version output would be sent to config-host.mak,
producing bad
Hi
On Fri, Aug 23, 2019 at 8:41 PM Daniel P. Berrangé wrote:
>
> This is ostensibly about adding docs for the g_autofree/g_autoptr
> macros. As part of doing that, however, the existing HACKING doc
> is merged into the CODING_STYLE doc and the text is converted to
> markdown with a table of
On 8/23/19 9:40 AM, Eric Blake wrote:
> Allow plugins to affect the handling of the new NBD_CMD_FLAG_FAST_ZERO
> flag, then update affected plugins. In particular, in-memory plugins
> are always fast; the full plugin is better served by omitting .zero
> and relying on .pwrite fallback; nbd takes
Patchew URL:
https://patchew.org/QEMU/20190823194927.23278-1-dmitry.fomic...@wdc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v5 0/4] virtio/block: handle zoned backing devices
Message-id:
Thanks for splitting this. The good news is that most of these devices
actually need _not_ be target-endian. Comments are inline.
Paolo
On 23/08/19 20:56, Tony Nguyen wrote:
> diff --git a/hw/audio/Makefile.objs b/hw/audio/Makefile.objs
> index 63db383709..13133b412d 100644
> ---
On 8/23/19 11:39 AM, Daniel P. Berrangé wrote:
> Document the use of g_autofree and g_autoptr in glib for automatic
> freeing of memory, or other resource cleanup (eg mutex unlocking).
>
> Signed-off-by: Daniel P. Berrangé
> ---
> CODING_STYLE.md | 101
Added a new boolean argument to blkconf_apply_backend_options()
to let the common block code know whether the chosen block
backend can handle zoned block devices or not.
blkconf_apply_backend_options() then sets BLK_PERM_SUPPORT_ZONED
permission accordingly. The raw code can then use this
Patchew URL:
https://patchew.org/QEMU/20190823192226.21154-1-dmitry.fomic...@wdc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v4 0/4] virtio/block: handle zoned backing devices
Message-id:
The purpose of this patch is to recognize a zoned block device (ZBD)
when it is opened as a raw file. The new code initializes the zoned
model propery introduced by the previous commit.
This commit is Linux-specific as it gets the Zoned Block Device Model
value (none/host-managed/host-aware) from
Patchew URL: https://patchew.org/QEMU/cover.1566467963.git.tony.ngu...@bt.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [RFC PATCH 00/17] Declare device little or big endian
Message-id:
Ping... Any objections to merging this patchset? Ask me if you are not
sure how to validate these patches without having the hardware :)
Currently, attaching zoned block devices (i.e., storage devices
compliant to ZAC/ZBC standards) using several virtio methods doesn't
work properly as zoned
This commit adds Zoned Device Model (as defined in T10 ZBC and
T13 ZAC standards) as a block driver property, along with some
useful access functions.
A new backend driver permission, BLK_PERM_SUPPORT_ZONED, is also
introduced. Only the drivers having this permission will be allowed
to open zoned
Abort opening a zoned device as a raw file in case the chosen
block backend driver lacks proper support for this type of
storage.
Signed-off-by: Dmitry Fomichev
---
block/file-posix.c | 14 ++
hw/block/fdc.c | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git
device_endian has been made redundant by MemOp.
Signed-off-by: Tony Nguyen
---
include/exec/memory.h | 3 ---
memory.c | 19 +--
memory_ldst.inc.c | 18 ++
3 files changed, 7 insertions(+), 33 deletions(-)
diff --git a/include/exec/memory.h
memory_region_big_endian is no longer useful now we are consistently
using MemOp for endianness.
Signed-off-by: Tony Nguyen
---
memory.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/memory.c b/memory.c
index ee7559a18c..b647a8d3dd 100644
--- a/memory.c
+++
Simplify code with MemOp short hand for host endianness, 0.
typedef enum MemOp {
/* snip */
#ifdef HOST_WORDS_BIGENDIAN
MO_LE= MO_BSWAP,
MO_BE= 0,
#else
MO_LE= 0,
MO_BE= MO_BSWAP,
#endif
/* snip */
};
Signed-off-by: Tony Nguyen
---
Simplify endianness comparisons with consistent use of the more
expressive MemOp.
Suggested-by: Richard Henderson
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
Acked-by: David Gibson
---
exec.c | 8 +++
hw/adc/stm32f2xx_adc.c | 2 +-
Simplify endianness comparisons with consistent use of the more
expressive MemOp.
Suggested-by: Richard Henderson
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
Acked-by: David Gibson
---
hw/audio/cs4231.c | 2 +-
hw/audio/milkymist-ac97.c | 2 +-
hw/char/escc.c
device_endian has been made redundant by MemOp.
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
---
include/exec/cpu-common.h | 8
1 file changed, 8 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 01a29ba571..7eeb78c48b 100644
---
Simplify endianness comparisons with consistent use of the more
expressive MemOp.
Suggested-by: Richard Henderson
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
Acked-by: David Gibson
---
hw/char/serial.c | 2 +-
include/exec/memory.h| 6 +++---
Preparation to replace device_endian with MemOp.
Mapping device_endian onto MemOp limits behaviour changes to this
relatively smaller patch.
The next patch will replace all device_endian usages with the
equivalent MemOp. That patch will be large but have no behaviour
changes.
A subsequent patch
This series deletes endian related enum, converter, and macro which have been
made redundant by MemOp being pushed down from TCG into the memory API.
This clean up was split out from an earlier series which collapsed byte swaps
along the I/O path.
Based-on:
[PATCH v9 00/20] Invert Endian
This commit adds Zoned Device Model (as defined in T10 ZBC and
T13 ZAC standards) as a block driver property, along with some
useful access functions.
A new backend driver permission, BLK_PERM_SUPPORT_ZONED, is also
introduced. Only the drivers having this permission will be allowed
to open zoned
On 8/23/19 11:39 AM, Daniel P. Berrangé wrote:
> The split of information between the two docs is rather arbitary and
> unclear. It is simpler for contributors if all the information is in
> one file.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> CODING_STYLE.md | 262
Ping... Any objections to merging this patchset? Ask me if you are not
sure how to validate these patches without having the hardware :)
Currently, attaching zoned block devices (i.e., storage devices
compliant to ZAC/ZBC standards) using several virtio methods doesn't
work properly as zoned
Added a new boolean argument to blkconf_apply_backend_options()
to let the common block code know whether the chosen block
backend can handle zoned block devices or not.
blkconf_apply_backend_options() then sets BLK_PERM_SUPPORT_ZONED
permission accordingly. The raw code can then use this
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
The purpose of this patch is to recognize a zoned block device (ZBD)
when it is opened as a raw file. The new code initializes the zoned
model propery introduced by the previous commit.
This commit is Linux-specific as it gets the Zoned Block Device Model
value (none/host-managed/host-aware) from
Abort opening a zoned device as a raw file in case the chosen
block backend driver lacks proper support for this type of
storage.
Signed-off-by: Dmitry Fomichev
---
block/file-posix.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/block/file-posix.c b/block/file-posix.c
The purpose of this patch is to recognize a zoned block device (ZBD)
when it is opened as a raw file. The new code initializes the zoned
model propery introduced by the previous commit.
This commit is Linux-specific as it gets the Zoned Block Device Model
value (none/host-managed/host-aware) from
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
This commit adds Zoned Device Model (as defined in T10 ZBC and
T13 ZAC standards) as a block driver property, along with some
useful access functions.
A new backend driver permission, BLK_PERM_SUPPORT_ZONED, is also
introduced. Only the drivers having this permission will be allowed
to open zoned
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
On 8/23/19 11:36 AM, Tony Nguyen wrote:
> Preparation for collapsing the two byte swaps adjust_endianness and
> handle_bswap into the former.
>
> Call memory_region_dispatch_{read|write} with endianness encoded into
> the "MemOp op" operand.
>
> This patch does not change any behaviour as
>
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
On 8/23/19 11:36 AM, Tony Nguyen wrote:
> Now that MemOp has been pushed down into the memory API, and
> callers are encoding endianness, we can collapse byte swaps
> along the I/O path into the accelerator and target independent
> adjust_endianness.
>
> Collapsing byte swaps along the I/O path
This series is an attempt to re-declare devices with DEVICE_NATIVE_ENDIAN as
DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN.
This clean up was split out from an earlier series which collapsed byte swaps
along the I/O path.
On Wed, 7 Aug 2019 at 12:42, Paolo Bonzini wrote:
> On 07/08/19 10:31,
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
Device realizing code with MemorRegionOps endianness as
DEVICE_NATIVE_ENDIAN is not common code.
Corrected devices were identified by making the declaration of
DEVICE_NATIVE_ENDIAN conditional upon NEED_CPU_H and then listing
what failed to compile.
Signed-off-by: Tony Nguyen
---
On 8/23/19 5:25 AM, tony.ngu...@bt.com wrote:
> Frustratingly, I keep getting blocked.
Whee! They have all arrived and applied correctly.
Thanks for your persistence.
r~
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
Block drivers should let their .bdrv_co_create() implementation return a
non-negative value to indicate success. However, jobs should return
exactly 0. Thus, we need to translate positive return values to 0 in
blockdev_create_run().
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Reitz
---
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
On 8/23/19 1:48 PM, Wouter Verhelst wrote:
> On Fri, Aug 23, 2019 at 09:34:26AM -0500, Eric Blake wrote:
>> +- bit 4, `NBD_CMD_FLAG_FAST_ZERO`; valid during
>> + `NBD_CMD_WRITE_ZEROES`. If set, but the server cannot perform the
>> + write zeroes any faster than it would for an equivalent
>> +
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
On Fri, Aug 23, 2019 at 09:34:26AM -0500, Eric Blake wrote:
> +- bit 4, `NBD_CMD_FLAG_FAST_ZERO`; valid during
> + `NBD_CMD_WRITE_ZEROES`. If set, but the server cannot perform the
> + write zeroes any faster than it would for an equivalent
> + `NBD_CMD_WRITE`,
One way of fulfilling the letter
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
On Thu, Aug 22, 2019 at 10:29 PM Bin Meng wrote:
>
> At present each hart's hartid in a RISC-V hart array is assigned
> the same value of its index in the hart array. But for a system
> that has multiple hart arrays, this is not the case any more.
>
> Add a new "hartid-base" property so that
Signed-off-by: Max Reitz
---
tests/qemu-iotests/266 | 182 +
tests/qemu-iotests/266.out | 107 ++
tests/qemu-iotests/group | 1 +
3 files changed, 290 insertions(+)
create mode 100755 tests/qemu-iotests/266
create mode 100644
For each device declared with DEVICE_NATIVE_ENDIAN, find the set of
targets from the set of target/hw/*/device.o.
If the set of targets are all little or all big endian, re-declare
the device endianness as DEVICE_LITTLE_ENDIAN or DEVICE_BIG_ENDIAN
respectively.
This *naive* deduction may result
Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
---
target/sparc/mmu_helper.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git
This bit configures endianness of PCI MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.
Tested working on OpenBSD.
Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =)
Signed-off-by: Tony Nguyen
Reviewed-by:
Jobs are expected to return 0 on success. .bdrv_co_create() on the
other hand is a block layer function, and as such returns a non-negative
value on success.
blockdev_create_run() should translate between the two (patch 1).
Without patch 1, blockdev-create is likely to fail for VPC images.
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Suggested-by: Richard Henderson
Signed-off-by: Tony Nguyen
Reviewed-by: Richard
On Thu, Aug 22, 2019 at 10:16 PM Bin Meng wrote:
>
> It is not useful if we only have one management CPU.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair Francis
Ah, I jumped the gun with patch 16. This should be before patch 16,
otherwise patch 16 is fine.
Alistair
>
> ---
>
> Changes
The fast path is taken when TLB_FLAGS_MASK is all zero.
TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,
there are no other side effects.
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
---
include/exec/cpu-all.h | 10 --
1 file changed, 8 insertions(+),
1 - 100 of 369 matches
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