On Mon, Oct 07, 2019 at 10:40:56AM +0200, Cédric Le Goater wrote:
> When an interrupt can not be presented to a vCPU, the XIVE presenter
> updates the Interrupt Pending Buffer of the XIVE NVT if backlog is
> activated in the END.
>
> Signed-off-by: Cédric Le Goater
This commit message doesn't
On Thu, Oct 10, 2019 at 12:29:45PM +0530, Ganesh Goudar wrote:
> From: Aravinda Prasad
>
> Introduce the KVM capability KVM_CAP_PPC_FWNMI so that
> the KVM causes guest exit with NMI as exit reason
> when it encounters a machine check exception on the
> address belonging to a guest. Without this
On Monday, October 14, 2019, Richard Henderson
wrote:
> On 10/13/19 4:53 PM, Aleksandar Markovic wrote:
> > Just for the sake of being punctual, may I ask you to add "Tested-by:"
> for Mark
> > Cave-Ayland, and "Reviewed-by:" for myself to all 22 ppc host patches,
> as it
> > was indicated in
On Sun, Oct 13, 2019 at 08:31:59PM -0700, Richard Henderson wrote:
> On 10/13/19 5:25 PM, David Gibson wrote:
> >
> > Uh.. do you want me to merge this? Probably best to CC me if you
> > do.. otherwise I'm likely to miss it.
>
> No thanks, it's now in a tcg pull request.
Ok, cool.
--
David
On 10/13/19 5:25 PM, David Gibson wrote:
>
> Uh.. do you want me to merge this? Probably best to CC me if you
> do.. otherwise I'm likely to miss it.
No thanks, it's now in a tcg pull request.
r~
On 10/13/19 4:53 PM, Aleksandar Markovic wrote:
> Just for the sake of being punctual, may I ask you to add "Tested-by:" for
> Mark
> Cave-Ayland, and "Reviewed-by:" for myself to all 22 ppc host patches, as it
> was indicated in the responses to the last version of the ppc host series?
I did
On Sun, Oct 13, 2019 at 07:38:04PM -0700, Richard Henderson wrote:
>On 10/13/19 6:01 PM, Wei Yang wrote:
>>> No, please.
>>>
>>> (1) The compiler does not know that qemu_*host_page_size is a power of 2,
>>> and
>>> will generate a real division at runtime. The same is true for
>>>
On Mon, Aug 19, 2019 at 03:23:16PM -0600, Alex Williamson wrote:
> On Mon, 29 Jul 2019 15:15:29 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Fri, Jul 26, 2019 at 06:55:27PM -0600, Alex Williamson wrote:
> > > Please see patch 1/ for the motivation and utility of this series.
> > > This v1
On 10/13/19 6:01 PM, Wei Yang wrote:
>> No, please.
>>
>> (1) The compiler does not know that qemu_*host_page_size is a power of 2, and
>> will generate a real division at runtime. The same is true for
>> TARGET_PAGE_SIZE when TARGET_PAGE_BITS_VARY.
>>
>
> Confused
>
> The definition of
Really appreciate your advice. Some comments below:
On 2019/10/12 3:06, John Snow wrote:
On 10/11/19 9:22 AM, Guoheyi wrote:
Hi folks,
We observed Linux on VM occasionally (at very low rate) got soft lockup
when a remote cdrom is attached. The guest hangs up at below call trace:
That's
On Sun, Oct 13, 2019 at 11:56:35AM -0400, Richard Henderson wrote:
>On 10/12/19 10:11 PM, Wei Yang wrote:
>> Use ROUND_UP() to define, which is a little bit easy to read.
>>
>> Signed-off-by: Wei Yang
>> ---
>> include/exec/cpu-all.h | 7 +++
>> 1 file changed, 3 insertions(+), 4
Uh.. do you want me to merge this? Probably best to CC me if you
do.. otherwise I'm likely to miss it.
On Mon, Sep 30, 2019 at 01:21:03PM -0700, Richard Henderson wrote:
> Changes since v6:
> * The have_foo tests have been split so that VSX is not
> combined with ISA revision.
> * The
in the Git repository at:
>
> https://github.com/rth7680/qemu.git tags/pull-tcg-20191013
>
> for you to fetch changes up to d2f86bba6931388e275e8eb4ccd1dbcc7cae6328:
>
> cpus: kick all vCPUs when running thread=single (2019-10-07 14:08:58
> -0400)
>
> -
On Sun, Oct 13, 2019 at 11:56:35AM -0400, Richard Henderson wrote:
> On 10/12/19 10:11 PM, Wei Yang wrote:
> > Use ROUND_UP() to define, which is a little bit easy to read.
> >
> > Signed-off-by: Wei Yang
> > ---
> > include/exec/cpu-all.h | 7 +++
> > 1 file changed, 3 insertions(+), 4
Patchew URL:
https://patchew.org/QEMU/20191013222544.3679-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL 00/23] tcg patch queue
Type: series
Message-id:
From: Alex Bennée
qemu_cpu_kick is used for a number of reasons including to indicate
there is work to be done. However when thread=single the old
qemu_cpu_kick_rr_cpu only advanced the vCPU to the next executing one
which can lead to a hang in the case that:
a) the kick is from outside the
The VSX instruction set instructions include double-word loads and
stores, double-word load and splat, double-word permute, and bit
select. All of which require multiple operations in the Altivec
instruction set.
Because the VSX registers map %vsr32 to %vr0, and we have no current
intention or
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.opc.h | 8 +++
tcg/ppc/tcg-target.inc.c | 113 ++-
3 files changed, 121 insertions(+), 2
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++--
2 files changed, 57
These new instructions are conditional only on MSR.VEC and
are thus part of the Altivec instruction set, and not VSX.
This includes negation and compare not equal.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c |
Add various bits and peaces related mostly to load and store
operations. In that context, logic, compare, and splat Altivec
instructions are used, and, therefore, the support for emitting
them is included in this patch too.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
These new instructions are conditional on MSR.FP when TX=0 and
MSR.VEC when TX=1. Since we only care about the Altivec registers,
and force TX=1, we can consider these to be Altivec instructions.
Since Altivec is true for any use of vector types, we only need
test have_isa_2_07.
This includes
I tried with `--enable-gtk` and it hangs as well.
Using gtk3 build from MacPorts with `+quartz`. Now, this may be a systemwide
problem with Gtk, I am yet to test other Gtk apps on Catalina.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to
These new instructions are conditional only on MSR.VSX and
are thus part of the VSX instruction set, and not Altivec.
This includes double-word loads and stores.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 11 +++
1 file changed, 11
These new instructions are conditional only on MSR.VEC and
are thus part of the Altivec instruction set, and not VSX.
This includes lots of double-word arithmetic and a few extra
logical operations.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h
These new instructions are conditional on MSR.VEC for TX=1,
so we can consider these Altivec instructions.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff
Introduce all of the flags required to enable tcg backend vector support,
and a runtime flag to indicate the host supports Altivec instructions.
For now, do not actually set have_isa_altivec to true, because we have not
yet added all of the code to actually generate all of the required insns.
This is only used for 32-bit hosts.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index d4b3354626..8a508136ce 100644
---
These new instructions are a mix of those like LXSD that are
only conditional only on MSR.VEC and those like LXV that are
conditional on MSR.VEC for TX=1. Thus, in the end, we can
consider all of these as Altivec instructions.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 20
1 file changed, 20 insertions(+)
diff --git
Previously we've been hard-coding knowledge that Power7 has ISEL, but
it was an optional instruction before that. Use the AT_HWCAP2 bit,
when present, to properly determine support.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 17
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 2 +-
Now that we have implemented the required tcg operations,
we can enable detection of host vector support.
Tested-by: Mark Cave-Ayland (PPC32)
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 4
1 file changed, 4 insertions(+)
diff --git
Introduce macros VRT(), VRA(), VRB(), VRC() used for encoding
elements of Altivec instructions.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c
This is identical to have_isa_2_06, so replace it.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index
Introduce macro VX4() used for encoding Altivec instructions.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 9d678c3bf1..8dc5455600
Introduce an enum to hold base < 2.06 < 3.00. Use macros to
preserve the existing have_isa_2_06 and have_isa_3_00 predicates.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 12 ++--
tcg/ppc/tcg-target.inc.c | 8
2 files
Altivec supports 32 128-bit vector registers, whose names are
by convention v0 through v31.
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
tcg/ppc/tcg-target.h | 11 -
tcg/ppc/tcg-target.inc.c | 88 +---
2 files changed, 65
The following changes since commit 9e5319ca52a5b9e84d55ad9c36e2c0b317a122bb:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2019-10-04 18:32:34 +0100)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-tcg-20191013
for you
The BDRV_REQ_NO_FALLBACK flag means that an operation should only be
performed if it can be offloaded or otherwise performed efficiently.
However a misaligned write request requires a RMW so we should return
an error and let the caller decide how to proceed.
This hits an assertion since commit
This commit adds support for 5.1 and 7.1 audio playback. This commit
adds a new property to usb-audio:
* multi=on|off
Whether to enable the 5.1 and 7.1 audio support. When off (default)
it continues to emulate the old stereo-only device. When on, it
emulates a slightly different audio
Signed-off-by: Kővágó, Zoltán
---
audio/paaudio.c | 50 -
1 file changed, 45 insertions(+), 5 deletions(-)
diff --git a/audio/paaudio.c b/audio/paaudio.c
index d195b1caa8..6ff0d17537 100644
--- a/audio/paaudio.c
+++ b/audio/paaudio.c
@@ -338,17
This assumption is no longer true when mixeng is turned off.
Signed-off-by: Kővágó, Zoltán
---
hw/usb/dev-audio.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/hw/usb/dev-audio.c b/hw/usb/dev-audio.c
index ae42e5a2f1..74c99b1f12 100644
---
The bit shifting trick worked because the number of bytes per frame was
always a power-of-two (since QEMU only supports mono, stereo and 8, 16
and 32 bit samples). But if we want to add support for surround sound,
this no longer holds true.
Signed-off-by: Kővágó, Zoltán
---
audio/alsaaudio.c
Which currently only means removing some checks. Old code won't require
more than two channels, but new code will need it.
Signed-off-by: Kővágó, Zoltán
---
audio/alsaaudio.c | 7 ---
audio/audio.c | 2 +-
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/audio/alsaaudio.c
With stereo playback, they need about 375 minutes of continuous audio
playback to overflow, which is usually not a problem (as stopping and
later resuming playback resets the counters). But with 7.1 audio, they
only need about 95 minutes to overflow.
After the overflow, the buf->prod %
Signed-off-by: Kővágó, Zoltán
---
audio/audio.c | 30 ++
audio/audio.h | 10 ++
audio/audio_int.h | 4 ++--
audio/paaudio.c| 20
audio/spiceaudio.c | 14 --
5 files changed, 54 insertions(+), 24 deletions(-)
This will allow us to disable mixeng when we use a decent backend.
Disabling mixeng have a few advantages:
* we no longer convert the audio output from one format to another, when
the underlying audio system would just convert it to a third format.
We no longer convert, only the underlying
Implementation of the previously added mixing-engine option.
Signed-off-by: Kővágó, Zoltán
---
Notes:
Changes from v4:
* audio_pcm_hw_add_* always returns a new HW (or fails) when not using
mixeng
audio/audio.c | 70 ++
Hi,
I've updated my mixeng-free patches. This time it's only documentation
fixes in the first patch, otherwise it's identical to v5.
Regards,
Zoltan
Kővágó, Zoltán (10):
audio: add mixing-engine option (documentation)
audio: make mixeng optional
paaudio: get/put_buffer functions
This lets us avoid some buffer copying when using mixeng.
Signed-off-by: Kővágó, Zoltán
---
audio/paaudio.c | 83 +
1 file changed, 83 insertions(+)
diff --git a/audio/paaudio.c b/audio/paaudio.c
index ed31f863f7..6ccdf31415 100644
---
I am also affected by this after upgrading to 10.15 Catalina.
I experience the same behavior using `qemu-system-x86_64`, but I can't
confirm whether other systems are also affected.
Building with SDL also fixed it for me so far:
* `brew edit`
* add `depends_on "sdl2"` among other dependencies
*
Hello dear team
I'm working on Qemu's source code, mainly on Qemu's CPU. I need you to
enlighten me on a number of points
1- How does Qemu emulate its different processors, Can I have a
diagram that describes how Qemu emulates?
2- How is the Qemu x86 CPU implemented?
3- Can I bring out a diagram?
Patchew URL:
https://patchew.org/QEMU/1570991178-5511-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v4 0/8] target/mips: Misc cleanups for September/October 2019
Type: series
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 21 +-
target/mips/msa_helper.c | 768 +--
target/mips/translate.c | 76 -
3 files changed, 496
From: Aleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic
---
target/mips/op_helper.c | 1010 +++
1 file changed, 663 insertions(+), 347 deletions(-)
diff --git
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 30 +++-
target/mips/msa_helper.c | 426 +--
target/mips/translate.c | 95 +--
3 files
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 20 ++-
target/mips/msa_helper.c | 320 ++-
target/mips/translate.c | 76 +--
3 files
From: Aleksandar Markovic
Aleksandar Rikalo wishes to change his primary mail address for QEMU.
Some minor line order is corrected in .mailmap to be alphabetical,
too.
Signed-off-by: Aleksandar Markovic
---
.mailmap| 5 +++--
MAINTAINERS | 18 +-
2 files changed, 12
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 10 +++-
target/mips/msa_helper.c | 131 ++-
target/mips/translate.c | 32 +---
3 files
From: Aleksandar Markovic
Mostly cosmetic changes.
v3->v4:
- added patches 7 and 8
v2->v3:
- removed all patches that were already integrated
- patches 1 and 2 are improved from v2
- added patches 3-6
v1->v2:
- minor corrections to satisfy reviews
- added several more patches
From: Aleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.c | 128 +++
1 file changed, 78 insertions(+), 50 deletions(-)
diff --git a/target/mips/helper.c
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 11 +++-
target/mips/msa_helper.c | 163 ++-
target/mips/translate.c | 38 +--
3 files
On 10/12/19 10:11 PM, Wei Yang wrote:
> There are three page size in qemu:
>
> real host page size
> host page size
> target page size
>
> All of them have dedicate variable to represent. For the last two, we
> use the same form in the whole qemu project, while for the first one we
> use
On 10/12/19 10:11 PM, Wei Yang wrote:
> Use ROUND_UP() to define, which is a little bit easy to read.
>
> Signed-off-by: Wei Yang
> ---
> include/exec/cpu-all.h | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
>
Public bug reported:
I have downloaded the latest stable source tarball 4.1.0 and compiled it
(i386-softmmu target).
After opening a black window, QEMU hangs (spinning beach ball).
When building with `--disable-cocoa --enable-sdl`, display seems to work fine.
The same happened when I tried to
Matthew Kilgore, le jeu. 03 oct. 2019 23:53:38 -0400, a ecrit:
> The current code does not correctly pass the color pair information to
> setcchar(), it instead always passes zero. This results in the curses
> output always being in white on black.
>
> This patch fixes this by using PAIR_NUMBER()
Matthew Kilgore, le jeu. 03 oct. 2019 23:53:37 -0400, a ecrit:
> The curses API provides the A_ATTRIBUTES and A_CHARTEXT bit masks for
> getting the attributes and character parts of a chtype, respectively. We
> should use provided constants instead of using 0xff.
>
> Signed-off-by: Matthew
Hello dear team
I'm working on Qemu's source code, mainly on Qemu's CPU. I need you to
enlighten me on a number of points
1- How does Qemu emulate its different processors, Can I have a diagram
that describes how Qemu emulates?
2- How is the Qemu x86 CPU implemented?
3- Can I bring out a diagram?
On Sun, Oct 13, 2019 at 10:11:45AM +0800, Wei Yang wrote:
> There are three page size in qemu:
>
> real host page size
> host page size
> target page size
>
> All of them have dedicate variable to represent. For the last two, we
> use the same form in the whole qemu project, while for the
On Sun, Oct 13, 2019 at 10:11:44AM +0800, Wei Yang wrote:
> Use ROUND_UP() to define, which is a little bit easy to read.
>
> Signed-off-by: Wei Yang
Reviewed-by: David Gibson
> ---
> include/exec/cpu-all.h | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git
lantianyu1...@gmail.com writes:
> From: Tianyu Lan
>
(Please also Cc: Roman on you Hyper-V related submissions to QEMU who's
known to be a great reviewer)
> Hyper-V direct tlb flush targets KVM on Hyper-V guest.
> Enable direct TLB flush for its guests meaning that TLB
> flush hypercalls are
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 174 +
1 file changed, 174 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 19540634df..21ba6004ee
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 1123
1 file changed, 1123 insertions(+)
diff --git a/target/avr/translate.c
This includes:
- ADD, ADC, ADIW
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 811 +
1 file changed, 811 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 53c9892a60..3eaa3e5099 100644
---
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 21ba6004ee..6d4a023ff9 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
Acked-by: Igor Mammedov
---
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 542 +
1 file changed, 542
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
---
target/avr/insn.decode | 175 +
1 file changed, 175 insertions(+)
create mode 100644 target/avr/insn.decode
diff --git
This includes:
- TCG translations for each instruction
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 132 +
1 file changed, 132 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c
Stubs for unimplemented instructions and helpers for instructions that need to
interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex
peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to
generate wake interrupts.
Memory
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 21ba6004ee..6d4a023ff9 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 132 +
1 file changed, 132 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c b/target/avr/translate.c
new file mode 100644
index 00..53c9892a60
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support
On Sun, Oct 13, 2019 at 10:11:43AM +0800, Wei Yang wrote:
> Patch 1 simplify the definition of xxx_PAGE_ALIGN.
> Patch 2 replaces getpagesize() with qemu_real_host_page_size. This one touch a
> volume of code. If some point is not correct, I'd appreciate your
> notification.
Pls queue at the
On Sun, Oct 13, 2019 at 10:11:45AM +0800, Wei Yang wrote:
> There are three page size in qemu:
>
> real host page size
> host page size
> target page size
>
> All of them have dedicate variable to represent. For the last two, we
> use the same form in the whole qemu project, while for the
On Sun, Oct 13, 2019 at 10:11:44AM +0800, Wei Yang wrote:
> Use ROUND_UP() to define, which is a little bit easy to read.
>
> Signed-off-by: Wei Yang
Reviewed-by: Michael S. Tsirkin
> ---
> include/exec/cpu-all.h | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git
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