For lld, --image-base is the preferred way to set the base address.
lld does not actually implement -Ttext-segment, but treats it as an alias for
-Ttext. -Ttext-segment=0x6000 combined with --no-rosegment can
create a 1.6GB executable.
Fix the problem by using --image-base for lld. GNU ld and
On 10/8/19 8:38 AM, Daniel P. Berrangé wrote:
On Tue, Oct 08, 2019 at 08:28:16AM -0500, Eric Blake wrote:
On 10/8/19 4:40 AM, Vladimir Sementsov-Ogievskiy wrote:
08.10.2019 12:24, Daniel P. Berrangé wrote:
On Mon, Oct 07, 2019 at 02:48:40PM -0500, Eric Blake wrote:
One benefit of --pid-file
CCing Jiri.
On Fri, Nov 15, 2019 at 09:08:37AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 12, 2019 at 11:48:11AM +0100, Cornelia Huck wrote:
> > Add 5.0 machine types for arm/i440fx/q35/s390x/spapr.
> >
> > For i440fx and q35, unversioned cpu models are still translated
> > to -v1; I'll
The warning will be enabled by default in clang 10. It is not available for
clang <= 9.
qemu/migration/migration.c:2038:24: error: implicit conversion from 'long' to
'double' changes value from 9223372036854775807 to 9223372036854775808
[-Werror,-Wimplicit-int-float-conversion]
...
On Fri, Nov 15, 2019 at 04:55:21PM +0100, Greg Kurz wrote:
> There's a recurring pattern in the code where a const link is added to a
> newly instanciated object and the link is then used in the object's realize
> function to keep a pointer to the QOM entity which the link points to.
>
> void
> On Fri, 15 Nov 2019 14:32:47 +
> gengdongjiu wrote:
>
> > > > + */
> > > > +static void acpi_ghes_build_notify(GArray *table, const uint8_t
> > > > +type)
> > >
> > > typically format should be build_WHAT(), so
> > > build_ghes_hw_error_notification()
> > >
> > > And I'd move this out
I have been dragging my feet exposing my production VMs to a patched
4.1.0 TBH. I have now taken the opportunity to upgrade from 4.0.0 to a
4.1.0 with the fix patches applied. As expected, I can not produce any
image corruption with the reproducer I've been using all along. I will
now use it in
On Tue, Nov 12, 2019 at 07:20:38PM +0100, Philippe Mathieu-Daudé wrote:
> On 11/4/19 4:13 PM, Cleber Rosa wrote:
> > This acceptance test, validates that a full blown Linux guest can
> > successfully boot in QEMU. In this specific case, the guest chosen is
> > Fedora version 31.
> >
> > *
On Fri, Nov 08, 2019 at 05:42:14PM -0200, Wainer dos Santos Moschetta wrote:
>
> On 11/4/19 1:13 PM, Cleber Rosa wrote:
> > This acceptance test, validates that a full blown Linux guest can
> > successfully boot in QEMU. In this specific case, the guest chosen is
> > Fedora version 31.
> >
> >
On Thu, Nov 07, 2019 at 06:31:03PM -0200, Wainer dos Santos Moschetta wrote:
>
> On 11/4/19 1:13 PM, Cleber Rosa wrote:
> > Tests using the avocado.utils.vmimage library make use of qemu-img,
> > and because it makes sense to use the version matching the rest of the
> > source code, let's make
Peter Maydell writes:
> It's on my queue to review if nobody else gets to it first, but since
> we're in freeze right now it won't be landing til after the release
> happens (expected mid-December).
Thanks in advance! I'll get started pushing questions about the RISC-V
semihosting ABI into that
On Fri, Nov 15, 2019 at 11:33:06PM +0100, Laurent Vivier wrote:
> The following changes since commit 36609b4fa36f0ac934874371874416f7533a5408:
>
> Merge remote-tracking branch
> 'remotes/palmer/tags/palmer-for-master-4.2-sf1' into staging (2019-11-02
> 17:59:03 +)
>
> are available in
On Fri, Nov 08, 2019 at 02:13:02PM +0100, Philippe Mathieu-Daudé wrote:
> On 11/4/19 4:13 PM, Cleber Rosa wrote:
> > So that when binaries such as qemu-img are searched for, those in the
> > build tree will be favored. As a clarification, SRC_ROOT_DIR is
> > dependent on the location from where
On Tue, Nov 12, 2019 at 12:00:20PM -0200, Wainer dos Santos Moschetta wrote:
>
> On 11/11/19 8:49 PM, Cleber Rosa wrote:
> > On Thu, Nov 07, 2019 at 05:46:13PM -0200, Wainer dos Santos Moschetta wrote:
> > > On 11/4/19 1:13 PM, Cleber Rosa wrote:
> > > > So that when binaries such as qemu-img are
On Fri, Nov 15, 2019 at 05:03:51PM +0100, Greg Kurz wrote:
> It has no apparent user.
>
> Signed-off-by: Greg Kurz
Applied to ppc-for-5.0, thanks.
> ---
> hw/ppc/pnv.c |2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index d7130c3304f0..24bc3d5ab32b
From: David Gibson
We have to set the default model of all machine classes, not just for
the active one. Otherwise, "query-machines" will indicate the wrong
CPU model (e.g. "power9_v2.0-powerpc64-cpu" instead of
"host-powerpc64-cpu") as "default-cpu-type".
s390x already fixed this in de60a92e
From: Greg Kurz
SpaprInterruptControllerClass and PnvChipClass have an intc_create() method
that calls the appropriate routine, ie. icp_create() or xive_tctx_create(),
to establish the link between the VCPU and the presenter component of the
interrupt controller during realize.
There aren't any
From: Alexey Kardashevskiy
Since "spapr: Render full FDT on ibm,client-architecture-support" we build
the entire flatten device tree (FDT) twice - at the reset time and
when "ibm,client-architecture-support" (CAS) is called. The full FDT from
CAS is then applied on top of the SLOF internal
From: Laurent Vivier
With the Quadra 800 emulation, mos6522 timers processing can consume
until 70% of the host CPU time with an idle guest (I guess the problem
should also happen with PowerMac emulation).
On a recent system, it can be painless (except if you look at top), but
on an old host
From: Greg Kurz
CPU_FOREACH() can race with vCPU hotplug/unplug on sPAPR machines, ie.
we may try to print out info about a vCPU with a NULL presenter pointer.
Check that in order to prevent QEMU from crashing.
Signed-off-by: Greg Kurz
Message-Id:
From: Greg Kurz
When a VCPU gets connected to the XIVE interrupt controller, we add a
const link targetting the CPU object to the TCTX object. Similar links
are added to the ICP object when using the XICS interrupt controller.
As explained in :
* The caller must ensure that @target stays
The following changes since commit 36609b4fa36f0ac934874371874416f7533a5408:
Merge remote-tracking branch 'remotes/palmer/tags/palmer-for-master-4.2-sf1'
into staging (2019-11-02 17:59:03 +)
are available in the Git repository at:
https://github.com/vivier/qemu.git
On Thu, Nov 07, 2019 at 05:22:24PM -0200, Wainer dos Santos Moschetta wrote:
>
> On 11/4/19 1:13 PM, Cleber Rosa wrote:
> > This is related to the the differences in in-tree and out-of-tree
> > builds in QEMU. For simplification, means my build directory.
> >
> > Currently, by running a `make
On 11/15/19 11:08 AM, Vladimir Sementsov-Ogievskiy wrote:
14.11.2019 5:46, Eric Blake wrote:
Qemu as server currently won't accept export names larger than 256
bytes, nor create dirty bitmap names longer than 1023 bytes, so most
uses of qemu as client or server have no reason to get anywhere
Add a notification queue which will be used to send async notifications
for file lock availability.
Signed-off-by: Vivek Goyal
---
contrib/virtiofsd/fuse_i.h | 1 +
contrib/virtiofsd/fuse_virtio.c| 108 ++---
hw/virtio/vhost-user-fs-pci.c
We are emulating posix locks for guest using open file description locks
in virtiofsd. When any of the fd is closed in guest, we find associated
OFD lock fd (if there is one) and close it to release all the locks.
Assumption here is that there is no other thread using lo_inode_plock
structure or
Daemon specifies size of notification buffer needed and that should be done
using config space.
Only ->notify_buf_size value of config space comes from daemon. Rest of
it is filled by qemu device emulation code.
Signed-off-by: Vivek Goyal
---
contrib/virtiofsd/fuse_virtio.c| 26
Hi,
Here are RFC patches for adding a notification queue to virtio-fs to
send notifications from host to guest. It also has patches to support
remote posix locks which make use of this newly introduced notification
queue.
These patches apply on top of following.
As of now we don't support fcntl(F_SETLKW) and if we see one, we return
-EOPNOTSUPP.
Change that by accepting these requests and returning a reply immediately
asking caller to wait. Once lock is available, send a notification to
the waiter indicating lock is available.
Signed-off-by: Vivek Goyal
On 11/15/19 5:13 PM, Thomas Huth wrote:
On 15/11/2019 17.13, Paolo Bonzini wrote:
On 15/11/19 16:54, Thomas Huth wrote:
On 15/11/2019 16.54, Peter Maydell wrote:
On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
When CONFIG_IDE_ISA is disabled, compilation currently fails:
On 11/15/19 5:12 PM, Thomas Huth wrote:
On 15/11/2019 17.15, Peter Maydell wrote:
On Fri, 15 Nov 2019 at 16:08, Thomas Huth wrote:
On 15/11/2019 16.54, Peter Maydell wrote:
On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -78,7 +78,6 @@
On 11/15/19 4:47 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add the CRP as unimplemented thus avoiding bus errors when
> guests access these registers.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 2 ++
>
On 11/15/19 7:12 PM, no-re...@patchew.org wrote:
Patchew URL:
https://patchew.org/QEMU/20191115154734.26449-1-edgar.igles...@gmail.com/
This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can
Cc'ing Gerd (Audio)
On 11/15/19 4:56 PM, Sai Pavan Boddu wrote:
Fill the audio channel with required number of bytes to cover the
elapsed time. This prevents rate control reset, and avoids debug prints
like below
log:
Resetting rate control (65692 samples)
...
Resetting
Hi Colin,
I didn't read much if the details but I think it is clear.
Per request of IBM focal got -march=z13 but tcg has no emulation for some
of the instructions of this cpu.
That is the breakage that you are seeing and afaik there is nothing we can
do than waiting for qemu to grow that
On Fri, Nov 15, 2019 at 10:59 AM Sai Pavan Boddu
wrote:
>
> Fill the audio channel with required number of bytes to cover the
> elapsed time. This prevents rate control reset, and avoids debug prints
> like below
>
> log:
> Resetting rate control (65692 samples)
> ...
>
Patchew URL:
https://patchew.org/QEMU/20191115154734.26449-1-edgar.igles...@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
ps is showing QEMU is running as follows:
/usr/bin/qemu-system-s390x -name guest=ubuntu20.04-focal-s390x,debug-
threads=on -S -object
secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain-10-ubuntu20.04-focal-s3
/master-key.aes -machine s390-ccw-virtio-eoan,accel=tcg,usb=off,dump-
I've also seen in the dmesg log:
[ 287.624414] User process fault: interruption code 0007 ilc:3 in
libstdc++.so.6.0.28[3ffb3e0+21d000]
[ 288.991706] User process fault: interruption code 0007 ilc:3 in
libstdc++.so.6.0.28[3ff9008+21d000]
--
You received this bug notification because
On commit abf0bf998dcb John Snow moved some code out of __init__.py
to machine.py. kvm_available() remained in though. So on patch 01
I continue his work by creating a home for that method (the new
'accel' module). Honestly I was unsure about whether move the code
to any existing module or make a
Public bug reported:
Running qemu-system-s390x (1:4.0+dfsg-0ubuntu10) on an x86-64 Focal host
with an upgrade of a Eoan s390x VM to a Focal s390x is triggering random
breakage, for example:
sudo apt-get update && sudo apt-get dist-upgrade
...
...
Unpacking debianutils (4.9) over (4.8.6.3) ...
This adds a method to check if the tcg accelerator is enabled
in the QEMU binary.
Signed-off-by: Wainer dos Santos Moschetta
---
python/qemu/accel.py | 8
1 file changed, 8 insertions(+)
diff --git a/python/qemu/accel.py b/python/qemu/accel.py
index 1978fbee4e..513904d46d 100644
---
Since commit cbe6d6365a48 the command `qemu -accel help` returns
the list of accelerators enabled in the QEMU binary. This adds
the list_accel() method which return that same list.
Signed-off-by: Wainer dos Santos Moschetta
---
python/qemu/accel.py | 20
1 file changed, 20
This creates the 'accel' Python module to be the home for
utilities that deal with accelerators. Also moved kvm_available()
from __init__.py to this new module.
Signed-off-by: Wainer dos Santos Moschetta
---
python/qemu/__init__.py | 20 +---
python/qemu/accel.py| 36
Currently kvm_available() checks for the presence of kvm module
and, if target and host arches don't mismatch. This patch adds
an 3rd checking: if QEMU binary was compiled with kvm
support.
Signed-off-by: Wainer dos Santos Moschetta
---
python/qemu/accel.py | 27 +--
1
On 11/15/19 8:14 AM, Vladimir Sementsov-Ogievskiy wrote:
This brings async request handling and block-status driven chunk sizes
to backup out of the box, which improves backup performance.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
+++ b/qapi/block-core.json
@@ -1455,6 +1455,12 @@
#
On 11/15/19 5:06 PM, Andrew Jones wrote:
>> bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
>> -return bitnum == vq - 1 ? 0 : bitnum + 1;
>> +
>> +/* We always have vq == 1 present in sve_vq_map. */
>
> This is true with TCG and 99.% likely to be true with KVM...
Eh? It's
Patchew URL:
https://patchew.org/QEMU/20191115141444.24155-1-vsement...@virtuozzo.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [RFC 00/24] backup performance: block_status + async
Type: series
Message-id:
15.11.2019 20:30, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20191115141444.24155-1-vsement...@virtuozzo.com/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Subject: [RFC 00/24] backup performance:
Instead of passing a pointer to memory now just extend the GByteArray
to all the read register helpers. They can then safely append their
data through the normal way. We don't bother with this abstraction for
write registers as we have already ensured the buffer being copied
from is the correct
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 10 -
target/arm/gdbstub.c | 99
target/arm/helper.c | 69 --
3 files changed, 173 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
Rather than having a static buffer replace str_buf with a GString
which we know can grow on demand. Convert the internal functions to
take a GString instead of a char * and length.
Signed-off-by: Alex Bennée
---
gdbstub.c | 194 --
1 file
This is described as optional but I'm not convinced of the numbering
when multiple target fragments are sent.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 2 +-
target/arm/gdbstub.c | 16 ++--
target/arm/helper.c | 2 +-
3 files changed, 12 insertions(+), 8 deletions(-)
We will want to generate similar dynamic XML for gdbstub support of
SVE registers (the upstream doesn't use XML). To that end lightly
rename a few things to make the distinction.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 20 +---
target/arm/gdbstub.c | 30
This is in preparation for further re-factoring of the register API
with the rest of the code. Theoretically the read register function
could overwrite the MAX_PACKET_LENGTH buffer although currently all
registers are well within the size range.
Signed-off-by: Alex Bennée
---
gdbstub.c | 52
Signed-off-by: Alex Bennée
---
include/exec/gdbstub.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 08363969c14..a898a2af990 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -102,6 +102,14 @@ static inline int
We only have one GDBState which should be allocated at the time we
process any commands. This will make further clean-up a bit easier.
Signed-off-by: Alex Bennée
---
gdbstub.c | 307 +++---
1 file changed, 177 insertions(+), 130 deletions(-)
diff
This is cleaner than poking memory directly and will make later
clean-ups easier.
Signed-off-by: Alex Bennée
---
target/m68k/helper.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index
Hi,
This RFC is for supporting SVE registers in QEMU's gdbstub.
However on the way to that there is a bunch of re-factoring to the
core gdbstub code to remove some of the hardcoded size limits from its
various buffers. By using dynamically sized buffers we are less likely
to trip up as we
We use g_new0() as it is the preferred form for such allocations. We
can also ensure that gdbserver_state is reset in one place.
Signed-off-by: Alex Bennée
---
gdbstub.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index
This is cleaner than poking memory directly and will make later
clean-ups easier.
Signed-off-by: Alex Bennée
---
target/arm/helper.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index be67e2c66d6..bd821931b3d
15.11.2019 19:33, Eric Blake wrote:
> On 11/15/19 9:47 AM, Vladimir Sementsov-Ogievskiy wrote:
>> 15.11.2019 18:03, Vladimir Sementsov-Ogievskiy wrote:
>>> 14.11.2019 5:46, Eric Blake wrote:
We document that for qcow2 persistent bitmaps, the name cannot exceed
1023 bytes. It is
14.11.2019 5:46, Eric Blake wrote:
> Qemu as server currently won't accept export names larger than 256
> bytes, nor create dirty bitmap names longer than 1023 bytes, so most
> uses of qemu as client or server have no reason to get anywhere near
> the NBD spec maximum of a 4k limit per string.
>
On Fri, Nov 15, 2019 at 10:50 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Add the CRP as unimplemented thus avoiding bus errors when
> guests access these registers.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c
When a vCPU is dispatched on a HW thread, its context is pushed in the
thread registers and it is activated by setting the VO bit in the CAM
line word2. The HW grabs the associated NVT, pulls the IPB bits and
merges them with the IPB of the new context. If interrupts were missed
while the vCPU was
On 15/11/2019 17.24, Kashyap Chamarthy wrote:
> This blog post summarizes the talk "Micro-Optimizing KVM VM-Exits"[1],
> given by Andrea Arcangeli at the recently concluded KVM Forum 2019.
Thanks, pushed now:
https://www.qemu.org/2019/11/15/micro-optimizing-kvm-vmexits/
Thomas
On Mon, 11 Nov 2019 09:40:47 +0800
Xiang Zheng wrote:
> From: Dongjiu Geng
>
> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
> translates the host VA delivered by host to guest PA, then fills this PA
> to guest APEI GHES memory, then notifies guest according to the
On 15/11/19 17:13, Sergio Lopez wrote:
> Add a new section explaining the particularities of the microvm
> machine type for triggering a guest-initiated shut down.
>
> Signed-off-by: Sergio Lopez
> ---
> docs/microvm.rst | 21 +
> 1 file changed, 21 insertions(+)
>
> diff
On Fri, Nov 15, 2019 at 02:09:25PM +0800, Micky Yun Chan wrote:
Thanks for the patch!
> +context = g_option_context_new(NULL);
Missing g_option_context_free() later in this function. g_auto() is the
easiest way to ensure that.
> +g_option_context_add_main_entries(context, entries,
On the P9 Processor, the thread interrupt context registers of a CPU
can be accessed "directly" when by load/store from the CPU or
"indirectly" by the IC through an indirect TIMA page. This requires to
configure first the PC_TCTXT_INDIRx registers.
Today, we rely on the get_tctx() handler to
On 11/15/19 9:47 AM, Vladimir Sementsov-Ogievskiy wrote:
15.11.2019 18:03, Vladimir Sementsov-Ogievskiy wrote:
14.11.2019 5:46, Eric Blake wrote:
We document that for qcow2 persistent bitmaps, the name cannot exceed
1023 bytes. It is inconsistent if transient bitmaps do not have to
abide by
When doing CAM line compares, fetch the block id from the interrupt
controller which can have set the PC_TCTXT_CHIPID field.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 2 +-
hw/intc/pnv_xive.c| 6 ++
hw/intc/spapr_xive.c | 6 ++
hw/intc/xive.c| 21
The XiveFabric QOM interface acts as the PowerBUS interface between
the interrupt controller and the system and should be implemented by
the QEMU machine. On HW, the XIVE sub-engine is responsible for the
communication with the other chip is the Common Queue (CQ) bridge
unit.
This interface
We will use it to resend missed interrupts when a vCPU context is
pushed on a HW thread.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 1 +
hw/intc/xive.c| 21 +++--
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/include/hw/ppc/xive.h
On Mon, 11 Nov 2019 11:37:40 +0100
Michal Privoznik wrote:
> The first patch fixes a crasher, the second fixes a memleak.
>
> Michal Privoznik (2):
> hw/vfio/pci: Fix double free of migration_blocker
> vfio-helpers: Free QEMUVFIOState in qemu_vfio_close()
>
> hw/vfio/pci.c | 2 ++
>
The TIMA operations are performed on behalf of the XIVE IVPE sub-engine
(Presenter) on the thread interrupt context registers. The current
operations supported by the model are simple and do not require access
to the controller but more complex operations will need access to the
controller NVT
On 15/11/2019 17.13, Paolo Bonzini wrote:
> On 15/11/19 16:54, Thomas Huth wrote:
>> On 15/11/2019 16.54, Peter Maydell wrote:
>>> On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
When CONFIG_IDE_ISA is disabled, compilation currently fails:
hw/i386/pc_piix.c: In function
The TIMA region gives access to the thread interrupt context registers
of a CPU. It is mapped at the same address on all chips and can be
accessed by any CPU of the system. To identify the chip from which the
access is being done, the PowerBUS uses a 'chip' field in the
load/store messages. QEMU
Now that the machines have handlers implementing the XiveFabric and
XivePresenter interfaces, remove xive_presenter_match() and make use
of the 'match_nvt' handler of the machine.
Signed-off-by: Cédric Le Goater
---
hw/intc/xive.c | 48 +---
1 file
When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field
overrides the hardwired chip ID in the Powerbus operations and for CAM
compares. This is typically used in the one block-per-chip configuration
to associate a unique block id number to each IC of the system.
Simplify the model
The CAM line matching sequence in the pseries machine does not change
much apart from the use of the new QOM interfaces. There is an extra
indirection because of the sPAPR IRQ backend of the machine. Only the
XIVE backend implements the new 'match_nvt' handler.
Signed-off-by: Cédric Le Goater
When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification
Virtual Target (NVT) to notify, it broadcasts a message on the
PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT
dispatched on one of its HW threads, and then forwards the
notification if any response was received.
It is now unused.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 2 --
hw/intc/pnv_xive.c| 13 -
hw/intc/spapr_xive.c | 8
hw/intc/xive.c| 7 ---
4 files changed, 30 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
and use this helper to exclude CPUs which are not enabled in the XIVE
controller.
Signed-off-by: Cédric Le Goater
---
hw/intc/pnv_xive.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 71ca4961b6b1..4c8c6e51c20f 100644
---
When dumping the END and NVT tables, the error logging is too noisy.
Signed-off-by: Cédric Le Goater
---
hw/intc/pnv_xive.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 02faf4135e48..a394331ddd6a 100644
---
CPU_FOREACH() loops on all the CPUs of the machine which is incorrect.
Each XIVE Presenter should scan only the HW threads of the chip it
belongs to.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 2 ++
hw/intc/pnv_xive.c | 63 ++--
The CAM line matching on the PowerNV machine now scans all chips of
the system and all CPUs of a chip to find a dispatched NVT in the
thread contexts.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 35 +++
1 file changed, 35 insertions(+)
diff --git
Each vCPU in the system is identified with an NVT identifier which is
pushed in the OS CAM line (QW1W2) of the HW thread interrupt context
register when the vCPU is dispatched on a HW thread. This identifier
is used by the presenter subengine to find a matching target to notify
of an event. It is
This is useful to dump the saved contexts of the vCPUs : configuration
of the base END index of the vCPU and the Interrupt Pending Buffer
register, which is updated when an interrupt can not be presented.
When dumping the NVT table, we skip empty indirect pages which are not
necessarily
A context should be 'valid' when pulled from the thread interrupt
context registers.
Signed-off-by: Cédric Le Goater
---
hw/intc/xive.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 42e9a11ef731..511e1a936347 100644
--- a/hw/intc/xive.c
+++
Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt'
handler of the XivePresenter QOM interface. This is simply moving code
and taking into account the new API.
To be noted that the xive_router_get_tctx() helper is not used anymore
when doing CAM matching and will be removed
This blog post summarizes the talk "Micro-Optimizing KVM VM-Exits"[1],
given by Andrea Arcangeli at the recently concluded KVM Forum 2019.
[1]
https://kvmforum2019.sched.com/event/Tmwr/micro-optimizing-kvm-vm-exits-andrea-arcangeli-red-hat-inc
Signed-off-by: Kashyap Chamarthy
---
v3:
-
The OS CAM line has a special encoding exploited by the HW. Provide
helper routines to hide the details to the TIMA command handlers. This
also clarifies the endianness of different variables : 'qw1w2' is
big-endian and 'cam' is native.
Signed-off-by: Cédric Le Goater
---
hw/intc/xive.c | 41
When an interrupt can not be presented to a vCPU, because it is not
running on any of the HW treads, the XIVE presenter updates the
Interrupt Pending Buffer register of the associated XIVE NVT
structure. This is only done if backlog is activated in the END but
this is generally the case.
The
Hello,
The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
acts as an hypervisor (L0). Supporting emulation of KVM to run guests
(L1) requires a few more extensions, among which guest support for the
XIVE interrupt controller on POWER9 processor.
The following changes extend the
On 15/11/2019 17.15, Peter Maydell wrote:
> On Fri, 15 Nov 2019 at 16:08, Thomas Huth wrote:
>>
>> On 15/11/2019 16.54, Peter Maydell wrote:
>>> On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -78,7 +78,6 @@ static void
pnv_xive_vst_size() tries to compute the size of a VSD table from the
information given by FW. The number of entries of the table are
deduced from the result and the MMIO regions of the ESBs and the END
ESBs are then resized accordingly with the computed value. This
reduces the number of elements
On Fri, 15 Nov 2019 at 16:08, Thomas Huth wrote:
>
> On 15/11/2019 16.54, Peter Maydell wrote:
> > On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
> >> --- a/hw/i386/pc_piix.c
> >> +++ b/hw/i386/pc_piix.c
> >> @@ -78,7 +78,6 @@ static void pc_init1(MachineState *machine,
> >>
Fix the alignment of the items in the "Limitations" section.
Signed-off-by: Sergio Lopez
---
docs/microvm.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/microvm.rst b/docs/microvm.rst
index aae811a922..4cf84746b9 100644
--- a/docs/microvm.rst
+++
hw/vfio/display.c needs the EDID subsystem, select it.
Cc: Alex Williamson
Signed-off-by: Paolo Bonzini
---
hw/vfio/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/vfio/Kconfig b/hw/vfio/Kconfig
index 34da2a3cfd..f0eaa75ce7 100644
--- a/hw/vfio/Kconfig
+++ b/hw/vfio/Kconfig
@@
1 - 100 of 246 matches
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