On Mon, Jan 27, 2020 at 02:46:58AM +0100, Zoltán Kővágó wrote:
> On 2020-01-18 07:30, Philippe Mathieu-Daudé wrote:
> > On 1/17/20 7:26 PM, KJ Liew wrote:
> > > QEMU Windows has broken dsound backend since the rewrite of audio API in
> > > version 4.2.0. Both playback and capture buffers failed to
On 31/01/20 07:50, Markus Armbruster wrote:
>>> Consider chardev-add. Example:
>>>
>>> {"execute": "chardev-add",
>>> "arguments": {"id": "bar",
>>>"backend": {"type": "file",
>>>"data": {"out": "/tmp/bar.log"
>>>
>>> The arguments
On 31/01/20 07:11, Markus Armbruster wrote:
> May I present you Armbru's Comment Trust Levels:
>
> ACTL2: The comment may be overly terse or incomplete, but the
> probability for it to be outright wrong is low.
>
> ACTL1: Treat as helpful guidance (with gratitude), but trust only the
> code.
>
>
> Hi all,
>
> Thanks to the generous help from Mark, I can now report that it is good to
> hear coreaudio has been restored into a working state with this patch! I
> tested qemu-system-ppc running MacOS and OSX.
>
> Best,
> Howard
Thank you for testing the two patches. I will wait a few days
On 30/01/2020 23.31, Philippe Mathieu-Daudé wrote:
> On 1/21/20 10:52 AM, Thomas Huth wrote:
>> We are going to enable some of the python-based tests in the "auto"
>> group,
>> and these tests require virtio-blk to work properly. Running iotests
>> without virtio-blk likely does not make too much
Thank a lot for the detailed answer. Surely it's worth discussing qemu here
leaving libvirt for RH bugzilla.
> But since modern qemu has declared -snapshot to be unsupported with
-blockdev, and modern libvirt has switched to -blockdev, I claim that this
is not a qemu bug, but a libvirt feature
On 1/29/20 8:04 PM, Marc Zyngier wrote:
On 2020-01-29 02:44, Alexey Kardashevskiy wrote:
On 28/01/2020 17:48, Gavin Shan wrote:
but a NMI is injected
through LAPIC on x86. So I'm not sure what architect (system reset on
ppc or injecting NMI on x86) aarch64 should follow.
I'd say whatever
On 1/30/20 9:58 PM, Marc Zyngier wrote:
On 2020-01-29 21:54, Gavin Shan wrote:
On 1/29/20 6:57 PM, Julien Thierry wrote:
On 1/29/20 3:46 AM, Gavin Shan wrote:
On 1/28/20 7:29 PM, Julien Thierry wrote:
.../...
Julien, thanks for the explanation. The question we're not sure if NMI should
Kevin Wolf writes:
> Am 28.01.2020 um 13:36 hat Markus Armbruster geschrieben:
>> Kevin Wolf writes:
>>
>> > Am 27.01.2020 um 21:11 hat John Snow geschrieben:
>> [...]
>> >> (The argument here is: It's a little harder and a little longer to type,
>> >> but the benefits from the schema
Kashyap Chamarthy writes:
> On Wed, Jan 15, 2020 at 03:02:48PM +0100, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>
> [Changed the subject-line to indicate deviation from the original
> topic.]
>
> [...]
>
>> > Libvirt is of course happy to switch to something else instead of
>> >
From: Aravinda Prasad
This patch sets the default value of SPAPR_CAP_FWNMI_MCE
to SPAPR_CAP_ON for machine type 5.0.
Signed-off-by: Aravinda Prasad
Signed-off-by: Ganesh Goudar
Message-Id: <20200130184423.20519-8-ganes...@linux.ibm.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 3 ++-
From: Benjamin Herrenschmidt
These changes introduces models for the PCIe Host Bridge (PHB4) of the
POWER9 processor. It includes the PowerBus logic interface (PBCQ),
IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI
and LSI interrupt sources as found on a POWER9 system using
From: Richard Henderson
Use a minimum number of mmu lookups for the contiguous bytes
that are accessed. If the lookup succeeds, we can finish the
operation with host addresses only.
Reported-by: Howard Spoelstra
Signed-off-by: Richard Henderson
Message-Id:
From: Richard Henderson
The value of addr has already been masked, just above.
Signed-off-by: Richard Henderson
Message-Id: <20200129235040.24022-4-richard.hender...@linaro.org>
Tested-by: Howard Spoelstra
Signed-off-by: David Gibson
---
target/ppc/mem_helper.c | 2 +-
1 file changed, 1
From: BALATON Zoltan
Fix PPC_INPUT macro to work with more complex expressions by
protecting its argument with parentheses.
Signed-off-by: BALATON Zoltan
Message-Id: <20200130021619.65fab747...@zero.eik.bme.hu>
Signed-off-by: David Gibson
---
target/ppc/cpu.h | 2 +-
1 file changed, 1
From: Aravinda Prasad
This patch adds support in QEMU to handle "ibm,nmi-register"
and "ibm,nmi-interlock" RTAS calls.
The machine check notification address is saved when the
OS issues "ibm,nmi-register" RTAS call.
This patch also handles the case when multiple processors
experience machine
From: Aravinda Prasad
Memory error such as bit flips that cannot be corrected
by hardware are passed on to the kernel for handling.
If the memory address in error belongs to guest then
the guest kernel is responsible for taking suitable action.
Patch [1] enhances KVM to exit guest with exit
From: Cédric Le Goater
This is a model of the PCIe Host Bridge (PHB3) found on a POWER8
processor. It includes the PowerBus logic interface (PBCQ), IOMMU
support, a single PCIe Gen.3 Root Complex, and support for MSI and LSI
interrupt sources as found on a POWER8 system using the XICS interrupt
From: Stefan Berger
For devices that cannot be statically initialized, implement a
get_dt_compatible() callback that allows us to ask the device for
the 'compatible' value.
Signed-off-by: Stefan Berger
Reviewed-by: Marc-André Lureau
Reviewed-by: David Gibson
Message-Id:
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Stefan Berger
Message-Id: <20200121152935.649898-7-stef...@linux.ibm.com>
Signed-off-by: David Gibson
---
docs/specs/index.rst | 1 +
docs/specs/tpm.rst | 503 +++
From: Richard Henderson
Use a minimum number of mmu lookups for the contiguous bytes
that are accessed. If the lookup succeeds, we can finish the
operation with host addresses only.
Reported-by: Howard Spoelstra
Signed-off-by: Richard Henderson
Message-Id:
From: Stefan Berger
Signed-off-by: Stefan Berger
Reviewed-by: Marc-André Lureau
Reviewed-by: David Gibson
Message-Id: <20200121152935.649898-6-stef...@linux.ibm.com>
[dwg: Use default in Kconfig rather than select to avoid breaking
Windows host build]
Signed-off-by: David Gibson
---
From: Aravinda Prasad
Introduce a wrapper function to wait on condition for
the main loop mutex. This function atomically releases
the main loop mutex and causes the calling thread to
block on the condition. This wrapper is required because
qemu_global_mutex is a static variable.
Signed-off-by:
From: Richard Henderson
Using probe_write instead of tlb_vaddr_to_host means that we
process watchpoints and notdirty pages more efficiently.
Signed-off-by: Richard Henderson
Message-Id: <20200129235040.24022-5-richard.hender...@linaro.org>
Tested-by: Howard Spoelstra
Signed-off-by: David
From: Aravinda Prasad
This patch includes migration support for machine check
handling. Especially this patch blocks VM migration
requests until the machine check error handling is
complete as these errors are specific to the source
hardware and is irrelevant on the target hardware.
From: Stefan Berger
Implement support for TPM on ppc64 by implementing the vTPM CRQ interface
as a frontend. It can use the tpm_emulator driver backend with the external
swtpm.
The Linux vTPM driver for ppc64 works with this emulation.
This TPM emulator also handles the TPM 2 case.
From: Aravinda Prasad
Upon a machine check exception (MCE) in a guest address space,
KVM causes a guest exit to enable QEMU to build and pass the
error to the guest in the PAPR defined rtas error log format.
This patch builds the rtas error log, copies it to the rtas_addr
and then invokes the
From: Cédric Le Goater
When the "hb-mode" option is activated on the powernv machine, the
firmware is mapped at 0x800 and the HRMOR of the HW threads are
set to the same address.
The PNOR mapping on the FW address space of the LPC bus is left enabled
to let the firmware load any other
From: Stefan Berger
Signed-off-by: Stefan Berger
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: David Gibson
Message-Id: <20200121152935.649898-2-stef...@linux.ibm.com>
Signed-off-by: David Gibson
---
hw/tpm/tpm_tis.c| 32
hw/tpm/tpm_util.c | 25
From: Thomas Huth
It's been deprecated since QEMU v3.1. The 40p machine should be
used nowadays instead.
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Hervé Poussineau
Signed-off-by: Thomas Huth
Message-Id: <20200114114617.28854-1-th...@redhat.com>
Signed-off-by: David Gibson
---
From: Cédric Le Goater
The PowerNV machine emulates an OpenPOWER system and the PowerNV chip
devices are models of the internal logic of the POWER processor. They
can not be instantiated by the user on the QEMU command line.
The PHB3/PHB4 devices could be an exception in the future after some
From: Cédric Le Goater
The Processor Control facility for POWER8 processors and later
provides a mechanism for the hypervisor to send messages to other
threads in the system (msgsnd instruction) and cause hypervisor-level
exceptions. Privileged non-hypervisor programs can also send messages
From: Aravinda Prasad
Introduce fwnmi an spapr capability and add a helper function
which tries to enable it, which would be used by following patch
of the series. This patch by itself does not change the existing
behavior.
Signed-off-by: Aravinda Prasad
[eliminate cap_ppc_fwnmi, add fwnmi cap
From: Cédric Le Goater
Commit 158e17a65e1a ("ppc/pnv: Link "chip" property to PnvCore::chip
pointer") introduced some cleanups of the PnvCore realize handler.
Let's continue by reworking a bit the interface of the PnvCore
handlers for the CPU threads. These changes make the "core-pir"
property
From: Stefan Berger
Extend the tpm_spapr frontend with VM suspend and resume support.
Signed-off-by: Stefan Berger
Message-Id: <20200121152935.649898-5-stef...@linux.ibm.com>
Reviewed-by: Marc-André Lureau
Signed-off-by: David Gibson
---
hw/tpm/tpm_spapr.c | 52
From: Greg Kurz
Most of the option vector helpers have assertions to check their
arguments aren't null. The guest can provide an arbitrary address
for the CAS structure that would result in such null arguments.
Fail CAS with H_PARAMETER and print a warning instead of aborting
QEMU.
For POWER9 DD2.2 cpus, the best current Spectre v2 indirect branch
mitigation is "count cache disabled", which is configured with:
-machine cap-ibs=fixed-ccd
However, this option isn't available on DD2.3 CPUs with KVM, because they
don't have the count cache disabled.
For POWER9 DD2.3 cpus,
From: Cédric Le Goater
The privileged message send and clear instructions (msgsndp & msgclrp)
are privileged, but will generate a hypervisor facility unavailable
exception if not enabled in the HFSCR and executed in privileged
non-hypervisor state.
Add checks when accessing the DPDES register
From: Cédric Le Goater
When in HV mode, if EA[0] is 0, the Hypervisor Offset Real Mode
Register controls the access.
Signed-off-by: Cédric Le Goater
Message-Id: <20200127144154.10170-2-...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/mmu-radix64.c | 6 ++
1 file changed, 6
From: Greg Kurz
According to the description of "ibm,client-architecture-support" that
can found in LoPAPR "B.6.2.3 Root Node Methods":
If multiple partition processors or threads are active at the time of
the ibm,client-architecture-support method call, or an error is detected
in the format of
The following changes since commit 928173659d6e5dc368284f73f90ea1d129e1f57d:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200130'
into staging (2020-01-30 16:19:04 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-5.0
From: Cédric Le Goater
Print out the offset at which the error occured.
Signed-off-by: Cédric Le Goater
Message-Id: <20200108090348.21224-3-...@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/pnv_pnor.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Fabiano Rosas
The kvm_handle_debug function can return 0 to go back into the guest
or return 1 to notify the gdbstub thread and pass control to GDB.
Signed-off-by: Fabiano Rosas
Message-Id: <20200110151344.278471-2-faro...@linux.ibm.com>
Tested-by: Leonardo Bras
Signed-off-by: David
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <1579100861-73692-71-git-send-email-imamm...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/virtex_ml507.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Message-Id: <20200108090348.21224-2-...@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/pnv_pnor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_pnor.c
On Wed, Jan 29, 2020 at 04:16:33AM -0800, Liu, Yi L wrote:
> From: Liu Yi L
>
> Currently, many platform vendors provide the capability of dual stage
> DMA address translation in hardware. For example, nested translation
> on Intel VT-d scalable mode, nested stage translation on ARM SMMUv3,
>
On Wed, Jan 29, 2020 at 04:16:34AM -0800, Liu, Yi L wrote:
> From: Peter Xu
>
> Currently, many platform vendors provide the capability of dual stage
> DMA address translation in hardware. For example, nested translation
> on Intel VT-d scalable mode, nested stage translation on ARM SMMUv3,
>
On Fri, Jan 31, 2020 at 4:45 AM Aleksandar Markovic
wrote:
>
> On Fri, Jan 31, 2020 at 4:09 AM Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Aleksandar,
> >
> > Cc'ing Thomas & Daniel who are not lawyers but tried to explain me few
> > times how licensing works.
> >
> > On Fri, Jan 31, 2020 at
On Fri, Jan 31, 2020 at 4:09 AM Philippe Mathieu-Daudé wrote:
>
> Hi Aleksandar,
>
> Cc'ing Thomas & Daniel who are not lawyers but tried to explain me few
> times how licensing works.
>
> On Fri, Jan 31, 2020 at 2:56 AM Aleksandar Markovic
> wrote:
> > On Fri, Jan 31, 2020 at 1:03 AM Aleksandar
Hi Aleksandar,
Cc'ing Thomas & Daniel who are not lawyers but tried to explain me few
times how licensing works.
On Fri, Jan 31, 2020 at 2:56 AM Aleksandar Markovic
wrote:
> On Fri, Jan 31, 2020 at 1:03 AM Aleksandar Markovic
> wrote:
> >
> > From: Philippe Mathieu-Daudé
> >
> > Add some AVR
On 1/21/20 12:51 AM, Philippe Mathieu-Daudé wrote:
Avocado tags are handy to automatically select tests matching
the tags. Since this test also runs U-Boot, tag it.
We can run all the tests using U-Boot as once with:
$ avocado --show=app run -t u-boot tests/acceptance/
JOB LOG:
Public bug reported:
I want to build qemu statically so as to use qemu on Android platform(Though
Limbo emulator is available on github,it's even slower than qemu in UserLAnd(an
Android APP that provides proot container for Linux dists)).
When I finished building qemu normally on my
On Fri, Jan 31, 2020 at 1:03 AM Aleksandar Markovic
wrote:
>
> From: Philippe Mathieu-Daudé
>
> Add some AVR microcontrollers from the ATmega family:
>
> - middle range: ATmega168 and ATmega328
> - high range: ATmega1280 and ATmega2560
>
> For product comparison:
>
On Wed, Jan 29, 2020 at 03:50:36PM -0800, Richard Henderson wrote:
> The first two address the performance regression noticed
> by Howard Spoelstra. The last two are just something I
> noticed at the same time.
Applied to ppc-for-5.0, thanks.
>
>
> r~
>
>
> Richard Henderson (4):
>
Hi Richard,
On 1/27/20 2:38 PM, Michael Rolnik wrote:
Hi Joaquin.
I looks like that the CPU families are not well defined. There are some
small variations within the families themselves i.e. some MCUs do not
support all the features of their families.
To get the features I looked at this
On 1/31/20 1:12 AM, Aleksandar Markovic wrote:
Michael, Philippe,
Can you guys do a quick checkup of this rc4? rc4, rc3,and rc2 should
be functionally 100% equivalent.
Tested OK.
git-backport-diff with rc2:
Key:
[] : patches are identical
[] : number of functional differences
On Fri, Jan 31, 2020 at 2:09 AM Philippe Mathieu-Daudé
wrote:
>
> Aleksandar, I addressed Alex Bennée comment as fixup, so you
> can squash directly. See:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg673846.html
>
> - convert DB_PRINT() to trace-events
> - fix style/indentation
>
>
- convert DB_PRINT() to trace-events
- fix style/indentation
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/avr_power.c | 17 +
hw/misc/trace-events | 4
2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/misc/avr_power.c b/hw/misc/avr_power.c
index
Aleksandar, I addressed Alex Bennée comment as fixup, so you
can squash directly. See:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg673846.html
- convert DB_PRINT() to trace-events
- fix style/indentation
Based-on: <1580428993-4767-1-git-send-email-aleksandar.marko...@rt-rk.com>
Convert DB_PRINT() to trace events.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/avr_timer16.c | 25 +++--
hw/timer/trace-events | 12
2 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c
index
On Fri, Jan 31, 2020 at 1:28 AM Philippe Mathieu-Daudé
wrote:
>
> On 1/31/20 1:26 AM, Aleksandar Markovic wrote:
> > On Fri, Jan 31, 2020 at 1:20 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 1/31/20 1:03 AM, Aleksandar Markovic wrote:
> >>> From: Philippe Mathieu-Daudé
> >>>
> >>> Add
On 1/31/20 1:26 AM, Aleksandar Markovic wrote:
On Fri, Jan 31, 2020 at 1:20 AM Philippe Mathieu-Daudé
wrote:
On 1/31/20 1:03 AM, Aleksandar Markovic wrote:
From: Philippe Mathieu-Daudé
Add avr_load_firmware() function to load firmware in ELF or
raw binary format.
[AM: Corrected the type
On Fri, Jan 31, 2020 at 1:23 AM Philippe Mathieu-Daudé
wrote:
>
> On 1/31/20 1:03 AM, Aleksandar Markovic wrote:
> > From: Michael Rolnik
> >
> > Add AVR related definitions into QEMU.
> >
> > [AM: Remove word 'Atmel' from filenames and all elements of code]
> > Suggested-by: Aleksandar Markovic
On Fri, Jan 31, 2020 at 1:20 AM Philippe Mathieu-Daudé
wrote:
>
> On 1/31/20 1:03 AM, Aleksandar Markovic wrote:
> > From: Philippe Mathieu-Daudé
> >
> > Add avr_load_firmware() function to load firmware in ELF or
> > raw binary format.
> >
> > [AM: Corrected the type of the variable containing
On 1/31/20 1:03 AM, Aleksandar Markovic wrote:
From: Michael Rolnik
Add AVR related definitions into QEMU.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksandar Markovic
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by:
On 1/29/20 10:23 PM, Philippe Mathieu-Daudé wrote:
From: Denis Plotnikov
Since, virtio_seg_max_adjust checks not only seg_max, but also
virtqueue_size parameter, let's make the test more general and
add new parameters to be checked there in the future.
Signed-off-by: Denis Plotnikov
From: Michael Rolnik
These were designed to facilitate testing but should provide enough
function to be useful in other contexts. Only a subset of the functions
of each peripheral is implemented, mainly due to the lack of a standard
way to handle electrical connections (like GPIO pins).
[AM:
On 1/31/20 1:03 AM, Aleksandar Markovic wrote:
From: Philippe Mathieu-Daudé
Add avr_load_firmware() function to load firmware in ELF or
raw binary format.
[AM: Corrected the type of the variable containing e_flags]
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé
Add some AVR microcontrollers from the ATmega family:
- middle range: ATmega168 and ATmega328
- high range: ATmega1280 and ATmega2560
For product comparison:
https://www.microchip.com/wwwproducts/ProductCompare/ATmega168P/ATmega328P
On 1/29/20 10:23 PM, Philippe Mathieu-Daudé wrote:
Add logging for easier debugging of failures:
$ avocado --show=machine run tests/acceptance/virtio_check_params.py
(1/1)
tests/acceptance/virtio_check_params.py:VirtioMaxSegSettingsCheck.test_machine_types:
machine: {'name':
From: Michael Rolnik
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
As the path name demonstrates, the FreeRTOS tests target a
From: Philippe Mathieu-Daudé
Arduino boards are build with AVR chipsets.
Add some of the popular boards:
- Arduino Duemilanove
- Arduino Uno
- Arduino Mega
For more information:
https://www.arduino.cc/en/Main/Products
https://store.arduino.cc/arduino-genuino/most-popular
[AM: Remove word
From: Michael Rolnik
These were designed to facilitate testing but should provide enough
function to be useful in other contexts. Only a subset of the functions
of each peripheral is implemented, mainly due to the lack of a standard
way to handle electrical connections (like GPIO pins).
[AM:
Hi, David and Juan
Does it look good to you?
On Mon, Oct 07, 2019 at 05:10:08PM +0800, Wei Yang wrote:
>ram_discard_range() unmap page for specific range. To be specific, this
>clears related page table entries so that userfault would be triggered.
>But this step is not necessary at the very
From: Michael Rolnik
Explains basic ways of using AVR target in QEMU.
Signed-off-by: Michael Rolnik
Message-Id: <20200118191416.19934-16-mrol...@gmail.com>
Signed-off-by: Richard Henderson
[PMD: Fixed typos]
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Aleksandar Markovic
---
From: Philippe Mathieu-Daudé
We have one test so far, and it is very fast:
$ avocado --show=app run -t arch:avr tests/acceptance/
(1/1) tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos: PASS (2.13
s)
RESULTS: PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
From: Michael Rolnik
Print out 'T' through serial port
The Arduino Duemilanove is based on a AVR5 CPU, while the
Arduino MEGA2560 on a AVR6 CPU.
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Acked-by: Thomas Huth
Signed-off-by: Philippe
From: Michael Rolnik
Add AVR related definitions into QEMU.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksandar Markovic
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
From: Michael Rolnik
Include AVR maintaners in MAINTAINERS file
Signed-off-by: Michael Rolnik
Signed-off-by: Philippe Mathieu-Daudé
[rth: Squash ordering fixes from f4bug]
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
MAINTAINERS | 24
1
Michael, Philippe,
Can you guys do a quick checkup of this rc4? rc4, rc3,and rc2 should
be functionally 100% equivalent.
Thank you,
Aleksandar
On Fri, Jan 31, 2020 at 1:06 AM Aleksandar Markovic
wrote:
>
> From: Aleksandar Markovic
>
> This is the AVR port from Michael, release (merge)
From: Philippe Mathieu-Daudé
Add avr_load_firmware() function to load firmware in ELF or
raw binary format.
[AM: Corrected the type of the variable containing e_flags]
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Aleksandar Markovic
---
From: Michael Rolnik
Provide function disassembles executed instruction when `-d in_asm` is
provided
Example:
`./avr-softmmu/qemu-system-avr -bios free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf
-d in_asm` will produce something like the following
```
...
IN:
0x014a: CALL
From: Michael Rolnik
Add a single code line that will automatically provide 'machine none'
test.
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Reviewed-by: Thomas Huth
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
From: Michael Rolnik
Make AVR support buildable.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksandar Markovic
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
From: Michael Rolnik
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
target/avr/insn.decode | 8 ++
target/avr/translate.c | 68
From: Michael Rolnik
This is a simple device of just one register, and whenever this
register is written to it calls qemu_set_irq function for each
of 8 bits/IRQs. It is used to implement AVR Power Reduction.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by:
From: Michael Rolnik
Add migration functions for AVR cores.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
From: Michael Rolnik
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Signed-off-by:
From: Michael Rolnik
This patch introduces AVR CPU class object and its basic elements
and functions.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
From: Michael Rolnik
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
target/avr/translate.c | 234
From: Michael Rolnik
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
From: Michael Rolnik
Start implementation of instructions by adding register definitions.
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
target/avr/translate.c |
From: Michael Rolnik
This includes GDB hooks for reading from wnd wrtiting to AVR
registers, and xml register definition file as well.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah
From: Aleksandar Markovic
This is the AVR port from Michael, release (merge) candidate 4.
The series can be found also in this repository:
https://github.com/AMarkovic/qemu-avr-merger-rc4
History:
Since v3:
- Removed a patch on load_elf() modification, since it has been merged
- Removed
From: Michael Rolnik
This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT
Signed-off-by: Michael Rolnik
Tested-by: Philippe
From: Michael Rolnik
AVR core types are:
- avr1
- avr2
- avr25
- avr3
- avr31
- avr35
- avr4
- avr5
- avr51
- avr6
- avrtiny
- xmega2
- xmega3
- xmega4
- xmega5
- xmega6
- xmega7
Each core type covers multiple AVR MCUs, mentioned in the comments
before
From: Michael Rolnik
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
---
target/avr/insn.decode | 14 +++
From: Michael Rolnik
This patch introduces enumeration "AVRFeature" that will be
used for defining various AVR core types.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
From: Michael Rolnik
This includes definitions of various basic parameters needed
for integration of a new platform into QEMU.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
From: Michael Rolnik
Add helpers for instructions that need to interact with QEMU. Also,
add stubs for unimplemented instructions. Instructions SPM and WDR
are left unimplemented because they require emulation of complex
peripherals. The implementation of instruction SLEEP is very limited
due to
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