On 2/11/20 1:39 AM, Taylor Simpson wrote:
This series adds support for the Hexagon processor with Linux user support
Hexagon is Qualcomm's very long instruction word (VLIW) digital signal
processor(DSP). We also support Hexagon Vector eXtensions (HVX). HVX
is a wide vector coprocessor
On 2/11/20 2:31 AM, no-re...@patchew.org wrote:
Patchew URL:
https://patchew.org/QEMU/1581381644-13678-1-git-send-email-tsimp...@quicinc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
[...]> ERROR: please use python3 interpreter
#21:
On 02/11/20 07:50, Philippe Mathieu-Daudé wrote:
> As we plan to let maintainers managing their own GitLab CI jobs,
> add a single directory to contain all the new files (to keep the
> root directory cleaner).
>
> EDK2 job is the first user, move it there.
>
> Suggested-by: Wainer dos Santos
On 2/11/20 1:40 AM, Taylor Simpson wrote:
Functions to support scatter/gather
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/system_ext_mmvec.c | 265
target/hexagon/mmvec/system_ext_mmvec.h | 38 +
2 files changed, 303 insertions(+)
create
From: Prasad J Pandit
Tulip network driver while copying tx/rx buffers does not check
frame size against r/w data length. This may lead to OOB buffer
access. Add check to avoid it.
Reported-by: Li Qiang
Reported-by: Ziming Zhang
Signed-off-by: Prasad J Pandit
---
hw/net/tulip.c | 55
On 2/11/20 1:40 AM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/opcodes.c | 223 +++
target/hexagon/opcodes.h | 67 ++
2 files changed, 290 insertions(+)
create mode 100644 target/hexagon/opcodes.c
On 2020/2/11 下午2:02, Liu, Jing2 wrote:
On 2/11/2020 12:02 PM, Jason Wang wrote:
On 2020/2/11 上午11:35, Liu, Jing2 wrote:
On 2/11/2020 11:17 AM, Jason Wang wrote:
On 2020/2/10 下午5:05, Zha Bin wrote:
From: Liu Jiang
Userspace VMMs (e.g. Qemu microvm, Firecracker) take advantage of
On 2/11/20 1:40 AM, Taylor Simpson wrote:
Python script that emits the decode tree in dectree_generated.h.
Signed-off-by: Taylor Simpson
---
target/hexagon/dectree.py | 354 ++
1 file changed, 354 insertions(+)
create mode 100755
On 2/11/20 1:40 AM, Taylor Simpson wrote:
Run the C preprocessor across the instruction definition and encoding
files to expand macros and prepare the iset.py file. The resulting
fill contains python data structures used to build the decode tree.
Signed-off-by: Taylor Simpson
---
On 2/11/20 1:39 AM, Taylor Simpson wrote:
For each instruction we create
DEF_HELPER function prototype
TCG code to generate call to helper
Helper definition
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 773 ++
1
On 2/11/20 1:39 AM, Taylor Simpson wrote:
Run the C preprocessor across the instruction definition files and macro
definitoin file to expand macros and prepare the semantics_generated.pyinc
file. The
resulting file contains one entry with the semantics for each instruction and
one line with
On 2/11/20 1:39 AM, Taylor Simpson wrote:
Utility functions called by various instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 664 +
target/hexagon/arch.h | 62
target/hexagon/conv_emu.c | 370 +++
On 2/11/20 1:39 AM, Taylor Simpson wrote:
Certain operand types represent a non-contiguous set of values.
For example, the compound compare-and-jump instruction can only access
registers R0-R7 and R16-23.
This table represents the mapping from the encoding to the actual values.
Signed-off-by:
On 2/11/20 1:39 AM, Taylor Simpson wrote:
Define types used in files imported from the Hexagon architecture library
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_arch_types.h | 42 +
1 file changed, 42 insertions(+)
create mode 100644
On 2/11/20 1:39 AM, Taylor Simpson wrote:
The Hexagon disassembler calls disassemble_hexagon to decode a packet
and format it for printing
Signed-off-by: Taylor Simpson
---
disas/Makefile.objs | 1 +
disas/hexagon.c | 56 +
On 2/11/20 1:39 AM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_regs.h | 97 +++
1 file changed, 97 insertions(+)
create mode 100644 target/hexagon/hex_regs.h
diff --git a/target/hexagon/hex_regs.h
On 2/11/20 1:39 AM, Taylor Simpson wrote:
Define EM_HEXAGON 164
Signed-off-by: Taylor Simpson
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 8fbfe60..d51e7d4 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -170,6 +170,8 @@
On 2/11/20 1:40 AM, Taylor Simpson wrote:
Add file to default-configs
Change configure
Add target/hexagon/Makefile.objs
Change scripts/qemu-binfmt-conf.sh
Modify tests/tcg/configure.sh
Add reference files to tests/tcg/hexagon
At this point in the patch series, you can build a hexagon-linux-user
Hi Taylor,
On 2/11/20 1:40 AM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 830 +++
3 files
As we plan to let maintainers managing their own GitLab CI jobs,
add a single directory to contain all the new files (to keep the
root directory cleaner).
EDK2 job is the first user, move it there.
Suggested-by: Wainer dos Santos Moschetta
Signed-off-by: Philippe Mathieu-Daudé
---
.gitignore
Hi everyone,
We have some issues about setting COLO feature. Hope somebody could
give us some advice.
Issue 1:
We dynamic to set COLO feature for PVM(2 core, 16G memory), but the
Primary VM will pause a long time(based on memory size) for waiting SVM
start. Does it have any idea to
On 2/11/2020 12:02 PM, Jason Wang wrote:
On 2020/2/11 上午11:35, Liu, Jing2 wrote:
On 2/11/2020 11:17 AM, Jason Wang wrote:
On 2020/2/10 下午5:05, Zha Bin wrote:
From: Liu Jiang
Userspace VMMs (e.g. Qemu microvm, Firecracker) take advantage of
using
virtio over mmio devices as a
On Tue, Feb 11, 2020 at 11:45:43AM +0800, Alex Williamson wrote:
> On Mon, 10 Feb 2020 21:52:51 -0500
> Yan Zhao wrote:
>
> > On Tue, Feb 11, 2020 at 03:44:54AM +0800, Alex Williamson wrote:
> > > On Mon, 10 Feb 2020 04:49:54 -0500
> > > Yan Zhao wrote:
> > >
> > > > On Sat, Feb 08, 2020 at
On 2020/2/11 上午11:35, Liu, Jing2 wrote:
On 2/11/2020 11:17 AM, Jason Wang wrote:
On 2020/2/10 下午5:05, Zha Bin wrote:
From: Liu Jiang
Userspace VMMs (e.g. Qemu microvm, Firecracker) take advantage of using
virtio over mmio devices as a lightweight machine model for modern
cloud. The
On Mon, 10 Feb 2020 21:52:51 -0500
Yan Zhao wrote:
> On Tue, Feb 11, 2020 at 03:44:54AM +0800, Alex Williamson wrote:
> > On Mon, 10 Feb 2020 04:49:54 -0500
> > Yan Zhao wrote:
> >
> > > On Sat, Feb 08, 2020 at 03:42:31AM +0800, Kirti Wankhede wrote:
> > > > VFIO_IOMMU_DIRTY_PAGES ioctl
On 2/11/2020 11:17 AM, Jason Wang wrote:
On 2020/2/10 下午5:05, Zha Bin wrote:
From: Liu Jiang
Userspace VMMs (e.g. Qemu microvm, Firecracker) take advantage of using
virtio over mmio devices as a lightweight machine model for modern
cloud. The standard virtio over MMIO transport layer only
On 1/29/2020 6:14 PM, Michael S. Tsirkin wrote:
On Tue, Jan 21, 2020 at 09:54:33PM +0800, Jing Liu wrote:
Bit 1 msi_sharing reported in the MsiState register indicates the mapping mode
device uses.
Bit 1 is 0 - device uses MSI non-sharing mode. This indicates vector per event
and
fixed
On 2020/2/10 下午5:05, Zha Bin wrote:
From: Liu Jiang
Userspace VMMs (e.g. Qemu microvm, Firecracker) take advantage of using
virtio over mmio devices as a lightweight machine model for modern
cloud. The standard virtio over MMIO transport layer only supports one
legacy interrupt, which is much
On 2020/2/11 上午5:45, Vikram Garhwal wrote:
+}
+} else {
+/* Normal mode Tx. */
+generate_frame(, data);
+
+can_bus_client_send(>bus_client, , 1);
I had a quick glance at can_bus_client_send():
It did:
On Tue, Feb 11, 2020 at 03:44:54AM +0800, Alex Williamson wrote:
> On Mon, 10 Feb 2020 04:49:54 -0500
> Yan Zhao wrote:
>
> > On Sat, Feb 08, 2020 at 03:42:31AM +0800, Kirti Wankhede wrote:
> > > VFIO_IOMMU_DIRTY_PAGES ioctl performs three operations:
> > > - Start pinned and unpinned pages
Patchew URL:
https://patchew.org/QEMU/1581381644-13678-1-git-send-email-tsimp...@quicinc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [RFC PATCH 00/66] Hexagon patch series
Message-id:
Functions to support scatter/gather
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/system_ext_mmvec.c | 265
target/hexagon/mmvec/system_ext_mmvec.h | 38 +
2 files changed, 303 insertions(+)
create mode 100644
Various forms of declare, read, write, free for HVX operands
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h | 232 ++
1 file changed, 232 insertions(+)
create mode 100644 target/hexagon/mmvec/macros.h
diff --git
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 830 +++
3 files changed, 851 insertions(+)
create mode 100644
Add HVX support to the semantics generator
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 175 ++---
target/hexagon/gen_semantics.c | 9 +++
2 files changed, 171 insertions(+), 13 deletions(-)
diff --git a/target/hexagon/do_qemu.py
Signed-off-by: Taylor Simpson
---
target/hexagon/gdbstub.c | 62
1 file changed, 62 insertions(+)
diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
index f07cb9a..e97b0af 100644
--- a/target/hexagon/gdbstub.c
+++
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h | 436 ++
1 file changed, 436 insertions(+)
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index 80adb83..93d86e7 100644
--- a/target/hexagon/mmvec/macros.h
+++
Override compare, transfer, conditional jump instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 119 ++
1 file changed, 119 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
Read the instruction memory
Create a packet data structure
Generate TCG code for the start of the packet
Invoke the generate function for each instruction
Generate TCG code for the end of the packet
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.c | 732
Override dczeroa, allocframe, and return instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 209 ++
1 file changed, 209 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index
Override compound compare and jump instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 105 ++
1 file changed, 105 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index
Override predicated load instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 235 ++
1 file changed, 235 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 553..673b7a5
Helpers for instructions overriden for optimization
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 314
1 file changed, 314 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index
Override predicated store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 648fc5d..9791d33
Include the generated files and set up the data structures
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 60 +
target/hexagon/genptr.h | 25 +
2 files changed, 85 insertions(+)
create mode 100644
Override store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 241 ++
1 file changed, 241 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 673b7a5..648fc5d 100644
---
Signed-off-by: Taylor Simpson
---
target/hexagon/decode.c | 23 +-
target/hexagon/mmvec/decode_ext_mmvec.c | 673
target/hexagon/mmvec/decode_ext_mmvec.h | 24 ++
target/hexagon/q6v_decode.c | 14 +
4 files changed, 732
Used to determine legal VLIW slots for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/iclass.c | 109
target/hexagon/iclass.h | 46
2 files changed, 155 insertions(+)
create mode 100644
Helpers for load-locked/store-conditional
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 52 +
1 file changed, 52 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index 2b91fdb..b780522
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 1 +
target/hexagon/op_helper.c | 75 ++
2 files changed, 76 insertions(+)
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 5dc0f71..3e4728d 100644
---
Utility functions called by various instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 664 +
target/hexagon/arch.h | 62
target/hexagon/conv_emu.c | 370 +++
target/hexagon/conv_emu.h | 50 +++
Imported from the Hexagon architecture library
imported/allext_macros.def Top level macro include for all extensions
imported/mmvec/macros.defHVX macro definitions
The macro definition files specify instruction attributes that are applied
to each instruction that reverences
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | +++
1 file changed, insertions(+)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 4399585..e89fe4c 100644
--- a/target/hexagon/macros.h
+++
Changes to packet semantics to support HVX
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.c | 174 +
target/hexagon/translate.h | 30
2 files changed, 204 insertions(+)
diff --git a/target/hexagon/translate.c
Various forms of declare, read, write, free
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 388
1 file changed, 388 insertions(+)
create mode 100644 target/hexagon/macros.h
diff --git a/target/hexagon/macros.h
Run the C preprocessor across the instruction definition and encoding
files to expand macros and prepare the iset.py file. The resulting
fill contains python data structures used to build the decode tree.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_dectree_import.c | 205
Implementation of Linux user emulation for RISC-V
Some common files modified in addition to new files in linux-user/hexagon
Signed-off-by: Taylor Simpson
---
linux-user/elfload.c| 16 ++
linux-user/hexagon/cpu_loop.c | 173 ++
linux-user/hexagon/signal.c
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 1 +
target/hexagon/genptr_helpers.h | 189
2 files changed, 190 insertions(+)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 30319b5..3da0018 100644
---
Helpers for store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 77 +
1 file changed, 77 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index b780522..27f965a 100644
---
Signed-off-by: Taylor Simpson
---
target/hexagon/Makefile.objs | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/Makefile.objs b/target/hexagon/Makefile.objs
index efcf510..3ff59e4 100644
--- a/target/hexagon/Makefile.objs
+++
Helpers for reading and writing registers
Helpers for getting and setting parts of values (e.g., set bit)
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 323
1 file changed, 323 insertions(+)
create mode 100644
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for packet semantics
store buffer (masked stores and scatter/gather)
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.c |
Imported from the Hexagon architecture library
imported/macros.def Scalar core macro definitions
The macro definition files specify instruction attributes that are applied
to each instruction that reverences the macro.
Signed-off-by: Taylor Simpson
---
Override mathematical operations with more than one definition
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index
Python script that emits the decode tree in dectree_generated.h.
Signed-off-by: Taylor Simpson
---
target/hexagon/dectree.py | 354 ++
1 file changed, 354 insertions(+)
create mode 100755 target/hexagon/dectree.py
diff --git
Override miscellaneous instructions identified during profiling
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 296 ++
1 file changed, 296 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
This series adds support for the Hexagon processor with Linux user support
Hexagon is Qualcomm's very long instruction word (VLIW) digital signal
processor(DSP). We also support Hexagon Vector eXtensions (HVX). HVX
is a wide vector coprocessor designed for high performance computer vision,
Override instructions to speed up qemu
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 97 +++
1 file changed, 97 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index e544dd5..52e4a47
Override memop instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 60 +++
1 file changed, 60 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 9791d33..f023442 100644
---
Override load instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 1 +
target/hexagon/helper_overrides.h | 404 ++
2 files changed, 405 insertions(+)
create mode 100644 target/hexagon/helper_overrides.h
diff --git
Take the words from instruction memory and build a packet_t for TCG code
generation
The following operations are performed
Convert the .new encoded offset to the register number of the producer
Reorder the instructions in the packet so .new producer is before consumer
Apply constant
The majority of helpers are generated. Define the helper functions needed
then include the generated file
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 37
target/hexagon/op_helper.c | 432 +
2 files changed, 469 insertions(+)
Signed-off-by: Taylor Simpson
---
target/hexagon/opcodes.c | 223 +++
target/hexagon/opcodes.h | 67 ++
2 files changed, 290 insertions(+)
create mode 100644 target/hexagon/opcodes.c
create mode 100644 target/hexagon/opcodes.h
diff
The insn_t and packet_t are the interface between instruction decoding and
TCG code generation
Signed-off-by: Taylor Simpson
---
target/hexagon/insn.h | 133 ++
1 file changed, 133 insertions(+)
create mode 100644 target/hexagon/insn.h
diff
Helpers referenced in macros.h
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 67 +
1 file changed, 67 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index 27f965a..85b449a 100644
---
Signed-off-by: Taylor Simpson
---
target/hexagon/attribs.h | 32
target/hexagon/attribs_def.h | 404 +++
2 files changed, 436 insertions(+)
create mode 100644 target/hexagon/attribs.h
create mode 100644 target/hexagon/attribs_def.h
diff --git
Lists the register and immediate operands for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 86 +++
1 file changed, 86 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index
Imported from the Hexagon architecture library
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/iclass.def | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 target/hexagon/imported/iclass.def
diff --git
For each instruction we create
DEF_HELPER function prototype
TCG code to generate call to helper
Helper definition
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 773 ++
1 file changed, 773 insertions(+)
create mode 100755
Data for printing (disassembling) each instruction (format string + operands)
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 151 ++
1 file changed, 151 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
Add CPU state header, CPU definitions and initialization routines
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu-param.h | 26
target/hexagon/cpu.c | 304 +
target/hexagon/cpu.h | 165
Gives a default definition of fWRAP_ for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 992dbc3..43acdd7 100755
---
Lists all the attributes associated with each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 5439964..f297931 100755
---
Declare bitfields within registers such as user status register (USR)
Signed-off-by: Taylor Simpson
---
target/hexagon/reg_fields.c | 28 +++
target/hexagon/reg_fields.h | 40 +++
target/hexagon/reg_fields_def.h | 109
3
The Hexagon disassembler calls disassemble_hexagon to decode a packet
and format it for printing
Signed-off-by: Taylor Simpson
---
disas/Makefile.objs | 1 +
disas/hexagon.c | 56 +
include/disas/dis-asm.h | 1 +
3 files changed, 58
Signed-off-by: Taylor Simpson
---
target/hexagon/printinsn.c | 93 ++
target/hexagon/printinsn.h | 26 +
2 files changed, 119 insertions(+)
create mode 100644 target/hexagon/printinsn.c
create mode 100644 target/hexagon/printinsn.h
diff
Define types used in files imported from the Hexagon architecture library
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_arch_types.h | 42 +
1 file changed, 42 insertions(+)
create mode 100644 target/hexagon/hex_arch_types.h
diff --git
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_regs.h | 97 +++
1 file changed, 97 insertions(+)
create mode 100644 target/hexagon/hex_regs.h
diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h
new file mode 100644
index
GDB register read and write routines
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.c | 3 +++
target/hexagon/gdbstub.c | 49
2 files changed, 52 insertions(+)
create mode 100644 target/hexagon/gdbstub.c
diff --git
Certain operand types represent a non-contiguous set of values.
For example, the compound compare-and-jump instruction can only access
registers R0-R7 and R16-23.
This table represents the mapping from the encoding to the actual values.
Signed-off-by: Taylor Simpson
---
target/hexagon/regmap.h
Gives a list of all the opcodes
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 12
1 file changed, 12 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 43acdd7..5439964 100755
--- a/target/hexagon/do_qemu.py
+++
Define EM_HEXAGON 164
Signed-off-by: Taylor Simpson
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 8fbfe60..d51e7d4 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -170,6 +170,8 @@ typedef struct mips_elf_abiflags_v0 {
#define
Add Taylor Simpson as the Hexagon target maintainer
Signed-off-by: Taylor Simpson
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e72b5e5..f48c564 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -172,6 +172,14 @@ F: include/hw/cris/
F:
Run the C preprocessor across the instruction definition files and macro
definitoin file to expand macros and prepare the semantics_generated.pyinc
file. The
resulting file contains one entry with the semantics for each instruction and
one line with the instruction attributes associated with
On Sat, 30 Nov 2019, BALATON Zoltan wrote:
That's all I could find out so far, any help to get further is appreciated.
I've created a ticket at my qmiga.osdn.io page where I've summarised
previous discussion at one place which could be used to track what we know
about it. See here:
I've started working on this issue and have some progress. Fedora 31
guest is already able to see a battery device but its state currently
hardcoded. I think i will finish this in a few weeks.
** Attachment added: "qemu-battery-poc.png"
On Mon, Feb 10, 2020 at 07:57:31PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> There's an assert in autoconverge that checks that we quit the
> iteration when we go below the expected threshold. Philippe
> saw a case where this assert fired with the measured
On Mon, Feb 10, 2020 at 04:29:53PM -0600, Eric Blake wrote:
> On 2/10/20 4:12 PM, Richard W.M. Jones wrote:
> >On Mon, Feb 10, 2020 at 03:37:20PM -0600, Eric Blake wrote:
> >>For now, only 2 of those 16 bits are defined: NBD_INIT_SPARSE (the
> >>image has at least one hole) and NBD_INIT_ZERO (the
On Mon, Feb 10, 2020 at 07:44:59PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> rdma_accept_incoming_migration is called from an fd handler and
> can't return an Error * anywhere.
> Currently it's leaking Error's in errp/local_err - there's
> no point putting
I've changed title to avoid derailing the original thread as this is more
about pegasos2 issue now but left cc list for now. Let me know if you
don't want to be cc'd.
On Mon, 10 Feb 2020, John Snow wrote:
On 2/10/20 10:38 AM, BALATON Zoltan wrote:
On Sat, 8 Feb 2020, BALATON Zoltan wrote:
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