From: Philippe Mathieu-Daudé
The board revision encode the amount of RAM. Add a helper
to extract the RAM size, and use it.
Since the amount of RAM is fixed (it is impossible to physically
modify to have more or less RAM), do not allow sizes different
than the one anounced by the manufacturer.
From: Guenter Roeck
Initialize EHCI controllers on AST2400 and AST2500 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
successfully instantiates a USB interface.
ehci-platform 1e6a3000.usb: EHCI Host Controller
ehci-platform 1e6a3000.usb: new USB bus
From: Philippe Mathieu-Daudé
The board revision encode the board version. Add a helper
to extract the version, and use it.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-4-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/raspi.c | 31
On Wed, 12 Feb 2020 at 16:42, Paolo Bonzini wrote:
>
> The following changes since commit 7bd9d0a9e26c7a3c67c0f174f0009ba19969b158:
>
> Merge remote-tracking branch
> 'remotes/huth-gitlab/tags/pull-request-2020-02-04' into staging (2020-02-04
> 16:12:31 +)
>
> are available in the Git
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-19-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 6 ++
target/arm/internals.h | 3 +++
target/arm/helper.c| 21
From: Philippe Mathieu-Daudé
The board revision encode the processor type. Add a helper
to extract the type, and use it.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-6-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/raspi.c | 18
The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits:
* the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is
8 or 16 bits
* the VMID field in VTTBR_EL2 is extended to 16 bits
* VTCR_EL2.VS lets the guest specify whether to use the full 16 bits,
or use the
From: Richard Henderson
The only remaining use was in op_helper.c. Use PSTATE_SS
directly, and move the commentary so that it is more obvious
what is going on.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20200208125816.14954-10-richard.hender...@linaro.org
From: Philippe Mathieu-Daudé
QOM'ify RaspiMachineState. Now machines inherit of RaspiMachineClass.
Cc: Igor Mammedov
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Igor Mammedov
Message-id: 20200208165645.15657-8-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
From: Philippe Mathieu-Daudé
We hardcode the board revision as 0xa21041 for the raspi2, and
0xa02082 for the raspi3:
166 static void raspi_init(MachineState *machine, int version)
167 {
...
194 int board_rev = version == 3 ? 0xa02082 : 0xa21041;
These revision codes are for the 2B
From: Richard Henderson
To implement PAN, we will want to swap, for short periods
of time, to a different privileged mmu_idx. In addition,
we cannot do this with flushing alone, because the AT*
instructions have both PAN and PAN-less versions.
Add the ARMMMUIdx*_PAN constants where necessary
From: Philippe Mathieu-Daudé
When booting without device tree, the Linux kernels uses the $R1
register to determine the machine type. The list of values is
registered at [1].
There are two entries for the Raspberry Pi:
- https://www.arm.linux.org.uk/developer/machines/list.php?mid=3138
name:
From: Philippe Mathieu-Daudé
The count of ARM cores is encoded in the board revision. Add a
helper to extract the number of cores, and use it. This will be
helpful when we add the Raspi0/1 that have a single core.
Signed-off-by: Philippe Mathieu-Daudé
Message-id:
From: Philippe Mathieu-Daudé
We want to have a common class_init(). The only value that
matters (and changes) is the board revision.
Pass the board_rev as class_data to class_init().
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20200208165645.15657-9-f4...@amsat.org
Reviewed-by: Peter
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu64.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu64.c
From: Richard Henderson
Split this helper out of msr_mask in translate.c. At the same time,
transform the negative reductive logic to positive accumulative logic.
It will be usable along the exception paths.
While touching msr_mask, fix up formatting.
Signed-off-by: Richard Henderson
From: Philippe Mathieu-Daudé
There is no point in creating the SoC object before allocating the RAM.
Move the call to keep all the SoC-related calls together.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Igor Mammedov
Message-id: 20200208165645.15657-7-f4...@amsat.org
Reviewed-by: Peter
From: Richard Henderson
For static const regdefs, file scope is preferred.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 57
From: Guenter Roeck
Initialize EHCI controllers on AST2600 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2600-evb
into Linux successfully instantiates a USB interface after
the necessary changes are made to its devicetree files.
ehci_hcd: USB 2.0 'Enhanced' Host
From: Richard Henderson
The PAN bit is preserved, or set as per SCTLR_ELx.SPAN,
plus several other conditions listed in the ARM ARM.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20200208125816.14954-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
Add definitions for all of the fields, up to ARMv8.5.
Convert the existing RESERVED register to a full register.
Query KVM for the value of the register for the host.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Chen Qun
It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-properties",
"arguments":{"typename":"exynos4210.uart"}}'
ASAN shows memory leak stack:
#1 0xfffd896d71cb in g_malloc0 (/lib64/libglib-2.0.so.0+0x571cb)
#2 0xaaad270beee3 in
From: Richard Henderson
This is a minor enhancement over ARMv8.1-PAN.
The *_PAN mmu_idx are used with the existing do_ats_write.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Heyi Guo
The original code defines a named object for the resource template but
then returns the resource template object itself; the resulted output
is like below:
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
From: Richard Henderson
We need only override the current condition under which
TBFLAG_A64.UNPRIV is set.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-20-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 41
From: Richard Henderson
For aarch64, there's a dedicated msr (imm, reg) insn.
For aarch32, this is done via msr to cpsr. Writes from el0
are ignored, which is already handled by the CPSR_USER mask.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Heyi Guo
According to ACPI spec, _ADR should be used for device on a bus that
has a standard enumeration algorithm, but not for device which is on
system bus and must be enumerated by OSPM. And it is not recommended
to contain both _HID and _ADR in a single device.
See ACPI 6.3, section
From: Richard Henderson
If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
This includes enablement of ARMv8.1-PAN.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.c | 4
target/arm/cpu64.c | 5 +
2 files
From: Richard Henderson
Use this along the exception return path, where we previously
accepted any values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/internals.h |
From: Heyi Guo
The address field in each _PRT mapping package should be constructed
with high word for device# and low word for function#, so it is wrong
to use bus_no as the high word. The existing code adds a bunch useless
entries with device #s above 31. Enumerate all possible slots
(i.e.
From: Richard Henderson
Examine the PAN bit for EL1, EL2, and Secure EL1 to
determine if it applies.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
Include definitions for all of the bits in ID_MMFR3.
We already have a definition for ID_AA64MMFR1.PAN.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-4-richard.hender...@linaro.org
Signed-off-by:
From: Richard Henderson
Using ~0 as the mask on the aarch64->aarch32 exception return
was not even as correct as the CPSR_ERET_MASK that we had used
on the aarch32->aarch32 exception return.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Roman Kapl
Uses the i.MX2 rudimentary watchdog driver.
Signed-off-by: Roman Kapl
Message-id: 20200207095529.11309-1-...@sysgo.com
Reviewed-by: Peter Maydell
[PMM: removed accidental duplicate #include line]
Signed-off-by: Peter Maydell
---
include/hw/arm/fsl-imx6.h | 3 +++
From: Heyi Guo
Differences between disassembled ASL files:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of DSDT, Thu Jan 23 16:00:04 2020
+ * Disassembly of DSDT.new, Thu Jan 23 16:47:12 2020
*
* Original Table Header:
* Signature
From: Richard Henderson
Use a common predicate for querying stage1-ness.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/internals.h |
From: Richard Henderson
CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED.
The function also takes into account bits that the cpu
does not support.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20200208125816.14954-8-richard.hender...@linaro.org
Signed-off-by:
From: Heyi Guo
The sub device "RP0" under PCI0 in ACPI/DSDT does not contain any
method or property other than "_ADR", so it is safe to remove it.
Signed-off-by: Heyi Guo
Acked-by: "Michael S. Tsirkin"
Reviewed-by: Michael S. Tsirkin
Message-id: 20200204014325.16279-3-guoh...@huawei.com
From: Heyi Guo
Using _UID of 0 for all PCI interrupt link devices absolutely violates
the spec. Simply increase one by one.
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
Message-id: 20200204014325.16279-6-guoh...@huawei.com
Signed-off-by: Peter Maydell
---
hw/arm/virt-acpi-build.c
'remotes/kraxel/tags/ui-20200212-pull-request'
into staging (2020-02-13 11:06:32 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20200213
for you to fetch changes up to dc7a88d0810ad272bdcd2e0869359af78fdd9114:
target
From: Richard Henderson
The J bit signals Jazelle mode, and so of course is RES0
when the feature is not enabled.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20200208125816.14954-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Heyi Guo
We are going to change ARM virt ACPI DSDT table, which will cause make
check to fail, so temporarily add related golden masters to ignore
list.
Signed-off-by: Heyi Guo
Reviewed-by: Michael S. Tsirkin
Message-id: 20200204014325.16279-2-guoh...@huawei.com
Signed-off-by: Peter
From: Roman Kapl
Documentation says for WDA '0: Assert WDOG output.' and for SRS
'0: Assert system reset signal.'.
Signed-off-by: Roman Kapl
Message-id: 20200207095409.11227-1-...@sysgo.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/misc/imx2_wdt.c | 2 +-
1 file
On Thu, 13 Feb 2020 at 14:26, Guenter Roeck wrote:
> What really puzzles me is that there is no trace output for
> flash data accesses (trace_pflash_data_read and trace_pflash_data_write),
> meaning the actual flash data access must be handled elsewhere.
> Can someone give me a hint where that
On 2020/2/13 16:18, Andrew Jones wrote:
On Thu, Feb 13, 2020 at 03:36:26PM +0800, Ying Fang wrote:
On ARM64 platform, cpu frequency is retrieved via ACPI CPPC.
A virtual cpufreq device based on ACPI CPPC is created to
present cpu frequency info to the guest.
The default frequency is set to
On Thu, 13 Feb 2020 11:58:36 +1100
David Gibson wrote:
> PAPR specifies a kind of odd, paravirtualized PCI bus, which looks to
> the guess mostly like classic PCI, even if some of the individual
> devices on the bus are PCI Express. One consequence of that is that
> virtio-pci devices still
On Thu, 13 Feb 2020 at 14:16, Philippe Mathieu-Daudé wrote:
> On 2/13/20 2:59 PM, Peter Maydell wrote:
> > The natural way to implement this is to have the .class_data
> > be a pointer to a struct which is in an array and defines
> > relevant per-class stuff, the same way we do in
> >
On Thu, Feb 13, 2020 at 02:40:45AM +, Liu, Yi L wrote:
> > From: Peter Xu
> > Sent: Wednesday, February 12, 2020 5:57 AM
> > To: Liu, Yi L
> > Subject: Re: [RFC v3 14/25] intel_iommu: add virtual command capability
> > support
> >
> > On Wed, Jan 29, 2020 at 04:16:45AM -0800, Liu, Yi L
* Markus Armbruster (arm...@redhat.com) wrote:
> "Dr. David Alan Gilbert" writes:
>
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/migration.c | 15 +++
> >> monitor/hmp-cmds.c| 4
> >> qapi/migration.json | 29
Eduardo Habkost writes:
> On Wed, Feb 12, 2020 at 08:39:55AM +0100, Philippe Mathieu-Daudé wrote:
>> Cc'ing Eduardo & Markus.
>>
>> On 2/12/20 7:44 AM, Chenqun (kuhn) wrote:
>> > > -Original Message-
>> > > From: Philippe Mathieu-Daudé [mailto:phi...@redhat.com]
>> > > Sent: Wednesday,
On 2/13/20 1:51 AM, Paolo Bonzini wrote:
On 13/02/20 08:40, Alexey Kardashevskiy wrote:
memory-region: system
- (prio 0, i/o): system
-01ff (prio 0, romd): omap_sx1.flash0-1
-01ff (prio 0,
This patch adds tests for following 14 implemented alsa timer ioctls:
* SNDRV_TIMER_IOCTL_PVERSION* SNDRV_TIMER_IOCTL_INFO
* SNDRV_TIMER_IOCTL_NEXT_DEVICE * SNDRV_TIMER_IOCTL_PARAMS
* SNDRV_TIMER_IOCTL_TREAD * SNDRV_TIMER_IOCTL_STATUS
* SNDRV_TIMER_IOCTL_GINFO *
This series covers tests for implemented rtc and alsa timer ioctls. The names
of ioctls that are covered by these tests can be found in patch descriptions.
The functionalities of each ioctl that is tested can be found in patches that
implement them.
Some of the features that are accessible
This patch adds tests for following 22 implemented rtc ioctls:
* RTC_AIE_ON * RTC_ALM_SET * RTC_WKALM_SET
* RTC_AIE_OFF* RTC_ALM_READ * RTC_WKALM_RD
* RTC_UIE_ON * RTC_RD_TIME * RTC_PLL_GET
* RTC_UIE_OFF* RTC_SET_TIME * RTC_PLL_SET
* RTC_PIE_ON *
QEMU has a funny new build error message when I use the upstream kernel headers:
CC block/file-posix.o
In file included from /home/cborntra/REPOS/qemu/include/qemu/timer.h:4,
from /home/cborntra/REPOS/qemu/include/qemu/timed-average.h:29,
from
On 2/13/20 2:59 PM, Peter Maydell wrote:
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
With the exception of the ignore_memory_transaction_failures
flag set for the raspi2, both machine_class_init() methods
are now identical. Merge them to keep a unique method.
Signed-off-by:
"Dr. David Alan Gilbert" writes:
> * Juan Quintela (quint...@redhat.com) wrote:
>> Signed-off-by: Juan Quintela
>> ---
>> migration/migration.c | 15 +++
>> monitor/hmp-cmds.c| 4
>> qapi/migration.json | 29 ++---
>> 3 files changed, 45
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
>
> Hi,
>
> This series is a preparatory to easily add the raspi0/raspi1/raspi4
> boards (see [1]).
>
> Igor has been working in his "refactor main RAM allocation to use
> hostmem backend" series, and now v4 [2] is almost reviewed.
>
>
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
>
> With the exception of the ignore_memory_transaction_failures
> flag set for the raspi2, both machine_class_init() methods
> are now identical. Merge them to keep a unique method.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On Thu, Feb 13, 2020 at 06:47:10AM -0600, Eric Blake wrote:
> On 2/13/20 2:01 AM, Roman Kagan wrote:
> > On Wed, Feb 12, 2020 at 03:44:19PM -0600, Eric Blake wrote:
> > > On 2/11/20 5:54 AM, Roman Kagan wrote:
> > > > Devices (virtio-blk, scsi, etc.) and the block layer are happy to use
> > > >
On 2/13/20 2:40 PM, Peter Maydell wrote:
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
The board revision encode the board version. Add a helper
to extract the version, and use it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 31 +++
On Thu, Feb 13, 2020 at 03:49:52PM +0800, Yubo Miao wrote:
> From: miaoyubo
>
> Since devices could not directly plugged into pxb-pcie, under arm, one
> pcie-root port is plugged into pxb-pcie. Due to the bus for each pxb-pcie
> is defined as 2 in acpi dsdt tables(one for pxb-pcie, one for
On Tue, 14 Jan 2020 at 10:20 Stefan Hajnoczi
wrote:
> On Fri, Jan 10, 2020 at 10:34 AM Marc-André Lureau
> wrote:
> > On Wed, Jan 8, 2020 at 5:57 AM V. wrote:
>
> Hi V.,
> I think I remember you from Etherboot/gPXE days :).
>
> > > 3.
> > > Now if Cross Cable is actually a new and (after a
On Wed, Feb 12, 2020 at 11:31:00PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/12/20 4:34 PM, Stefan Hajnoczi wrote:
> > On Tue, Feb 11, 2020 at 11:10:54AM +, Alex Bennée wrote:
> > > Otherwise any -D settings the user may have made get ignored.
> > >
> > > Signed-off-by: Alex Bennée
> > >
Hi Peter, Michael,
On 2/11/20 6:31 PM, Auger Eric wrote:
> Hi Peter,
>
> On 2/11/20 4:00 PM, Peter Maydell wrote:
>> On Sat, 8 Feb 2020 at 12:01, Eric Auger wrote:
>>>
>>> Adds the "virtio,pci-iommu" node in the host bridge node and
>>> the RID mapping, excluding the IOMMU RID.
>>>
>>> This is
From: miaoyubo
Currently virt machine is not supported by pxb-pcie,
and only one main host bridge described in ACPI tables.
Under this circumstance, different io numas for differnt devices
is not possible, in order to present io numas to the guest,
especially for host pssthrough devices.
** Tags added: ikeradar
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1805256
Title:
qemu-img hangs on rcu_call_ready_event logic in Aarch64 when
converting images
Status in kunpeng920:
From: miaoyubo
Since devices could not directly plugged into pxb-pcie, under arm, one
pcie-root port is plugged into pxb-pcie. Due to the bus for each pxb-pcie
is defined as 2 in acpi dsdt tables(one for pxb-pcie, one for pcie-root-port),
only one device could be plugged into one pxb-pcie.
From: miaoyubo
Currently pxb-pcie is not supported by arm and only one
main host bridge is described in acpi tables, which means
it is not impossible to present different io numas for different
devices. This series of patches make arm to support PXB-PCIE.
Users can configure pxb-pcie with
On Tue, Feb 11, 2020 at 03:35:09PM -0500, Alexander Bulekov wrote:
> diff --git a/tests/qtest/fuzz/virtio_scsi_fuzz.c
> b/tests/qtest/fuzz/virtio_scsi_fuzz.c
> new file mode 100644
> index 00..f62f512a26
> --- /dev/null
> +++ b/tests/qtest/fuzz/virtio_scsi_fuzz.c
> @@ -0,0 +1,214 @@
> +/*
On Sat, 8 Feb 2020 at 16:57, Philippe Mathieu-Daudé wrote:
>
> The board revision encode the board version. Add a helper
> to extract the version, and use it.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/raspi.c | 31 +++
> 1 file changed, 27
On Wed, 12 Feb 2020 at 16:18, Gerd Hoffmann wrote:
>
> The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
>
> Merge remote-tracking branch
> 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging
> (2020-02-10 18:09:14 +)
>
> are available in the Git
On 12.02.20 19:03, David Hildenbrand wrote:
> On 12.02.20 14:42, David Hildenbrand wrote:
>> We already allow resizable ram blocks for anonymous memory, however, they
>> are not actually resized. All memory is mmaped() R/W, including the memory
>> exceeding the used_length, up to the max_length.
On Thu, Feb 13, 2020 at 02:26:10PM +0100, Johannes Berg wrote:
> On Thu, 2020-01-23 at 09:17 +0100, Johannes Berg wrote:
> > Hi,
> >
> > Here's a repost of all the patches I sent back in August, with the
> > in-band notifications rebased over the reset patch, so IDs have now
> > changed a bit.
>
Daniel P. Berrangé writes:
> On Thu, Jan 30, 2020 at 09:03:00AM +0100, Markus Armbruster wrote:
>> Juan Quintela writes:
>>
>> > It will indicate which level use for compression.
>> >
>> > Signed-off-by: Juan Quintela
>>
>> This is slightly confusing (there is no zlib compression), unless
On Thu, 13 Feb 2020 at 13:12, Peter Maydell wrote:
>
> On Tue, 11 Feb 2020 at 19:42, Richard Henderson
> wrote:
> >
> > Select should always be 0 for a regime with one range.
> >
> > Signed-off-by: Richard Henderson
>
> This change makes sense, and matches what aa32_va_parameters() does,
> but
On Thu, 2020-01-23 at 09:17 +0100, Johannes Berg wrote:
> Hi,
>
> Here's a repost of all the patches I sent back in August, with the
> in-band notifications rebased over the reset patch, so IDs have now
> changed a bit.
Ping?
The patches still apply on top of latest qemu.
I wanted to send some
If one is compiling more than one tree from the same source, it is
possible that they need different submodules. Change the check to see
that all modules that we are interested in are updated, discarding the
ones that we don't care about.
Signed-off-by: Juan Quintela
---
v1->v2:
patchw
From: Zhimin Feng
If the migration is cancelled when it is in the completion phase,
the migration state is set to MIGRATION_STATUS_CANCELLING.
The VM maybe wait for the 'pause_sem' semaphore in migration_maybe_pause
function, so that VM always is paused.
Reported-by: Euler Robot
Signed-off-by:
From: Pan Nengyuan
spotted by asan, 'check-qtest-aarch64' runs fail if sanitizers is enabled.
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
Reviewed-by: Juan Quintela
Reviewed-by: Laurent Vivier
Signed-off-by: Juan Quintela
---
tests/qtest/migration-test.c | 14 --
1
From: "Dr. David Alan Gilbert"
There's an assert in autoconverge that checks that we quit the
iteration when we go below the expected threshold. Philippe
saw a case where this assert fired with the measured value
slightly over the threshold. (about 3k out of a few million).
I can think of two
The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
Merge remote-tracking branch
'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10
18:09:14 +)
are available in the Git repository at:
https://github.com/juanquintela/qemu.git
From: "Dr. David Alan Gilbert"
rdma_accept_incoming_migration is called from an fd handler and
can't return an Error * anywhere.
Currently it's leaking Error's in errp/local_err - there's
no point putting them in there unless we can report them.
Turn most into fprintf's, and the last into an
From: Keqian Zhu
qemu_savevm_nr_failover_devices() is originally designed to
get the number of failover devices, but it actually returns
the number of "unplug-pending" failover devices now. Moreover,
what drives migration state to wait-unplug should be the number
of "unplug-pending" failover
On Thu, 13 Feb 2020 at 10:09, Philippe Mathieu-Daudé wrote:
>
> On 2/13/20 3:56 AM, kuhn.chen...@huawei.com wrote:
> > From: Chen Qun
> >
> > It's easy to reproduce as follow:
> > virsh qemu-monitor-command vm1 --pretty '{"execute":
> > "device-list-properties",
> >
On Thu, 13 Feb 2020 at 13:12, Peter Maydell wrote:
>
> On Tue, 11 Feb 2020 at 19:42, Richard Henderson
> wrote:
> >
> > Select should always be 0 for a regime with one range.
> >
> > Signed-off-by: Richard Henderson
>
> This change makes sense, and matches what aa32_va_parameters() does,
> but
On Tue, 11 Feb 2020 at 19:42, Richard Henderson
wrote:
>
> Select should always be 0 for a regime with one range.
>
> Signed-off-by: Richard Henderson
This change makes sense, and matches what aa32_va_parameters() does,
but I think we need to update some of the callsites.
(1) In
On Tue, 11 Feb 2020 at 19:42, Richard Henderson
wrote:
>
> For the purpose of rebuild_hflags_a64, we do not need to compute
> all of the va parameters, only tbi. Moreover, we can compute them
> in a form that is more useful to storing in hflags.
>
> This eliminates the need for
Gerd Hoffmann writes:
> Hi,
>
>> Thanks to the QMP coroutine support, the screendump handler can
>> trigger a graphic_hw_update(), yield and let the main loop run until
>> update is done. Then the handler is resumed, and the ppm_save() will
>> write the screen image to disk in the coroutine
Public bug reported:
After upgrade qemu to v4.2.0, vhost-user multi-queues interrupt failed
with event idx interrupt mode when reconnection happens.
Test Environment:
DPDK version: DPDK v19.11
Other software versions: qemu 4.2.0.
OS: Linux 4.15.0-20-generic
Compiler: gcc (Ubuntu 7.3.0-16ubuntu3)
On 2/13/20 2:01 AM, Roman Kagan wrote:
On Wed, Feb 12, 2020 at 03:44:19PM -0600, Eric Blake wrote:
On 2/11/20 5:54 AM, Roman Kagan wrote:
Devices (virtio-blk, scsi, etc.) and the block layer are happy to use
32-bit for logical_block_size, physical_block_size, and min_io_size.
However, the
Le 13/02/2020 à 13:29, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> v2->v3:
>
> - corrected number of arguments for two mips syscalls
>
> v1->v2:
>
> - corrected mips parts based on Laurent's review
>
> This series is a spin-off of another larger linux-user series
> that
On Wed, 12 Feb 2020 at 14:44, David Hildenbrand wrote:
>
> We want to actually resize ram blocks (make everything between
> used_length and max_length inaccessible) - however, not all ram block
> notifiers will support that. Let's teach the notifier that ram blocks
> are indeed resizable, but
On 13.02.2020 14:45, Stefan Hajnoczi wrote:
On Thu, Feb 13, 2020 at 12:28:25PM +0300, Denis Plotnikov wrote:
On 13.02.2020 12:08, Stefan Hajnoczi wrote:
On Thu, Feb 13, 2020 at 11:08:35AM +0300, Denis Plotnikov wrote:
On 12.02.2020 18:43, Stefan Hajnoczi wrote:
On Tue, Feb 11, 2020 at
Hi Palmer,
On Thu, Feb 13, 2020 at 1:30 AM Palmer Dabbelt wrote:
>
> The following changes since commit 81a23caf47956778c5a5056ad656d1ef92bf9659:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2020-02-10 17:08:51 +)
>
> are available in the Git
From: Aleksandar Markovic
Update x86_64 syscall numbers based on Linux kernel v5.5.
CC: Paolo Bonzini
CC: Richard Henderson
CC: Eduardo Habkost
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
---
linux-user/x86_64/syscall_nr.h | 24
1 file changed,
From: Aleksandar Markovic
Update xtensa syscall numbers based on Linux kernel v5.5.
CC: Max Filippov
Acked-by: Max Filippov
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
---
linux-user/xtensa/syscall_nr.h | 38 --
1 file changed, 36
From: Aleksandar Markovic
Currently, there is no usage of TARGET_NR_syscall_count for target
xtensa, and there is no obvious indication if there is some planned
usage in future.
CC: Max Filippov
Acked-by: Max Filippov
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
---
From: Aleksandar Markovic
Update arm syscall numbers based on Linux kernel v5.5.
CC: Peter Maydell
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
---
linux-user/arm/syscall_nr.h | 44
1 file changed, 44 insertions(+)
diff --git
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