Hi Palmer,
On Mon, Feb 24, 2020 at 9:40 PM Bin Meng wrote:
>
>
> This series advances the roms/opensbi submodule to the v0.6 release,
> and builds and captures platform firmware binaries from that release.
>
> A 32-bit sifive_u bios image has also been added, so that we can have
> 32-bit test
On Fri, 28 Feb 2020, BALATON Zoltan wrote:
I think I now understand the problem with via-ide at least and the following
FYI, I came up with this patch:
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=161714
that fixes my problem with via-ide. The first patch also touches CMD646
This small series implements the quirky mode of via-ide found at least
on pegasos2 which is needed for guests that expect this and activate
work arounds on that platform so don't work unless this is emulated.
(Symptom is missing IDE interrupts.) We need a flag to turn this mode
on or off so the
Some machines operate in "non 100% native mode" where interrupts are
fixed at legacy IDE interrupts and some guests expect this behaviour
without checking based on knowledge about hardware. Even Linux has
arch specific workarounds for this that are activated on such boards
so this needs to be
We'll need a flag for implementing some device specific behaviour in
via-ide but we already have a currently CMD646 specific field that can
be repurposed for this and leave room for furhter flags if needed in
the future. This patch changes the "secondary" field to "flags" and
define the flags for
> +##
> +# zstd check
> +
> +if test "$zstd" != "no" ; then
> +if $pkg_config --exist libzstd ; then
The option is spelled --exists. This is generating an error during configure.
r~
On 2/28/20 3:46 AM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (18):
> vl: Add missing "hw/boards.h" include
> hw/southbridge/ich9: Removed unused headers
> hw/i386/ioapic_internal: Remove unused "hw/i386/ioapic.h" header
> hw/timer: Remove unused "ui/console.h" header
>
On 2/28/20 4:53 AM, Philippe Mathieu-Daudé wrote:
> We only build the little-endian softmmu configurations.
> Checking for big endian is pointless, remove the unused code.
>
> Philippe Mathieu-Daudé (5):
> hw/arm/gumstix: Simplify since the machines are little-endian only
> hw/arm/mainstone:
On 2/29/20 4:34 AM, Robert Hoo wrote:
> And intialize buffer_is_zero() with it, when Intel AVX512F is
> available on host.
>
> This function utilizes Intel AVX512 fundamental instructions which
> is faster than its implementation with AVX2 (in my unit test, with
> 4K buffer, on CascadeLake SP,
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makefile.objs
This is the first part of v6 patchset. The changelog of v6 is only coverd
the part1.
Features:
* support specification riscv-v-spec-0.7.1.
* support basic vector extension.
* support Zvlsseg.
* support Zvamo.
* not support Zvediv as it is changing.
* SLEN always equals VLEN.
*
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
Thank you for your reply. It works well with "Ctrl-A c" to swith to and
from QEMU monitor in xterm terminal.
The problem is elsewhere, with the option -monitor. With "-monitor ", whether is or not the tty from which qemu is
started, the characters I type are misinterpreted. Maybe I must report
Hi Stefan,
On 2/28/20 6:52 PM, Stefan Berger wrote:
> On 2/28/20 9:49 AM, Auger Eric wrote:
>> Hi Stefan,
>> On 2/28/20 3:37 PM, Stefan Berger wrote:
>>> On 2/27/20 3:07 AM, Auger Eric wrote:
Hi Stefan,
On 2/26/20 11:44 PM, Stefan Berger wrote:
> On 2/26/20 3:59 PM, Eric Auger
The RCC (reset and clock control) is a hardware peripheral reset and
clock configuration controller available on the STM32F4xx series
devices.
This commit adds preliminary support for the RCC peripheral emulation,
in order to support proper emulation of the firmware images that use
the STM32Cube
On 2020/2/29 2:46, Richard Henderson wrote:
On 2/28/20 1:19 AM, LIU Zhiwei wrote:
+#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ETYPE, MTYPE, H, DO_OP, SUF) \
+static void vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
+ uint32_t wd, uint32_t idx, CPURISCVState *env,
If it is enabled, config-host.mak will have CONFIG_AVX512F_OPT defined.
AVX512F instruction set is available since Intel Skylake, and can be enabled in
compiling with -mavx512f.
More info:
1) Introduce {enable,disable}-avx512f configure option
2) Implement new buffer_zero_avx512() with AVX512F instructions
Changes in v4:
In init_cpuid_cache(), stringently test AVX512F OS level enablement.
Changes in v3:
In init_accel(), init length_to_accel value in every accel case, because
in
And intialize buffer_is_zero() with it, when Intel AVX512F is
available on host.
This function utilizes Intel AVX512 fundamental instructions which
is faster than its implementation with AVX2 (in my unit test, with
4K buffer, on CascadeLake SP, ~36% faster, buffer_zero_avx512() V.S.
Am 29.02.20 um 12:17 schrieb Stefan Hajnoczi:
> The L2TPv3 RFC number is 3931:
> https://tools.ietf.org/html/rfc3931
>
> Reported-by: Henrik Johansson
> Signed-off-by: Stefan Hajnoczi
> ---
> qemu-options.hx | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
On Fri, 28 Feb 2020 at 21:20, Stefan Weil wrote:
> Maybe it is sufficient to update qemu.nsi after that series was merged.
If you're happy to do it that way round I think that would certainly
make life easier in trying to get this series merged without too
much delay.
> Do you think that all
The L2TPv3 RFC number is 3931:
https://tools.ietf.org/html/rfc3931
Reported-by: Henrik Johansson
Signed-off-by: Stefan Hajnoczi
---
qemu-options.hx | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index ac315c1ac4..55a539e04f 100644
---
On Sat, Feb 29, 2020 at 10:50:40AM +0100, Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle
> ---
> hw/display/artist.c | 18 ++
> 1 file changed, 6 insertions(+), 12 deletions(-)
That was supposed to only go to Helge for testing, so please ignore.
Sven
Signed-off-by: Sven Schnelle
---
hw/display/artist.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/hw/display/artist.c b/hw/display/artist.c
index f3a1375224..6cc85eb292 100644
--- a/hw/display/artist.c
+++ b/hw/display/artist.c
@@ -340,14 +340,13 @@
On 28/02/20 22:02, Sunil Muthuswamy wrote:
>> -Original Message-
>> From: Paolo Bonzini
>> Sent: Friday, February 28, 2020 2:45 AM
>> To: Sunil Muthuswamy ; Richard Henderson
>> ; Eduardo Habkost
>>
>> Cc: qemu-devel@nongnu.org; Stefan Weil
>> Subject: [EXTERNAL] Re: PATCH] WHPX: TSC
On Tue, Feb 18, 2020 at 11:39:24AM -0800, Richard Henderson wrote:
> From: Philippe Mathieu-Daudé
>
> Signed-off-by: Philippe Mathieu-Daudé
> Message-Id: <20200214001303.12873-5-f4...@amsat.org>
> Signed-off-by: Richard Henderson
> ---
> hw/display/artist.c | 3 +++
> 1 file changed, 3
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