From: "Dr. David Alan Gilbert"
After c9808d60281 we have both an object representing the serial-isa
device and a separate object representing the underlying common serial
uart. Both of these have vmsd's associated with them and thus the
migration stream ends up with two copies of the migration
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 251
4 files
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 ++
4 files
On Mon, 30 Mar 2020 at 17:21, Philippe Mathieu-Daudé wrote:
>
> On 3/30/20 6:08 PM, Peter Maydell wrote:
> > On Mon, 30 Mar 2020 at 16:30, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Since commit 3f940dc98, we added support for vAttach packet
> >> to select a particular thread/cpu/core. However
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 49
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 145
target/riscv/vector_helper.c| 83 ++
* Philippe Mathieu-Daudé (phi...@redhat.com) wrote:
> Cc'ing the ppl who responded the thread you quoted.
>
> On 3/30/20 4:11 PM, Markus Armbruster wrote:
> > Philippe Mathieu-Daudé writes:
> > ---
> > qga/commands-posix.c | 8 +++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
>
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 116
target/riscv/vector_helper.c| 111
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 +
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 141
4 files
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 117
4 files
On Mon, Mar 30, 2020 at 1:28 AM Anup Patel wrote:
>
> As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has
> 12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1]
> is required to handle the 34bit intermediate physical address coming
> from Stage1 SV32 page table.
于 2020年3月31日 GMT+08:00 上午12:22:43, "Philippe Mathieu-Daudé"
写到:
>On 3/30/20 6:18 PM, Jiaxun Yang wrote:
>>
>>
>> 于 2020年3月30日 GMT+08:00 下午11:39:44, "Philippe Mathieu-Daudé"
> 写到:
>>> Hi Jiaxun Yang,
>>>
>>> On 3/24/20 1:22 PM, Jiaxun Yang wrote:
Loongson multimedia condition
Am 25.03.2020 um 00:21 hat John Snow geschrieben:
> Mark the verify functions as "private" with a leading underscore, to
> discourage their use.
>
> (Also, make pending patches not yet using the new entry points fail in a
> very obvious way.)
>
> Signed-off-by: John Snow
> Reviewed-by: Max
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 205
4 files
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 107
4 files changed, 122 insertions(+)
diff --git
Am 25.03.2020 um 00:20 hat John Snow geschrieben:
> Just a mild cleanup while I was here.
>
> Although we now have universal qmp logging on or off, many existing
> callers to hmp functions don't expect that output to be logged, which
> causes quite a few changes in the test output.
>
> For now,
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 100
4 files changed, 129 insertions(+)
diff
15:32 Pon, 30.03.2020. Peter Maydell је
написао/ла:
>
> Consensus in the thread seemed to lean towards having
> the 'configure/make' runes auto-create a build directory;
> if we want to do that we should probably not say anything in
> the release notes, because we'll cause people to change
>
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 +
target/riscv/vector_helper.c| 385
4 files
On Tue, Mar 24, 2020 at 08:48:36PM +0100, Philippe Mathieu-Daudé wrote:
> Similarly to commit 807e2b6fce0 for Windows, kindly return a
> QMP error message instead of crashing the whole process.
>
> Cc: qemu-sta...@nongnu.org
> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1594054
I find
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 137
target/riscv/vector_helper.c
On 3/30/20 6:08 PM, Peter Maydell wrote:
On Mon, 30 Mar 2020 at 16:30, Philippe Mathieu-Daudé wrote:
Since commit 3f940dc98, we added support for vAttach packet
to select a particular thread/cpu/core. However when using
the GDB physical memory mode, it is not clear which CPU
address space is
On 3/30/20 6:18 PM, Jiaxun Yang wrote:
于 2020年3月30日 GMT+08:00 下午11:39:44, "Philippe Mathieu-Daudé"
写到:
Hi Jiaxun Yang,
On 3/24/20 1:22 PM, Jiaxun Yang wrote:
Loongson multimedia condition instructions were previously
implemented as
write 0 to rd due to lack of documentation. So I just
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c|
于 2020年3月30日 GMT+08:00 下午11:39:44, "Philippe Mathieu-Daudé"
写到:
>Hi Jiaxun Yang,
>
>On 3/24/20 1:22 PM, Jiaxun Yang wrote:
>> Loongson multimedia condition instructions were previously
>implemented as
>> write 0 to rd due to lack of documentation. So I just confirmed with
>Loongson
>> about
Am 25.03.2020 um 00:20 hat John Snow geschrieben:
> Representing nested, recursive data structures in mypy is notoriously
> difficult; the best we can reliably do right now is denote the atom
> types as "Any" while describing the general shape of the data.
>
> Regardless, this fully annotates the
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 +
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 163
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c|
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 46 +
target/riscv/vector_helper.c
On Mon, 30 Mar 2020 at 16:30, Philippe Mathieu-Daudé wrote:
>
> Since commit 3f940dc98, we added support for vAttach packet
> to select a particular thread/cpu/core. However when using
> the GDB physical memory mode, it is not clear which CPU
> address space is used.
> Since the CPU address space
On 3/30/20 6:04 PM, Philippe Mathieu-Daudé wrote:
Cc'ing the ppl who responded the thread you quoted.
On 3/30/20 4:11 PM, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
> ---
> qga/commands-posix.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 90 +
target/riscv/vector_helper.c
On 30.03.20 17:38, Janosch Frank wrote:
> The cpu number reporting is handled by KVM and QEMU only fills in the
> VM name, uuid and other values.
>
> Unfortuantely KVM doesn't report reserved cpus and doesn't even know
s/Unfortuantely/Unfortunately/
> they exist until the are created via the
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 52
target/riscv/vector_helper.c
Cc'ing the ppl who responded the thread you quoted.
On 3/30/20 4:11 PM, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
> ---
> qga/commands-posix.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/qga/commands-posix.c b/qga/commands-posix.c
> index
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 11 ++
target/riscv/insn_trans/trans_rvv.inc.c | 113 +++
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 49 +++
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 186
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 25 ++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 291
target/riscv/vector_helper.c
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair
Vladimir Sementsov-Ogievskiy writes:
> It's possible that we'll try to set err twice (or more). It's bad, it
> will crash.
True.
> Instead, use warn_report().
Improvement even without the potential crash enabled by the loop.
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
>
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by:
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
Am 25.03.2020 um 00:20 hat John Snow geschrieben:
> This allows others to get repeatable results with pylint. If you run
> `pylint iotests.py`, you should see a 100% pass.
>
> Signed-off-by: John Snow
> Reviewed-by: Max Reitz
I see you said "should" and not "will", but I still get two
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from
The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/internals.h | 24
1 file changed, 24
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by:
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 15 +
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
Am 25.03.2020 um 00:20 hat John Snow geschrieben:
> This doesn't fix everything in here, but it does help clean up the
> pylint report considerably.
>
> This should be 100% style changes only; the intent is to make pylint
> more useful by working on establishing a baseline for iotests that we
>
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
Hi Jiaxun Yang,
On 3/24/20 1:22 PM, Jiaxun Yang wrote:
Loongson multimedia condition instructions were previously implemented as
write 0 to rd due to lack of documentation. So I just confirmed with Loongson
about their encoding and implemented them correctly.
If you have a binary using
The cpu number reporting is handled by KVM and QEMU only fills in the
VM name, uuid and other values.
Unfortuantely KVM doesn't report reserved cpus and doesn't even know
they exist until the are created via the ioctl.
So let's fix up the cpu values after KVM has written its values to the
3.2.2
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode
I thought backward migration wasn't supported.
Isn't it this commit?
commit 4cc017e505df7e5344e4dfe7fc1777c5f11f
Author: Marc-André Lureau
Date: Tue Oct 22 00:32:41 2019 +0200
serial: register vmsd with DeviceClass
Migration from old to new code works, however the other way
>>> +/* No valid pte or access denied due to protection */
>>> +if (cause_excp) {
>>> +ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
>>> +}
>>> +return 1;
>>> +}
>>> +
>>> +ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot);
>>> +
>>> +
On 3/30/20 4:18 PM, Greg Kurz wrote:
> On Mon, 30 Mar 2020 11:49:43 +0200
> Cédric Le Goater wrote:
>
>> This is moving code under a new ppc_radix64_xlate() routine shared by
>> the MMU Radix page fault handler and the get_phys_page_debug PPC
>> callback. The difference being that
Since commit 3f940dc98, we added support for vAttach packet
to select a particular thread/cpu/core. However when using
the GDB physical memory mode, it is not clear which CPU
address space is used.
Since the CPU address space is stored in CPUState::as, use
address_space_rw() instead of
On 30.03.2020 18:06, Markus Armbruster wrote:
Denis Plotnikov writes:
The patch adds some preparation parts for incompatible compression type
feature to qcow2 allowing the use different compression methods for
image clusters (de)compressing.
It is implied that the compression type is set
Lukas Straub writes:
> On Fri, 27 Mar 2020 15:40:38 -0600
> Benjamin wrote:
>
>> Qemu version 4.2.0 includes new functionality for something called TCG
>> Plugins. There are a few examples in the tests/plugins directory, and the
>> API is more or less defined in qemu-plugin.h.
>>
>> This
The tulip networking card emulation has an OOB issue in
'tulip_copy_tx_buffers' when the guest provide malformed descriptor.
This test will trigger a ASAN heap overflow crash. To trigger this
issue we can construct the data as following:
1. construct a 'tulip_descriptor'. Its control is set to
Denis Plotnikov writes:
> The patch adds some preparation parts for incompatible compression type
> feature to qcow2 allowing the use different compression methods for
> image clusters (de)compressing.
>
> It is implied that the compression type is set on the image creation and
> can be changed
inux-user-for-5.0-pull-request' into staging
> (2020-03-30 11:32:01 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20200330
>
> for you to fetch changes up to 88828bf133b64b7a860c166af3423ef1a4
On 30.03.2020 16:14, Vladimir Sementsov-Ogievskiy wrote:
30.03.2020 12:54, Denis Plotnikov wrote:
zstd significantly reduces cluster compression time.
It provides better compression performance maintaining
the same level of the compression ratio in comparison with
zlib, which, at the moment,
Marc-André Lureau writes:
> Direct leak of 4120 byte(s) in 1 object(s) allocated from:
> #0 0x7fa114931887 in __interceptor_calloc (/lib64/libasan.so.6+0xb0887)
> #1 0x7fa1144ad8f0 in g_malloc0 (/lib64/libglib-2.0.so.0+0x588f0)
> #2 0x561e3c9c8897 in qmp_object_add
>
On Mon, 30 Mar 2020 02:34:02 -0400
Yan Zhao wrote:
> On Mon, Mar 30, 2020 at 09:35:27AM +0800, Yan Zhao wrote:
> > On Sat, Mar 28, 2020 at 01:25:37AM +0800, Alex Williamson wrote:
> > > On Fri, 27 Mar 2020 11:19:34 +
> > > yan.y.z...@intel.com wrote:
> > >
> > > > From: Yan Zhao
> > >
Jason Wang 于2020年3月30日周一 下午3:25写道：
>
> On 2020/3/28 上午12:11, Li Qiang wrote:
> > The tulip networking card emulation has an OOB issue in
> > 'tulip_copy_tx_buffers' when the guest provide malformed descriptor.
> > This test will trigger a ASAN heap overflow crash.
>
>
> Hi Qiang:
>
> Thanks for
Paolo Bonzini writes:
> On 25/03/20 19:47, Marc-André Lureau wrote:
>> If object-add failed, no need to create a return value that may later
>> be leaked.
>>
>> Signed-off-by: Marc-André Lureau
>> ---
>> qom/qom-qmp-cmds.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff
On Mon, Mar 30, 2020 at 12:36:23PM +0200, Auger Eric wrote:
> I think in general, as long as the kernel dependencies are not resolved,
> the QEMU series is supposed to stay in RFC state.
Yeah I agree. I think the subject is not extremely important, but we
definitely should wait for the kernel
John Snow writes:
> This allows others to get repeatable results with pylint. If you run
> `pylint iotests.py`, you should see a 100% pass.
Nice.
>
> Signed-off-by: John Snow
> Reviewed-by: Max Reitz
> ---
> tests/qemu-iotests/pylintrc | 22 ++
> 1 file changed, 22
John Snow writes:
> This doesn't fix everything in here, but it does help clean up the
> pylint report considerably.
>
> This should be 100% style changes only; the intent is to make pylint
> more useful by working on establishing a baseline for iotests that we
> can gate against in the future.
Am 30.03.2020 um 15:42 hat Daniel P. Berrangé geschrieben:
> On Mon, Mar 30, 2020 at 02:31:52PM +0100, Peter Maydell wrote:
> > On Mon, 30 Mar 2020 at 14:26, Markus Armbruster wrote:
> > >
> > > Peter Maydell writes:
> > >
> > > > AIUI from Paolo, the intention is to deprecate and eventually
> >
For best case its really a good idea to configure default number of
queues to the number of CPU's.
For the series:
Reviewed-by: Pankaj Gupta
On Mon, 30 Mar 2020 11:49:43 +0200
Cédric Le Goater wrote:
> This is moving code under a new ppc_radix64_xlate() routine shared by
> the MMU Radix page fault handler and the get_phys_page_debug PPC
> callback. The difference being that get_phys_page_debug does not
> generate exceptions.
>
> The
We are generally moving to int64_t for both offset and bytes paramaters
on all io paths. Convert generic io path now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block.h | 8 ++--
include/block/block_int.h | 20 -
block/blkverify.c | 2 +-
block/io.c
We are generally moving to int64_t for both offset and bytes paramaters
on all io paths. Convert tracked requests now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block_int.h | 4 ++--
block/io.c| 11 ++-
2 files changed, 8 insertions(+), 7
Hi all!
There is an idea to make NBD protocol extension to support 64bit
write-zero/discard/block-status commands (commands, which doesn't
transfer user data). It's needed to increase performance of zeroing
large ranges (up to the whole image). Zeroing of the whole image is used
as first step of
We are generally moving to int64_t for both offset and bytes parameters
on all io paths. Convert driver handlers parameters which are already
64bit to signed type.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block_int.h | 28 ++--
block/backup-top.c
Philippe Mathieu-Daudé writes:
> On 3/25/20 7:19 AM, Dietmar Maurer wrote:
>> but error_setg() also calls malloc, so this does not help at all?
>
> IIUC the problem, you can send a QMP command to ask to read let's say
> 3GB of a file, and QEMU crashes. But this doesn't mean there the .heap
> is
On 3/30/2020 8:54 AM, Yan Zhao wrote:
On Fri, Mar 27, 2020 at 01:28:13PM +0800, Kirti Wankhede wrote:
Hit send button little early.
>
> I checked v12, it's not like what I said.
> In v12, bitmaps are generated per vfio_dma, and combination of the
> bitmaps are required in order to
On Mon, Mar 30, 2020 at 02:31:52PM +0100, Peter Maydell wrote:
> On Mon, 30 Mar 2020 at 14:26, Markus Armbruster wrote:
> >
> > Peter Maydell writes:
> >
> > > AIUI from Paolo, the intention is to deprecate and eventually
> > > stop supporting "in-tree" builds, so that the only option is
> > >
From: Changbin Du
The arm_current_el() should be invoked after mode switching. Otherwise, we
get a wrong current EL value, since current EL is also determined by
current mode.
Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry")
Signed-off-by: Changbin Du
Reviewed-by:
In some places in xlnx_zynqmp_realize() we were putting an
error into our local Error*, but forgetting to check for
failure and pass it back to the caller. Add the missing code.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
In xlnx_zynqmp_realize() if the attempt to realize the SD
controller object fails then the error-return path will leak
the 'bus_name' string. Fix this by deferring the allocation
until after the realize has succeeded.
Fixes: Coverity CID 1421911
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E.
Raise ConfigError rather than VersionRequirementError when we detect
that the Python being used by Sphinx is too old.
Currently the way we flag the Python version problem up to the user
causes Sphinx to print an unnecessary Python stack trace as well as
the information about the problem; in most
From: Niek Linnenbank
The allwinner_h3_dramc_map_rows function simulates row addressing behavior
when bootloader software attempts to detect the amount of available SDRAM.
Currently the line that calculates the 64-bit address of the mirrored row
uses a signed 32-bit multiply operation that in
From: Niek Linnenbank
The Orange Pi PC initialization function needs to verify that the SD card
block backend is usable before calling the Boot ROM setup routine. When
calling blk_is_available() the input parameter should not be NULL.
This commit ensures that blk_is_available is only called with
repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20200330
for you to fetch changes up to 88828bf133b64b7a860c166af3423ef1a47c5d3b:
target/arm: fix incorrect current EL bug in aarch32 exception emulation
(2020-03-30 13:55:32 +0100
On Mon, 30 Mar 2020 at 14:26, Markus Armbruster wrote:
>
> Peter Maydell writes:
>
> > AIUI from Paolo, the intention is to deprecate and eventually
> > stop supporting "in-tree" builds, so that the only option is
> > building in a separate build directory. I thought we should
> > probably
On Mon, 30 Mar 2020 at 14:17, BALATON Zoltan wrote:
>
> On Mon, 30 Mar 2020, Peter Maydell wrote:
> > In dcr_write_pcie() we take the iothread lock around a call to
> > pcie_host_mmcfg_udpate(). This is an incorrect attempt to deal with
> > the bug fixed in commit 235352ee6e73d7716, where we
Peter Maydell writes:
> AIUI from Paolo, the intention is to deprecate and eventually
> stop supporting "in-tree" builds, so that the only option is
> building in a separate build directory. I thought we should
> probably mention that in the 5.0 changelog, so I wrote up some
> text:
>
>
On 2020/3/30 20:38, Auger Eric wrote:
Hi Zenghui,
[...]
+
+ ptr = gicv3_data.redist_base[pe0] + GICR_PENDBASER;
+ pendbaser = readq(ptr);
+ writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr);
+
+ ptr = gicv3_data.redist_base[pe1] + GICR_PENDBASER;
+ pendbaser = readq(ptr);
+
On Mon, 30 Mar 2020, Peter Maydell wrote:
In dcr_write_pcie() we take the iothread lock around a call to
pcie_host_mmcfg_udpate(). This is an incorrect attempt to deal with
the bug fixed in commit 235352ee6e73d7716, where we were not taking
the iothread lock before calling device dcr read/write
30.03.2020 12:54, Denis Plotnikov wrote:
zstd significantly reduces cluster compression time.
It provides better compression performance maintaining
the same level of the compression ratio in comparison with
zlib, which, at the moment, is the only compression
method available.
The performance
Peter Maydell writes:
> On Fri, 20 Mar 2020 at 09:18, Markus Armbruster wrote:
>>
>> Our current QAPI doc-comment markup allows section headers (introduced
>> with a leading '=' or '==') anywhere in a free-form documentation
>> comment. This works for Texinfo because the generator simply
On 27/03/20 16:04, Peter Xu wrote:
> That makes perfect sense to me, however... What if the vcpu generates
> dirty bits _after_ we do KVM_GET_DIRTY_LOG but _before_ we send
> KVM_SET_USER_MEMORY_REGION to remove the memslot? If the vcpu is in
> the userspace I think it's fine because BQL is
On Sat, 28 Mar 2020 at 14:02, Changbin Du wrote:
>
> The arm_current_el() should be invoked after mode switching. Otherwise, we
> get a wrong current EL value, since current EL is also determined by
> current mode.
>
> Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry")
>
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