Re: [PATCH v2] lockable: Replace locks with lock guard macros

Hi Julia, On 4/19/20 5:46 AM, Julia Suvorova wrote: On Sat, Apr 18, 2020 at 2:03 PM Marcel Apfelbaum wrote: Hi Simran, On 4/2/20 9:50 AM, Simran Singhal wrote: Replace manual lock()/unlock() calls with lock guard macros (QEMU_LOCK_GUARD/WITH_QEMU_LOCK_GUARD). Signed-off-by: Simran Singhal

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

> On Apr 18, 2020, at 6:18 PM, Marcel Apfelbaum > wrote: > > Hi Ani, > > On 4/18/20 6:25 AM, Ani Sinha wrote: >> +Julia who implemented >> https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.kernel.org_patch_1131_&d=DwICaQ&c=s883GpUCOChKOHiocYtGcg&r=IIUxIyRwG4RGy57y2nvMNYcDkqW

Re: [PATCH v2] lockable: Replace locks with lock guard macros

On Sat, Apr 18, 2020 at 2:03 PM Marcel Apfelbaum wrote: > > Hi Simran, > > On 4/2/20 9:50 AM, Simran Singhal wrote: > > Replace manual lock()/unlock() calls with lock guard macros > > (QEMU_LOCK_GUARD/WITH_QEMU_LOCK_GUARD). > > > > Signed-off-by: Simran Singhal > > --- > > Changes in v2: > >

Re: [PATCH v4 1/2] target/arm: kvm: Handle DABT with no valid ISS

On Fri, 17 Apr 2020 at 14:10, Andrew Jones wrote: > > On Fri, Apr 17, 2020 at 11:39:25AM +0100, Peter Maydell wrote: > > On Mon, 23 Mar 2020 at 11:32, Beata Michalska > > wrote: > > > > > > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort > > > exception with no valid ISS

Re: [PATCH v2 4/6] dwc-hsotg USB host controller emulation

Hi Peter, On 4/16/20 8:45 AM, Peter Maydell wrote: On Sun, 29 Mar 2020 at 00:18, Paul Zimmerman wrote: < snip > +/* nifty macros from Arnon's EHCI version */ +#define get_field(data, field) \ +(((data) & field##_MASK) >> field##_SHIFT) + +#define set_field(data, newval, field) do { \ +

Re: [PATCH] target/arm: Vectorize integer comparison vs zero

Patchew URL: https://patchew.org/QEMU/20200418162808.4680-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH] target/arm: Vectorize integer comparison vs zero Message-id: 20200418162808.4680-1-richar

[PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS

When vs interrupts (2, 6, 10) are enabled, pending and not delegated in hideleg, they are not always forwarded to hs mode after a return to vs mode. This happens independently of the state of spie and sie on the hs-level sstatus before the return. Instead, the vs-level status sie state seems to be

[PATCH] target/arm: Vectorize integer comparison vs zero

These instructions are often used in glibc's string routines. They were the final uses of the 32-bit at a time neon helpers. Signed-off-by: Richard Henderson --- target/arm/helper.h| 27 ++-- target/arm/translate.h | 5 + target/arm/neon_helper.c | 24 target/arm/translate

[PATCH 15/16] tcg/i386: Use tcg_constant_vec with tcg vec expanders

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 9cb627d6eb..deace219d2 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/

[PATCH 16/16] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec

These interfaces have been replaced by tcg_gen_dupi_vec and tcg_constant_vec. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 tcg/tcg-op-vec.c | 20 2 files changed, 24 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 11ed

[PATCH 14/16] tcg: Add tcg_reg_alloc_dup2

There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 88 +++ 1 file changed, 88 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index fc1c97d586..d712d19842 1

[PATCH] tcg: Add load_dest parameter to GVecGen2

We have this same parameter for GVecGen2i, GVecGen3, and GVecGen3i. This will make some SVE2 insns easier to parameterize. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-gvec.c | 45 --- 2 files changed, 34 insertio

[PATCH 11/16] tcg: Remove movi and dupi opcodes

These are now completely covered by mov from a TYPE_CONST temporary. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 --- tcg/aarch64/tcg-target.inc.c | 3 --- tcg/arm/tcg-target.inc.c | 1 - tcg/i386/tcg-target.inc.c| 3 --- tcg/mips/tcg-target.inc.c| 2 --

[PATCH 07/16] tcg: Rename struct tcg_temp_info to TempOptInfo

Fix this name vs our coding style. Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index effb47eefd..b86bf3d707 100644 --- a/tcg/optimize.c +++ b/tcg/optimiz

[PATCH 13/16] tcg: Increase tcg_out_dupi_vec immediate to int64_t

While we don't store more than tcg_target_long in TCGTemp, we shouldn't be limited to that for code generation. We will be able to use this for INDEX_op_dup2_vec with 2 constants. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 2 +- tcg/i386/tcg-target.inc.c| 20 ++

[PATCH 04/16] tcg: Use tcg_constant_{i32,i64} with tcg int expanders

Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 13 +-- tcg/tcg-op.c | 216 --- 2 files changed, 100 insertions(+), 129 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 230db6e022..11ed9192f7 100644 --- a/inc

[PATCH 12/16] tcg: Use tcg_out_dupi_vec from temp_load

Having dupi pass though movi is confusing and arguably wrong. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 7 tcg/i386/tcg-target.inc.c| 63 tcg/ppc/tcg-target.inc.c | 6 tcg/tcg.c| 8 - 4 fi

[PATCH 09/16] tcg/optimize: Use tcg_constant_internal with constant folding

Signed-off-by: Richard Henderson --- tcg/optimize.c | 106 ++--- 1 file changed, 48 insertions(+), 58 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index d36d7e1d7f..dd5187be31 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -178,37 +17

[PATCH 05/16] tcg: Use tcg_constant_{i32,vec} with tcg vec expanders

Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 63 ++-- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index f3927089a7..655b3ae32d 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -23

[PATCH 10/16] tcg/tci: Add special tci_movi_{i32,i64} opcodes

The normal movi opcodes are going away. We need something for TCI to use internally. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 8 tcg/tci.c| 4 ++-- tcg/tci/tcg-target.inc.c | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/

[PATCH 08/16] tcg/optimize: Adjust TempOptInfo allocation

Do not allocate a large block for indexing. Instead, allocate for each temporary as they are seen. In general, this will use less memory, if we consider that most TBs do not touch every target register. This also allows us to allocate TempOptInfo for new temps created during optimization. Signe

[PATCH 02/16] tcg: Introduce TYPE_CONST temporaries

These will hold a single constant for the duration of the TB. They are hashed, so that each value has one temp across the TB. Not used yet, this is all infrastructure. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 27 ++- tcg/optimize.c| 40 ++--- tcg/tcg-op

[PATCH 03/16] tcg: Use tcg_constant_i32 with icount expander

We must do this before we adjust how tcg_out_movi_i32, lest the under-the-hood poking that we do be broken. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/include/exec/gen-icount.h b/i

[PATCH 00/16] tcg: Better handling of constants

This promotes constants to full-fledged temporaries, which are then hashed so we have only a single copy across the TB. If an opcode requires forcing one into a register, then we will only do this once -- at least until the register is killed, e.g. by a function call. While this is probably an mo

[PATCH 06/16] tcg: Use tcg_constant_{i32,i64} with tcg plugins

Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 49 +++--- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 51580d51a0..e5dc9d0ca9 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel

[PATCH 01/16] tcg: Add temp_readonly

In most, but not all, places that we check for TEMP_FIXED, we are really testing that we do not modify the temporary. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 5 + tcg/tcg.c | 21 ++--- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/

[PATCH 3/3] target/arm: Use clear_vec_high more effectively

Do not explicitly store zero to the NEON high part when we can pass !is_q to clear_vec_high. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 59 +++--- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/t

[PATCH 2/3] target/arm: Use tcg_gen_gvec_mov for clear_vec_high

The 8-byte store for the end a !is_q operation can be merged with the other stores. Use a no-op vector move to trigger the expand_clr portion of tcg_gen_gvec_mov. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) di

[PATCH 1/3] tcg: Improve vector tail clearing

Better handling of non-power-of-2 tails as seen with Arm 8-byte vector operations. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 82 --- 1 file changed, 63 insertions(+), 19 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c in

[PATCH 0/3] tcg: Improve vector tail clearing

Something I noticed while looking at AdvSIMD dumps, while testing changes common with SVE2. If we're going to load a zero into a vector register for clearing the high bits of the SVE register, we might as well use that zero to store the 8 bytes at the top of the AdvSIMD register as well. Output a

[PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl

For use when a target needs to pass a configure-specific target_ulong value to duplicate. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index fa8a0c8d03..d89f91f40e 10

[PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications

Replace the outgoing interface. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 593bb4542e..de16c027b3 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2326,7

[PATCH 3/7] target/ppc: Use tcg_gen_gvec_dup_imm

We can now unify the implementation of the 3 VSPLTI instructions. Signed-off-by: Richard Henderson --- target/ppc/translate/vmx-impl.inc.c | 32 - target/ppc/translate/vsx-impl.inc.c | 2 +- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/target/ppc/

[PATCH 4/7] target/arm: Use tcg_gen_gvec_dup_imm

In a few cases, we're able to remove some manual replication. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 10 +- target/arm/translate-sve.c | 12 +--- target/arm/translate.c | 9 ++--- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a

[PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm

Add a version of tcg_gen_dup_* that takes both immediate and a vector element size operand. This will replace the set of tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element size within the function name. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-

[PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i

These interfaces are now unused. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 5 - tcg/tcg-op-gvec.c | 28 2 files changed, 33 deletions(-) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index eb0d47a42b..fa8a0c8d

[PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm

The gen_gvec_dupi switch is unnecessarily with the new function. Replace it with a local gen_gvec_dup_imm that takes care of the register to offset conversion and length arguments. Drop zero_vec and use use gen_gvec_dup_imm with 0. Signed-off-by: Richard Henderson --- target/s390x/translate_vx.

[PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface

Replace 4 separate routines with a single routine taking a vece parameter. This avoids several targets needing to create this interface internally. I noticed this in particular reviewing the riscv code; I'm not sure why it took three targets to notice. ;-) r~ Richard Henderson (7): tcg: Ad

[Bug 1871798] Re: Fails to start on Windows host without explicit --disable-pie

Fixed in commit 469a788cdd3c618ef1b8a23a339510082b3eeea7. ** Changed in: qemu Status: Incomplete => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1871798 Title: Fails to start

[Bug 1869497] Re: x86_cpu_gdb_read_register segfaults when gdb requests registers

Fixed in commit bbc40fefcee0d69d61ceaf8c0695d2ce43cdc87b. ** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1869497 Title: x86_cpu_gdb_read_regi

Re: [PATCH] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

Hi Ani, On 4/18/20 6:25 AM, Ani Sinha wrote: +Julia who implemented https://patchwork.kernel.org/patch/1131/ On Apr 18, 2020, at 3:26 AM, Laine Stump wrote: On 4/17/20 12:35 PM, Ani Sinha wrote: +Laine On Apr 17, 2020, at 9:39 PM, Michael S. Tsirkin wrote: Problem is, I think this i

Re: [PATCH v2] lockable: Replace locks with lock guard macros

Hi Simran, On 4/2/20 9:50 AM, Simran Singhal wrote: Replace manual lock()/unlock() calls with lock guard macros (QEMU_LOCK_GUARD/WITH_QEMU_LOCK_GUARD). Signed-off-by: Simran Singhal --- Changes in v2: -Drop changes in file hw/rdma/rdma_utils.c hw/hyperv/hyperv.c | 15 ++

Re: [PATCH-for-5.0?] target/ppc: Fix TCG temporary leaks in gen_slbia()

Excerpts from Philippe Mathieu-Daudé's message of April 17, 2020 9:00 pm: > On 4/17/20 12:51 PM, Nicholas Piggin wrote: >> Excerpts from Philippe Mathieu-Daudé's message of April 17, 2020 7:07 pm: >>> This fixes: >>> >>> $ qemu-system-ppc64 \ >>> -machine pseries-4.1 -cpu power9 \ >>> -smp 4

Re: [PATCH] resend slave fd to vhost when reconnect to vhost

oh, yes, there is some mis-config here, thanks for pointing that out. looks like the upstream has fixed it. Thanks, Xun Raphael Norwitz 于2020年4月18日周六 上午9:46写道： > > On Fri, Apr 17, 2020 at 01:14:00PM +0800, ni.xun.in...@gmail.com wrote: > > > > From: Ni Xun > > > > when reconnecting to vhost se

Re: [PATCH resend v2] net: cadence_gem: clear RX control descriptor

On Sat, Apr 18, 2020 at 11:51:45AM +0300, Ramon Fried wrote: > The RX ring descriptors control field is used for setting > SOF and EOF (start of frame and end of frame). > The SOF and EOF weren't cleared from the previous descriptors, > causing inconsistencies in ring buffer. > Fix that by clearing

[Bug 1872113] Re: qemu docs fails to build with Sphinx 3.0.x

The upstream fix for this is now in 5.0-rc3 and will be in the final 5.0 release. ** Changed in: qemu Status: In Progress => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1872113

[Bug 1872847] Re: qemu-alpha linux-user breaks python3.6

** Changed in: gentoo Status: Fix Committed => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1872847 Title: qemu-alpha linux-user breaks python3.6 Status in QEMU: New Status

[PATCH resend v2] net: cadence_gem: clear RX control descriptor

The RX ring descriptors control field is used for setting SOF and EOF (start of frame and end of frame). The SOF and EOF weren't cleared from the previous descriptors, causing inconsistencies in ring buffer. Fix that by clearing the control field of every descriptors we're processing. Signed-off-b

[Bug 1872847] Re: qemu-alpha linux-user breaks python3.6

** Changed in: gentoo Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1872847 Title: qemu-alpha linux-user breaks python3.6 Status in QEMU: New Status in Gentoo