Currently, the option use_acpi_pci_hotplug is being used to control device
hotplug capability using ACPI for slots of cold plugged bridges. Hence, we
are renaming this option to better reflect what it actually does.
Change-Id: I2a6ab47e80fa2bc9504ce88e063d710efaceb842
Signed-off-by: Ani Sinha
Hello Bastian,
Thanks for your feedback, I like your proposals.
> Also what do the _U and _C suffixes mean? I could not find them in the user
> manual [1].
See TC27X UM chapter 3.2 "Contents of the Segments"
"CPUx default attributes for these segments: non-cached" vs "cached"
These regions are
Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
"-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vector register length, default value is 128 bit.
elen is the max operator size in bits, default
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 26
On Wed, 10 Jun 2020 12:24:14 +0200
David Hildenbrand wrote:
> On 10.06.20 12:07, David Gibson wrote:
> > On Wed, Jun 10, 2020 at 09:22:45AM +0200, David Hildenbrand wrote:
> >> On 10.06.20 06:31, David Gibson wrote:
> >>> On Tue, Jun 09, 2020 at 12:44:39PM -0400, Michael S. Tsirkin wrote:
>
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 116
2 files changed, 117 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index
On 6/10/20 3:57 AM, Vladimir Sementsov-Ogievskiy wrote:
08.06.2020 21:26, Eric Blake wrote:
Ever since commit 36683283 (v2.8), the server code asserts that error
strings sent to the client are well-formed per the protocol by not
exceeding the maximum string length of 4096. At the time the
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 49 +
2 files changed, 51 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 25 +
target/riscv/vector_helper.c| 24
On 09/06/2020 10.39, Wu, Wentong wrote:
> Hi @Thomas Huth,
> It's my first time to send patch in qemu community, not sure if there is
> something wrong sending patch like below and I'm happy to receive any
> suggestions. And by the way, could you please help review the patch?
Hi,
it would be
Previously, the option use_acpi_pci_hotplug was being used to control device
hotplug capability using ACPI for slots of cold plugged bridges. Hence, we
are renaming this option to better reflect what it actually does.
Change-Id: I2a6ab47e80fa2bc9504ce88e063d710efaceb842
Signed-off-by: Ani Sinha
On Wed, 10 Jun 2020 10:48:42 +0200
Cornelia Huck wrote:
> On Wed, 10 Jun 2020 14:39:22 +1000
> David Gibson wrote:
>
> > On Tue, Jun 09, 2020 at 12:16:41PM +0200, Cornelia Huck wrote:
> > > On Sun, 7 Jun 2020 13:07:35 +1000
> > > David Gibson wrote:
> > >
> > > > On Sat, Jun 06, 2020 at
10.06.2020 15:19, Sam Eiderman wrote:
Thanks David,
Yes, I imaging the following use case:
disk.vmdk is a 50 GB disk that contains 12 MB binary of zeroes in its beginning.
/dev/sda is a raw disk containing garbage
I invoke:
qemu-img convert disk.vmdk -O raw /dev/sda
Required output:
The
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 27 +++
target/riscv/vector_helper.c| 29
On Tue, 9 Jun 2020 18:05:59 +0200
Cornelia Huck wrote:
> Which devices are compatible in the end? It seems the only ones that
> are known to be working are virtio-ccw devices with IOMMU_PLATFORM on.
> virtio-pci devices and non-virtio ccw (vfio-ccw, 3270) seem to be out,
> as far as I understand
On 6/10/20 12:24 PM, David Hildenbrand wrote:
On 10.06.20 12:07, David Gibson wrote:
On Wed, Jun 10, 2020 at 09:22:45AM +0200, David Hildenbrand wrote:
On 10.06.20 06:31, David Gibson wrote:
On Tue, Jun 09, 2020 at 12:44:39PM -0400, Michael S. Tsirkin wrote:
On Tue, Jun 09, 2020 at
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 3 +
target/riscv/insn_trans/trans_rvv.inc.c | 78 +
target/riscv/vector_helper.c| 60 +++
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 28 +++
target/riscv/vector_helper.c| 63 +
4
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18
target/riscv/vector_helper.c| 114
4 files
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 20
4
To simplify internal implementation the hmat-cache parsing code
expects hmat-lb to be already parsed. This means, that hmat-lb
arguments must come before hmat-cache. Document this restriction
so that management applications can follow it.
Signed-off-by: Michal Privoznik
---
qemu-options.hx | 3
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 19 +++
4
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 60 +
target/riscv/internals.h| 6 +++
3 files changed, 67 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvv.inc.c | 35 ++
target/riscv/vector_helper.c| 40
The documentation to `-numa hmat-cache` says that @node-id, @size
and @level are the only required attributes. The rest
(@associativity, @policy and @line) is optional. Well, not quite
- if I try to start QEMU with only the three required attributes
defined the QAPI code is complaining about
On Tue, 9 Jun 2020 12:44:39 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Jun 09, 2020 at 06:28:39PM +0200, Halil Pasic wrote:
> > On Tue, 9 Jun 2020 17:47:47 +0200
> > Claudio Imbrenda wrote:
> >
> > > On Tue, 9 Jun 2020 11:41:30 +0200
> > > Halil Pasic wrote:
> > >
> > > [...]
> > >
> > > >
Le 10/06/2020 à 09:50, Thomas Huth a écrit :
> On 10/06/2020 09.31, Philippe Mathieu-Daudé wrote:
>> On 6/10/20 5:51 AM, Thomas Huth wrote:
>>> The #ifdef CONFIG_VFIO_IGD in pci-quirks.c is not working since the
>>> required header config-devices.h is not included, so that the legacy
>>> IGD
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c| 46
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 7 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 11
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 10 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 5
target/riscv/vector_helper.c| 39
From: KONRAD Frederic
This have been introduced by:
8de702cb677c8381fb702cae252d6b69aa4c653b
It doesn't seem to be used so remove it.
Signed-off-by: KONRAD Frederic
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alex Bennée
Message-Id:
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200601142930.29408-9-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
target/i386/cpu.c
From: Philippe Mathieu-Daudé
When compiling with GCC 10 (Fedora 32) using CFLAGS=-O2 we get:
CC or1k-softmmu/hw/openrisc/openrisc_sim.o
hw/openrisc/openrisc_sim.c: In function ‘openrisc_sim_init’:
hw/openrisc/openrisc_sim.c:87:42: error: ‘cpu_irqs[0]’ may be used
uninitialized in
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Paul Durrant
Reviewed-by: Richard Henderson
Message-Id: <20200601142930.29408-8-f4...@amsat.org>
Signed-off-by: Laurent
On 6/9/20 8:17 PM, Eric Blake wrote:
The following changes since commit 31d321c2b3574dcc74e9f6411af06bca6b5d10f4:
Merge remote-tracking branch
'remotes/philmd-gitlab/tags/sparc-next-20200609' into staging (2020-06-09
17:29:47 +0100)
are available in the Git repository at:
From: Eric Blake
Prefer a consistent naming for the --merge argument.
Fixes: 3b51ab4bf
Signed-off-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20200529144527.1943527-1-ebl...@redhat.com>
Signed-off-by: Laurent Vivier
---
docs/tools/qemu-img.rst | 2 +-
1 file
From: Philippe Mathieu-Daudé
Replace disabled DPRINTF() by qemu_log_mask(GUEST_ERROR).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200603123754.19059-3-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
target/unicore32/helper.c | 11 +++
1
Technically, this is a v2 of:
https://lists.nongnu.org/archive/html/qemu-devel/2020-05/msg08316.html
But as it turned out during the review of v1, we don't need to change
the code rather than documentation.
Michal Privoznik (2):
qemu-options.hx: Mark all hmat-cache attributes required
From: Philippe Mathieu-Daudé
Replace a deprecated DPRINTF() call by qemu_log_mask(LOG_UNIMP).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Message-Id: <20200606070216.30952-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
From: Raphael Norwitz
The ‘enable’ parameter to the vhost_migration_log() function is given as
an int, but "true"/"false" values are passed in wherever it is invoked.
Inside the function itself it is only ever compared with bool values.
Therefore the parameter value itself should be changed to
From: Philippe Mathieu-Daudé
Replace some debug printf() calls by qemu_log_mask(LOG_GUEST_ERROR).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20200524164503.11944-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/dma/puv3_dma.c | 9 +++--
From: Philippe Mathieu-Daudé
Use the common API for semihosting logging.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200603123754.19059-4-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
default-configs/unicore32-softmmu.mak | 1 +
From: Philippe Mathieu-Daudé
memory_region_set_size() handle the 16 Exabytes limit by
special-casing the UINT64_MAX value. This is not a problem
for the 32-bit maximum, 4 GiB.
By using the UINT32_MAX value, the aspeed-ram-container
MemoryRegion ends up missing 1 byte:
$ qemu-system-arm -M
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200601142930.29408-7-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/hppa/dino.c | 4
From: Philippe Mathieu-Daudé
Update Fred Konrad email address to avoid emails bouncing.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: KONRAD Frederic
Message-Id: <20200518103920.10699-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
From: Philippe Mathieu-Daudé
Convert APM_DPRINTF() to trace events and remove ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200524164806.12658-1-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/isa/apm.c| 15 +--
From: Thomas Huth
The '\n' sneaked in by accident here, an "id" string should really
not contain a newline character at the end.
Fixes: 78cd6f7bf6b ('net: Add a new convenience option "--nic" ...')
Signed-off-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200603123754.19059-2-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
target/unicore32/helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/unicore32/helper.c
-branch-for-5.1-pull-request
for you to fetch changes up to fe18e6eecdd45d3dff0c8968cbb07c5e02fbe4c8:
semihosting: remove the pthread include which seems unused (2020-06-10 11:2=
9:44 +0200)
Trivial branch pull request 20200610
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c|
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 48 +
target/riscv/vector_helper.c
On 6/10/20 7:54 AM, David Hildenbrand wrote:
VFIO is (except devices without a physical IOMMU or some mediated devices)
incompatible with discarding of RAM. The kernel will pin basically all VM
memory. Let's convert to ram_block_discard_disable(), which can now
fail, in contrast to
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 48 +
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 6 +
target/riscv/vector_helper.c| 33
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 38 +
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 33 +
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 +
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Richard Henderson
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvv.inc.c | 35 +
target/riscv/vector_helper.c| 174
libslirp fix included in commit 7769c23774d1, released in QEMU-v5.0.0
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1858415
Title:
in tcp_emu function has OOB bug
Status in QEMU:
Fix Released
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 19 ++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c| 85
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.inc.c | 6 ++
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 43 +
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 251
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 149
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 91
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 +
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 141
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 107
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 49
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 100
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c|
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 205
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 +
target/riscv/vector_helper.c| 385
** Information type changed from Private Security to Public
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1858415
Title:
in tcp_emu function has OOB bug
Status in QEMU:
Fix Released
Bug
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 118
target/riscv/vector_helper.c
Thanks David,
Yes, I imaging the following use case:
disk.vmdk is a 50 GB disk that contains 12 MB binary of zeroes in its beginning.
/dev/sda is a raw disk containing garbage
I invoke:
qemu-img convert disk.vmdk -O raw /dev/sda
Required output:
The first 12 MB of /dev/sda contain zeros, the
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 113
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51
сре, 10. јун 2020. у 14:06 Philippe Mathieu-Daudé је
написао/ла:
>
> On 6/10/20 1:08 PM, Aleksandar Markovic wrote:
> > пон, 8. јун 2020. у 11:05 Philippe Mathieu-Daudé је
> > написао/ла:
> >>
> >> Aurelien Jarno expressed his desire to orphan the SH4 hardware [*]:
> >>
> >> I don't mind being
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 117
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 +
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 163
On Tue, 9 Jun 2020 10:19:14 -0400
"Michael S. Tsirkin" wrote:
> On Fri, Jun 05, 2020 at 06:09:11PM -0600, Vishal Verma wrote:
> > Update expected SRAT files for the change to account for NVDIMM NUMA
> > nodes in the SRAT.
> >
> > AML diffs:
> >
> > tests/data/acpi/pc/SRAT.dimmpxm:
> > ---
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c|
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88
bdrv_is_allocated_above wrongly handles short backing files: it reports
after-EOF space as UNALLOCATED which is wrong, as on read the data is
generated on the level of short backing file (if all overlays has
unallocated area at that place).
Reusing bdrv_common_block_status_above fixes the issue
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 52
target/riscv/vector_helper.c
In order to reuse bdrv_common_block_status_above in
bdrv_is_allocated_above, let's support include_base parameter.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/coroutines.h | 2 ++
block/io.c | 14 ++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git
These cases are fixed by previous patches around block_status and
is_allocated.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
---
tests/qemu-iotests/274 | 20
tests/qemu-iotests/274.out | 65 ++
2 files changed, 85
v5: rebase on coroutine-wrappers series, 02 changed correspondingly
Based on series "[PATCH v7 0/7] coroutines: generate wrapper code", or
in other words:
Based-on: <20200610100336.23451-1-vsement...@virtuozzo.com>
Hi all!
These series are here to address the following problem:
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 11 ++
target/riscv/insn_trans/trans_rvv.inc.c | 113 +++
target/riscv/vector_helper.c
bdrv_co_block_status_above has several design problems with handling
short backing files:
1. With want_zeros=true, it may return ret with BDRV_BLOCK_ZERO but
without BDRV_BLOCK_ALLOCATED flag, when actually short backing file
which produces these after-EOF zeros is inside requested backing
We are going to reuse bdrv_common_block_status_above in
bdrv_is_allocated_above. bdrv_is_allocated_above may be called with
include_base == false and still bs == base (for ex. from img_rebase()).
So, support this corner case.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Kevin Wolf
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 46 +
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 90 +
target/riscv/vector_helper.c
On Wednesday, 2020-06-10 at 08:28:29 +03, Sam Eiderman wrote:
> Hi,
>
> 168468fe19c8 ("qemu-img: Add --target-is-zero to convert") has added a
> nice functionality for cloud scenarios:
>
> * Create a virtual disk
> * Convert a sparse image (qcow2, vmdk) to the virtual disk using
>
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 25 ++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 291
target/riscv/vector_helper.c
Let's auto-enable it also when maxmem is specified but no slots are
defined. This will result in us properly creating ACPI srat tables,
indicating the maximum possible PFN to the guest OS. Based on this, e.g.,
Linux will enable the swiotlb properly.
This avoids having to manually force the
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair
The content of unplugged memory is undefined and should not be migrated,
ever. Exclude all unplugged memory during precopy using the precopy notifier
infrastructure introduced for free page hinting in virtio-balloon.
Unplugged memory is marked as "not dirty", meaning it won't be
considered for
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