The last real change to this file is from 2012, so it is very likely
that this file is completely out-of-date and ignored today. Let's
simply remove it to avoid confusion if someone finds it by accident.
Signed-off-by: Thomas Huth
---
target/i386/TODO | 31 ---
1
On 6/11/20 8:16 PM, Denis V. Lunev wrote:
> Nowaday SCSI drivers in guests are able to align UNMAP requests before
> sending to the device. Right now QEMU provides an ability to set
> this via "discard_granularity" property of the block device which could
> be used by management layer.
>
> Though,
Richard Henderson writes:
> On 6/11/20 9:44 AM, Alex Bennée wrote:
>>
>> Richard Henderson writes:
>>
>>> On aarch64, gcc 9.3 is generating
>>>
>>> qemu/exec.c: In function ‘address_space_translate_iommu’:
>>> qemu/exec.c:431:28: note: parameter passing for argument of type \
>>>
Default discard granularity is set to -2 now.
Signed-off-by: Denis V. Lunev
CC: Kevin Wolf
CC: Max Reitz
CC: Eduardo Habkost
CC: Marcel Apfelbaum
CC: John Snow
CC: Paolo Bonzini
CC: Fam Zheng
---
tests/qemu-iotests/172.out | 106 ++---
1 file changed, 53
Nowaday SCSI drivers in guests are able to align UNMAP requests before
sending to the device. Right now QEMU provides an ability to set
this via "discard_granularity" property of the block device which could
be used by management layer.
Though, in particular, from the point of QEMU, there is
Nowaday SCSI drivers in guests are able to align UNMAP requests before
sending to the device. Right now QEMU provides an ability to set
this via "discard_granularity" property of the block device which could
be used by management layer.
Though, in particular, from the point of QEMU, there is
Right now bdrv_fclose() is just calling bdrv_flush().
The problem is that migration code is working inefficently from black
layer terms and are frequently called for very small pieces of not
properly aligned data. Block layer is capable to work this way, but
this is very slow.
This patch is a
This series do standard basic things:
- it creates intermediate buffer for all writes from QEMU migration code
to QCOW2 image,
- this buffer is sent to disk asynchronously, allowing several writes to
run in parallel.
In general, migration code is fantastically inefficent (by observation),
From: Vladimir Sementsov-Ogievskiy
Currently, aio task pool assumes that there is a main coroutine, which
creates tasks and wait for them. Let's remove the restriction by using
CoQueue. Code becomes clearer, interface more obvious.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by:
This patch does 2 standard basic things:
- it creates intermediate buffer for all writes from QEMU migration code
to block driver,
- this buffer is sent to disk asynchronously, allowing several writes to
run in parallel.
Thus bdrv_vmstate_write() is becoming asynchronous. All pending
qemu_fclose() could return error, f.e. if bdrv_co_flush() will return
the error.
This validation will become more important once we will start waiting of
asynchronous IO operations, started from bdrv_write_vmstate(), which are
coming soon.
Signed-off-by: Denis V. Lunev
CC: Kevin Wolf
CC: Max
Reviewed-by: Robert Foley
Tested-by: Robert Foley
The testing was mostly bringing up pairs of aarch64 VMs and
either waiting for the divergence or exiting out before divergence
with ctrl-a x at various stages of boot.
When we exit from the VM before divergence, we observe the below:
we seem to
On Thu, 11 Jun 2020 at 16:43, Richard Henderson
wrote:
>
> On 6/11/20 7:45 AM, Peter Maydell wrote:
> > In commit 37bfce81b10450071 we accidentally introduced a leak of a TCG
> > temporary in do_2shift_env_64(); free it.
> >
> > Signed-off-by: Peter Maydell
> > ---
> > My test setup wasn't
On Tue, 9 Jun 2020 at 21:53, Eric Blake wrote:
>
> The following changes since commit 31d321c2b3574dcc74e9f6411af06bca6b5d10f4:
>
> Merge remote-tracking branch
> 'remotes/philmd-gitlab/tags/sparc-next-20200609' into staging (2020-06-09
> 17:29:47 +0100)
>
> are available in the Git
Steve, could you describe your problem with more details?
What is the version of qemu you are using?
** Tags added: linux-user
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https://bugs.launchpad.net/bugs/1594394
Title:
Using
On 6/11/20 9:44 AM, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> On aarch64, gcc 9.3 is generating
>>
>> qemu/exec.c: In function ‘address_space_translate_iommu’:
>> qemu/exec.c:431:28: note: parameter passing for argument of type \
>> ‘MemTxAttrs’ {aka ‘struct MemTxAttrs’} changed
On systems where the IASL tool exists, we can convert
extected ACPI tables to ASL format, which is useful
for debugging and documentation purposes.
This script does this for all ACPI tables under tests/data/acpi/.
Signed-off-by: Michael S. Tsirkin
---
tests/data/acpi/disassemle-aml.sh | 52
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the Neon VDUP (scalar) insn to decodetree. (Note that we
> can't call this just "VDUP" as we used that already in vfp.decode for
> the "VDUP (general purpose register" insn.)
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/neon-dp.decode
On 6/11/20 7:45 AM, Peter Maydell wrote:
> +static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
> +{
> +int n;
> +TCGv_i32 tmp, tmp2, tmp3, tmp4;
> +TCGv_ptr ptr1;
> +
> +if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
> +return false;
> +}
> +
> +/* UNDEF accesses to
* Eric Blake (ebl...@redhat.com) wrote:
> On 6/11/20 6:17 AM, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > The monitors currently have a 'getfd' command that lets you pass an fd
> > via the monitor socket. 'openfd' is a new command that opens a file
> > and
Richard Henderson writes:
> On aarch64, gcc 9.3 is generating
>
> qemu/exec.c: In function ‘address_space_translate_iommu’:
> qemu/exec.c:431:28: note: parameter passing for argument of type \
> ‘MemTxAttrs’ {aka ‘struct MemTxAttrs’} changed in GCC 9.1
>
> and many other reptitions. This
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the Neon VTBL, VTBX instructions to decodetree. The actual
> implementation of the insn is copied across to the new trans function
> unchanged except for renaming 'tmp5' to 'tmp4'.
>
> Signed-off-by: Peter Maydell
> ---
>
When BDRV_REQ_NO_FALLBACK is supported, the NBD driver supports a
larger request size. Add code to try large zero requests with a
NO_FALLBACK request prior to having to split a request into chunks
according to max_pwrite_zeroes.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/io.c | 19
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the Neon VEXT insn to decodetree. Rather than keeping the
> old implementation which used fixed temporaries cpu_V0 and cpu_V1
> and did the extraction with by-hand shift and logic ops, we use
> the TCG extract2 insn.
>
> We don't need to special
Recent changes in NBD protocol allowed to use some commands without
max_block restriction. Let's drop the restrictions.
NBD change is here:
https://github.com/NetworkBlockDevice/nbd/commit/9f30fedb8699f151e7ef4ccc07e624330be3316b#diff-762fb7c670348da69cc9050ef58fe3ae
v4: fix auto_no_fallback
The NBD spec was recently updated to clarify that max_block doesn't
relate to NBD_CMD_WRITE_ZEROES with NBD_CMD_FLAG_FAST_ZERO (which
mirrors Qemu flag BDRV_REQ_NO_FALLBACK). To drop the restriction we
need new max_pwrite_zeroes_fast.
Default value of new max_pwrite_zeroes_fast is zero and it
It's wrong to update head using num in this place, as num may be
reduced during the iteration (seems it doesn't, but it's not obvious),
and we'll have wrong head value on next iteration.
Instead update head at iteration end.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Expose the RIL bit so that the guest driver uses range
invalidation.
Signed-off-by: Eric Auger
---
hw/arm/smmuv3-internal.h | 1 +
hw/arm/smmuv3.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 5babf72f7d..4e7ec252ed
The NBD spec was recently updated to clarify that max_block doesn't
relate to NBD_CMD_WRITE_ZEROES with NBD_CMD_FLAG_FAST_ZERO (which
mirrors Qemu flag BDRV_REQ_NO_FALLBACK).
bs->bl.max_write_zero_fast is zero by default which means using
max_pwrite_zeroes. Update nbd driver to allow larger
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the Neon 2-reg-scalar long multiplies to decodetree.
> These are the last instructions in the group.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/neon-dp.decode | 18
> target/arm/translate-neon.inc.c | 163
On 6/11/20 12:02 PM, Philippe Mathieu-Daudé wrote:
The TPMDEV describe TPM backends. Use the TPM_BACKEND config
name which is self-explicit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Berger
---
hw/tpm/Kconfig | 12 ++--
1 file changed, 6 insertions(+), 6
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the VQDMULH and VQRDMULH insns in the 2-reg-scalar group
> to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/neon-dp.decode | 3 +++
> target/arm/translate-neon.inc.c | 29 +++
>
On 6/11/20 12:02 PM, Philippe Mathieu-Daudé wrote:
Hi,
Yesterday I started to review some vTPM patches and got very
confused by the files under hw/tpm/. In particular after
running:
$ git grep TYPE_TPM_BACKEND
backends/tpm.c:188:.name = TYPE_TPM_BACKEND,
hw/tpm/tpm_emulator.c:985:
At the moment each entry in the IOTLB corresponds to a page sized
mapping (4K, 16K or 64K), even if the page belongs to a mapped
block. In case of block mapping this unefficiently consume IOTLB
entries.
Change the value of the entry so that it reflects the actual
mapping it belongs to (block or
On 6/11/20 12:02 PM, Philippe Mathieu-Daudé wrote:
As we will have various TPM backend files, it is cleaner
to use a single directory.
Suggested-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Berger
---
backends/{tpm.c => tpm/tpm_backend.c} | 0
Peter Maydell writes:
> On Thu, 11 Jun 2020 at 15:45, Alex Bennée wrote:
>>
>> Pretty much all calls to qemu_log are either wrapped in some other
>> enabling check or only enabled with debug defines. Add a specific flag
>> for TCG warnings and expand the documentation of the qemu_log
>>
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the VQRDMLAH and VQRDMLSH insns in the 2-reg-scalar
> group to decodetree.
...
> +static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
> +NeonGenThreeOpEnvFn *opfn)
> +{
> +/*
> + * VQRDMLAH/VQRDMLSH:
On 6/11/20 12:02 PM, Philippe Mathieu-Daudé wrote:
Commit 8dc6701722 introduce the documentation but an
incorrect path name was used. Fix that.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Berger
---
docs/specs/tpm.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
SMMU3.2 brings the support of range-based TLB invalidation and
level hint. When this feature is supported, the SMMUv3 driver
is allowed to send TLB invalidations for a range of IOVAs instead
of using page based invalidation.
Implementing this feature in the virtual SMMUv3 device is
mandated for
Patchew URL:
https://patchew.org/QEMU/1591880064-30638-1-git-send-email-yi.l@intel.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST
Enhance the smmu_iotlb_inv_iova() helper with range invalidation.
This uses the new fields passed in the NH_VA and NH_VAA commands:
the size of the range, the level and the granule.
As NH_VA and NH_VAA both use those fields, their decoding and
handling is factorized in a new
Compute the starting level on CD decoding and store it
into SMMUTransTableInfo. We will need this information
on IOTLB lookup so let's avoid to recompute it each time.
Signed-off-by: Eric Auger
---
include/hw/arm/smmu-common.h | 1 +
hw/arm/smmu-common.c | 2 +-
hw/arm/smmuv3.c
Instead of using a Jenkins hash function to generate
the key let's just use a 64 bit unsigned integer that
contains the asid and the 40 upper bits of the iova.
A maximum of 52-bit IOVA is supported. This change in the
key format also prepares for the addition of new fields
in subsequent patches
Let's introduce an helper for S1 IOVA range invalidation.
This will be used for NH_VA and NH_VAA commands. It decodes
the same fields, trace, calls the UNMAP notifiers and
invalidate the corresponding IOTLB entries.
At the moment, we do not support 3.2 range invalidation yet.
So it reduces to a
Add two helpers to lookup for a given IOTLB entry and
an one. We also more the tracing there.
Signed-off-by: Eric Auger
---
include/hw/arm/smmu-common.h | 2 ++
hw/arm/smmu-common.c | 36
hw/arm/smmuv3.c | 26 ++
Hi Stefan,
On 6/11/20 5:19 PM, Stefan Berger wrote:
> On 6/11/20 9:59 AM, Eric Auger wrote:
>> In preparation of its move to the generic acpi code,
>> let's convert build_tpm2() to use build_append API. This
>> latter now is prefered in place of direct ACPI struct field
>> settings with manual
Introduce a specialized SMMUTLBEntry to store the result of
the PTW and cache in the IOTLB. This structure extends the
generic IOMMUTLBEntry struct with the level of the entry and
the granule size.
Those latter will be useful when implementing range invalidation.
Signed-off-by: Eric Auger
---
Page and block PTE decoding can share some code. Let's
first handle table PTE and factorize some code shared by
page and block PTEs.
Signed-off-by: Eric Auger
---
hw/arm/smmu-common.c | 51
1 file changed, 18 insertions(+), 33 deletions(-)
diff
>From CODING_STYLE.rst:
Do not include "qemu/osdep.h" from header files since the .c
file will have already included it.
Remove "qemu/osdep.h" from "tpm_tis.h".
Reviewed-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_tis.h | 1 -
1 file changed, 1 deletion(-)
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the float versions of VMLA, VMLS and VMUL in the Neon
> 2-reg-scalar group to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> As noted in the comment on the WRAP_FP_FN macro, we could have
> had a do_2scalar_fp() function, but for 3 insns
On Wed, Jun 10, 2020 at 6:09 PM Bin Meng wrote:
>
> From: Bin Meng
>
> There is no need to have two functions that have exactly the same
> codes for 32-bit and 64-bit base CPUs.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair Francis
Applied to riscv-to-apply branch.
Alistair
> ---
>
>
The TPMDEV describe TPM backends. Use the TPM_BACKEND config
name which is self-explicit.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/tpm/Kconfig | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/tpm/Kconfig b/hw/tpm/Kconfig
index 4794e7fe28..5028fd8880 100644
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Convert the VMLA, VMLS and VMUL insns in the Neon "2 registers and a
> scalar" group to decodetree. These are 32x32->32 operations where
> one of the inputs is the scalar, followed by a possible accumulate
> operation of the 32-bit result.
>
> The
Remove unnecessary 'tpm_int.h' header inclusion.
Reviewed-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_crb.c| 1 -
hw/tpm/tpm_spapr.c | 1 -
hw/tpm/tpm_tis_common.c | 1 -
3 files changed, 3 deletions(-)
diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c
From: Filip Bozuta
This series covers strace support for printing arguments of following syscalls:
*acct() *lgetxattr() *removexattr() *lchown()
*fsync() *fgetxattr() *lremovexattr() *fallocate()
*fdatasync() *listxattr()
From: Filip Bozuta
This patch implements strace argument printing functionality for following
syscalls:
*acct - switch process accounting on or off
int acct(const char *filename)
man page: https://www.man7.org/linux/man-pages/man2/acct.2.html
*fsync, fdatasync -
We are going to make "tpm_util.h" publicly accessible by
moving it to the include/ directory in the next commit.
The DEFINE_PROP_TPMBE() macro is only meaningful for the
TPM hardware files (in hw/tpm/), so keep this macro in a
local header.
Reviewed-by: Stefan Berger
Signed-off-by: Philippe
We are going to split the TPM backends from the TPM emulated
hardware in the next commit. Make the TPM util helpers accessible
by moving local "tpm_util.h" to global "sysemu/tpm_util.h".
Reviewed-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
---
docs/specs/tpm.rst
We are going to make "tpm_util.h" publicly accessible by
moving it to the include/ directory in a pair of commits.
Keep declarations internals to hw/tpm/ in "tpm_int.h".
Reviewed-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_int.h | 11 +++
hw/tpm/tpm_util.h |
TPM subsytem is split into backends (see commit f4ede81eed2)
and frontends (see i.e. 3676bc69b35). Keep the emulated
hardware 'frontends' under hw/tpm/, but move the backends
in the backends/tpm/ directory.
Suggested-by: Marc-André Lureau
Signed-off-by: Philippe Mathieu-Daudé
---
RFC due to a
Commit 8dc6701722 introduce the documentation but an
incorrect path name was used. Fix that.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/specs/tpm.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
index 5e61238bc5..9e48e3b981
Hi,
Yesterday I started to review some vTPM patches and got very
confused by the files under hw/tpm/. In particular after
running:
$ git grep TYPE_TPM_BACKEND
backends/tpm.c:188:.name = TYPE_TPM_BACKEND,
hw/tpm/tpm_emulator.c:985:.parent = TYPE_TPM_BACKEND,
Nothing in "tpm_ppi.h" require declarations from "hw/acpi/tpm.h".
Reduce dependencies and include it only in the files requiring it.
Reviewed-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_ppi.h| 1 -
hw/tpm/tpm_ppi.c| 1 +
hw/tpm/tpm_tis_isa.c| 1 +
Files using the TPM_STANDARD_CMDLINE_OPTS macro declared in
"tpm_int.h" will use QEMU_OPT_STRING definition declared in
"qemu/option.h".
Reviewed-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
---
hw/tpm/tpm_int.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/tpm/tpm_int.h
As we will have various TPM backend files, it is cleaner
to use a single directory.
Suggested-by: Stefan Berger
Signed-off-by: Philippe Mathieu-Daudé
---
backends/{tpm.c => tpm/tpm_backend.c} | 0
MAINTAINERS | 2 +-
backends/Makefile.objs| 2 +-
From: Filip Bozuta
This patch implements strace argument printing functionality for following
syscall:
*fallocate - manipulate file space
int fallocate(int fd, int mode, off_t offset, off_t len)
man page: https://www.man7.org/linux/man-pages/man2/fallocate.2.html
From: Filip Bozuta
This patch implements strace argument printing functionality for syscall:
*lseek - reposition read/write file offset
off_t lseek(int fd, off_t offset, int whence)
man page: https://www.man7.org/linux/man-pages/man2/lseek.2.html
Implementation notes:
From: Filip Bozuta
Structure "struct syscallname" in file "strace.c" is used for "-strace"
to print arguments and return values of syscalls. The last field of
this structure "result" represents the calling function that prints the
return values. This field was extended in this
From: Filip Bozuta
This patch implements strace argument printing functionality for syscalls:
*chown, lchown - change ownership of a file
int chown(const char *pathname, uid_t owner, gid_t group)
int lchown(const char *pathname, uid_t owner, gid_t group)
man page:
From: Filip Bozuta
This patch implements strace argument printing functionality for following
syscalls:
*getxattr, lgetxattr, fgetxattr - retrieve an extended attribute value
ssize_t getxattr(const char *path, const char *name, void *value,
size_t size)
ssize_t
On 6/11/20 7:45 AM, Peter Maydell wrote:
> In commit 37bfce81b10450071 we accidentally introduced a leak of a TCG
> temporary in do_2shift_env_64(); free it.
>
> Signed-off-by: Peter Maydell
> ---
> My test setup wasn't looking for temporary-leak warnings (they are
> not as easy to get at as
On 6/11/20 7:45 AM, Peter Maydell wrote:
> Mark the arrays of function pointers in trans_VSHLL_S_2sh() and
> trans_VSHLL_U_2sh() as both 'static' and 'const'.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
On 11/06/2020 15:40, Greg Kurz wrote:
> We obviously only want to print a warning in these cases, but this is done
> in a rather convoluted manner. Just use warn_report() instead.
>
> Signed-off-by: Greg Kurz
> ---
> hw/ppc/spapr_caps.c | 28 ++--
> 1 file changed, 6
Since Ceph version Infernalis (9.2.0) the new fast-diff mechanism
of RBD allows for querying actual rbd image usage.
Prior to this version there was no easy and fast way to query how
much allocation a RBD image had inside a Ceph cluster.
To use the fast-diff feature it needs to be enabled per
On 11/06/2020 15:40, Greg Kurz wrote:
> We have a dedicated error API for hints. Use it instead of embedding
> the hint in the error message, as recommanded in the "qapi/error.h"
> header file.
>
> Since spapr_caps_apply() passes _fatal, all functions must
> also call the ERRP_AUTO_PROPAGATE()
Did anything ever happen here? Trying to upgrade Ubuntu ARM container
images using qemu-user on x86-64 from bionic to focal..
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https://bugs.launchpad.net/bugs/1594394
Title:
Using
On 6/11/20 9:59 AM, Eric Auger wrote:
In preparation of its move to the generic acpi code,
let's convert build_tpm2() to use build_append API. This
latter now is prefered in place of direct ACPI struct field
settings with manual endianness conversion.
Signed-off-by: Eric Auger
---
v3 ->
On Fri, Jun 05, 2020 at 07:35:34AM +0800, Coiby Xu wrote:
> v8
> - re-try connecting to socket server to fix asan error
> - fix license naming issue
Great, thanks for posting these patches!
I have posted feedback. I'd like to merge this soon. If you are busy I
can send you patches that address
On Fri, Jun 05, 2020 at 07:35:37AM +0800, Coiby Xu wrote:
> +static void coroutine_fn vu_block_virtio_process_req(void *opaque)
> +{
> +struct req_data *data = opaque;
> +VuServer *server = data->server;
> +VuVirtq *vq = data->vq;
> +VuVirtqElement *elem = data->elem;
> +
On 6/11/20 9:59 AM, Eric Auger wrote:
We plan to build the TPM2 table on ARM too. In order to reuse the
generation code, let's move build_tpm2() to aml-build.c.
No change in the implementation.
Signed-off-by: Eric Auger
Reviewed-by: Stefan Berger
---
include/hw/acpi/aml-build.h | 2
At the moment the virtio-iommu translates MSI transactions.
This behavior is inherited from ARM SMMU. The virt machine
code knows where the guest MSI doorbells are so we can easily
declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
setting the guest will not map MSIs through the IOMMU
When translating an address we need to check if it belongs to
a reserved virtual address range. If it does, there are 2 cases:
- it belongs to a RESERVED region: the guest should neither use
this address in a MAP not instruct the end-point to DMA on
them. We report an error
- It belongs to
The machine may need to pass reserved regions to the
virtio-iommu-pci device (such as the MSI window on x86).
So let's add an array of Interval properties.
Signed-off-by: Eric Auger
Reviewed-by: Jean-Philippe Brucker
---
v12 -> v12:
- added Jean's R-b
---
hw/virtio/virtio-iommu-pci.c | 3 +++
On 6/11/20 4:45 PM, Alex Bennée wrote:
> Pretty much all calls to qemu_log are either wrapped in some other
> enabling check or only enabled with debug defines. Add a specific flag
> for TCG warnings and expand the documentation of the qemu_log
> function.
>
> Signed-off-by: Alex Bennée
> Cc:
This patch implements the PROBE request. At the moment,
only THE RESV_MEM property is handled. The first goal is
to report iommu wide reserved regions such as the MSI regions
set by the machine code. On x86 this will be the IOAPIC MSI
region, [0xFEE0 - 0xFEEF], on ARM this may be the ITS
Introduce a new property defining a reserved region:
, , .
This will be used to encode reserved IOVA regions.
For instance, in virtio-iommu use case, reserved IOVA regions
will be passed by the machine code to the virtio-iommu-pci
device (an array of those). The type of the reserved region
will
By default the virtio-iommu translates MSI transactions. This
behavior is inherited from ARM SMMU. However the virt machine
code knows where the MSI doorbells are, so we can easily
declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
setting the guest iommu subsystem will not need to
On Thu, Jun 11, 2020 at 03:24:31PM +0200, Claudio Fontana wrote:
> On 6/4/20 8:27 PM, Paolo Bonzini wrote:
> > On 28/05/20 21:37, Roman Bolshakov wrote:
> >> There's no similar field in CPUX86State, but it's needed for MMIO traps.
> >>
> >> Signed-off-by: Roman Bolshakov
> >> ---
> >>
Convert the Neon VEXT insn to decodetree. Rather than keeping the
old implementation which used fixed temporaries cpu_V0 and cpu_V1
and did the extraction with by-hand shift and logic ops, we use
the TCG extract2 insn.
We don't need to special case 0 or 8 immediates any more as the
optimizer is
Hi Stefan,
On 6/11/20 4:25 PM, Stefan Berger wrote:
> On 6/11/20 9:59 AM, Eric Auger wrote:
>> In preparation of its move to the generic acpi code,
>> let's convert build_tpm2() to use build_append API. This
>> latter now is prefered in place of direct ACPI struct field
>> settings with manual
Convert the VMLA, VMLS and VMUL insns in the Neon "2 registers and a
scalar" group to decodetree. These are 32x32->32 operations where
one of the inputs is the scalar, followed by a possible accumulate
operation of the 32-bit result.
The refactoring removes some of the oddities of the old
Hi Stefan,
On 6/11/20 4:25 PM, Stefan Berger wrote:
> On 6/11/20 9:59 AM, Eric Auger wrote:
>> In preparation of its move to the generic acpi code,
>> let's convert build_tpm2() to use build_append API. This
>> latter now is prefered in place of direct ACPI struct field
>> settings with manual
Convert the VQDMULH and VQRDMULH insns in the 2-reg-scalar group
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 3 +++
target/arm/translate-neon.inc.c | 29 +++
target/arm/translate.c | 42 ++---
3
On Thu, 11 Jun 2020 at 15:45, Alex Bennée wrote:
>
> Pretty much all calls to qemu_log are either wrapped in some other
> enabling check or only enabled with debug defines. Add a specific flag
> for TCG warnings and expand the documentation of the qemu_log
> function.
>
> Signed-off-by: Alex
Pretty much all calls to qemu_log are either wrapped in some other
enabling check or only enabled with debug defines. Add a specific flag
for TCG warnings and expand the documentation of the qemu_log
function.
Signed-off-by: Alex Bennée
Cc: Peter Maydell
---
include/qemu/log-for-trace.h | 9
Convert the Neon VDUP (scalar) insn to decodetree. (Note that we
can't call this just "VDUP" as we used that already in vfp.decode for
the "VDUP (general purpose register" insn.)
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 7 +++
target/arm/translate-neon.inc.c | 26
This patchset converts the whole 2-reg-scalar group to decodetree,
together with the VEXT, VTBL, VTBX, VDUP insns which don't fall
into any particular group. The only remaining unconverted Neon
insns are now the "2 registers misc" group.
Based-on: 20200609160209.29960-1-peter.mayd...@linaro.org
Convert the VQRDMLAH and VQRDMLSH insns in the 2-reg-scalar
group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 3 ++
target/arm/translate-neon.inc.c | 74 +
target/arm/translate.c | 38 +
3 files
Convert the float versions of VMLA, VMLS and VMUL in the Neon
2-reg-scalar group to decodetree.
Signed-off-by: Peter Maydell
---
As noted in the comment on the WRAP_FP_FN macro, we could have
had a do_2scalar_fp() function, but for 3 insns it seemed
simpler to just do the wrapping to get hold of
Mark the arrays of function pointers in trans_VSHLL_S_2sh() and
trans_VSHLL_U_2sh() as both 'static' and 'const'.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-neon.inc.c
201 - 300 of 489 matches
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