[Bug 1885350] [NEW] RISCV dynamic rounding mode is not behaving correctly

Public bug reported: Hello, I’ve gone through the RISC-V code in latest QEMU release (qemu-5.0.0-rc2) and when checking the Floating point encodings I found the rounding mode is only updated if the opcode field “rm” is changed “ctx->frm == rm”. But according to RISC-V Volume I: Unprivileged ISA,

Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM

On Fri, Jun 26, 2020 at 9:37 PM Atish Patra wrote: > > On Fri, Jun 26, 2020 at 7:54 PM Bin Meng wrote: > > > > Hi Atish, > > > > On Sat, Jun 27, 2020 at 12:58 AM Atish Patra wrote: > > > > > > On Fri, Jun 26, 2020 at 4:50 AM Bin Meng wrote: > > > > > > > > Hi Atish, > > > > > > > > On Fri, Jun

Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM

On Fri, Jun 26, 2020 at 7:54 PM Bin Meng wrote: > > Hi Atish, > > On Sat, Jun 27, 2020 at 12:58 AM Atish Patra wrote: > > > > On Fri, Jun 26, 2020 at 4:50 AM Bin Meng wrote: > > > > > > Hi Atish, > > > > > > On Fri, Jun 26, 2020 at 8:33 AM Atish Patra wrote: > > > > > > > > Currently, the fdt

Re: [PATCH v3 2/3] RISC-V: Copy the fdt in dram instead of ROM

Hi Atish, On Sat, Jun 27, 2020 at 12:58 AM Atish Patra wrote: > > On Fri, Jun 26, 2020 at 4:50 AM Bin Meng wrote: > > > > Hi Atish, > > > > On Fri, Jun 26, 2020 at 8:33 AM Atish Patra wrote: > > > > > > Currently, the fdt is copied to the ROM after the reset vector. The > > > firmware > > >

Re: [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines

Patchew URL: https://patchew.org/QEMU/20200626235519.591734-1-hskinnem...@google.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT

[PATCH v3 11/12] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj

This allows these NPCM7xx-based boards to boot from a flash image, e.g. one built with OpenBMC. For example like this: IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc qemu-system-arm -machine quanta-gsj -nographic \ -bios ~/qemu/bootrom/npcm7xx_bootrom.bin \ -drive

[PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model

This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman Signed-off-by: Havard Skinnemoen --- hw/arm/npcm7xx.c | 32 +++ hw/nvram/Makefile.objs | 1 + hw/nvram/npcm7xx_otp.c

[PATCH v3 10/12] hw/ssi: NPCM7xx Flash Interface Unit device model

This implements a device model for the NPCM7xx SPI flash controller. Direct reads and writes, and user-mode transactions have been tested in various modes. Protection features are not implemented yet. All the FIU instances are available in the SoC's address space, regardless of whether or not

[PATCH v3 12/12] docs/system: Add Nuvoton machine documentation

Reviewed-by: Cédric Le Goater Signed-off-by: Havard Skinnemoen --- docs/system/arm/nuvoton.rst | 92 + docs/system/target-arm.rst | 1 + 2 files changed, 93 insertions(+) create mode 100644 docs/system/arm/nuvoton.rst diff --git

[PATCH v3 09/12] hw/mem: Stubbed out NPCM7xx Memory Controller model

This just implements the bare minimum to cause the boot block to skip memory initialization. Reviewed-by: Tyrone Ting Reviewed-by: Cédric Le Goater Signed-off-by: Havard Skinnemoen --- hw/arm/npcm7xx.c| 10 + hw/mem/Makefile.objs| 1 + hw/mem/npcm7xx_mc.c | 83

[PATCH v3 07/12] hw/arm: Load -bios image as a boot ROM for npcm7xx

If a -bios option is specified on the command line, load the image into the internal ROM memory region, which contains the first instructions run by the CPU after reset. A minimal Apache-2.0-licensed boot ROM can be found at https://github.com/google/vbootrom It is by no means feature complete,

[PATCH v3 06/12] hw/arm: Add two NPCM7xx-based machines

This adds two new machines, both supported by OpenBMC: - npcm750-evb: Nuvoton NPCM750 Evaluation Board. - quanta-gsj: A board with a NPCM730 chip. They rely on the NPCM7xx SoC device to do the heavy lifting. They are almost completely identical at the moment, apart from the SoC type, which

[PATCH v3 04/12] hw/timer: Add NPCM7xx Timer device model

The NPCM730 and NPCM750 SoCs have three timer modules each holding five timers and some shared registers (e.g. interrupt status). Each timer runs at 25 MHz divided by a prescaler, and counts down from a configurable initial value to zero. When zero is reached, the interrupt flag for the timer is

[PATCH v3 03/12] hw/misc: Add NPCM7xx Clock Controller device model

Enough functionality to boot the Linux kernel has been implemented. This includes: - Correct power-on reset values so the various clock rates can be accurately calculated. - Clock enables stick around when written. In addition, a best effort attempt to implement SECCNT and CNTR25M was

[PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models

The Nuvoton NPCM7xx SoC family are used to implement Baseboard Management Controllers in servers. While the family includes four SoCs, this patch implements limited support for two of them: NPCM730 (targeted for Data Center applications) and NPCM750 (targeted for Enterprise applications). This

[PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines

Time for another refresh of this patchset. Sorry it took so long -- I've been trying to figure out why the Winbond flash model isn't working with npcm750-evb, and I'm fairly convinced the number of dummy cycles in DIO mode should be 4, not 1. Unfortunately, I don't see any other machines using

[PATCH v3 02/12] hw/misc: Add NPCM7xx System Global Control Registers device model

Implement a device model for the System Global Control Registers in the NPCM730 and NPCM750 BMC SoCs. This is primarily used to enable SMP boot (the boot ROM spins reading the SCRPAD register) and DDR memory initialization; other registers are best effort for now. The reset values of the MDLR

[PATCH v3 01/12] npcm7xx: Add config symbol

Add a config symbol for the NPCM7xx BMC SoC family that subsequent patches can use in Makefiles. Reviewed-by: Tyrone Ting Acked-by: Joel Stanley Signed-off-by: Havard Skinnemoen --- default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 8 2 files changed, 9

[Bug 1885332] Re: Error in user-mode calculation of ELF aux vector's AT_PHDR

I just confirmed that this is still a problem on git tag v5.0.0, where I applied the following: diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 619c054cc4..093656d059 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2016,6 +2016,7 @@ static abi_ulong

Re: [PATCH QEMU v25 03/17] vfio: Add save and load functions for VFIO PCI devices

On Fri, 26 Jun 2020 13:16:13 +0100 "Dr. David Alan Gilbert" wrote: > * Alex Williamson (alex.william...@redhat.com) wrote: > > On Wed, 24 Jun 2020 19:59:39 +0530 > > Kirti Wankhede wrote: > > > > > On 6/23/2020 1:58 AM, Alex Williamson wrote: > > > > On Sun, 21 Jun 2020 01:51:12 +0530 > >

Re: [PULL 00/63] riscv-to-apply queue

Patchew URL: https://patchew.org/QEMU/20200626214410.3613258-1-alistair.fran...@wdc.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT

Re: [PULL 00/63] riscv-to-apply queue

Patchew URL: https://patchew.org/QEMU/20200626214410.3613258-1-alistair.fran...@wdc.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PULL 00/63] riscv-to-apply queue Type: series Message-id:

Re: [PATCH v5 07/11] mac_oldworld: Map macio to expected address at reset

On Fri, 26 Jun 2020, Mark Cave-Ayland wrote: On 16/06/2020 14:47, BALATON Zoltan wrote: Add a reset function that maps macio to the address expected by the firmware of the board at startup. Signed-off-by: BALATON Zoltan --- hw/ppc/mac.h | 12 hw/ppc/mac_oldworld.c | 15

Re: [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls

On Fri, Jun 26, 2020 at 3:01 PM Jessica Clarke wrote: > > On 26 Jun 2020, at 22:43, Alistair Francis wrote: > > > > From: Jessica Clarke > > > > Claiming an interrupt and changing the source priority both potentially > > affect whether an interrupt is pending, thus we must re-compute xEIP. > >

Re: [PATCH v5 01/11] mac_oldworld: Allow loading binary ROM image

On Fri, 26 Jun 2020, Mark Cave-Ayland wrote: On 16/06/2020 14:47, BALATON Zoltan wrote: The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of the rom region and fall back to loading a binary image with -bios if loading ELF image failed. This allows testing emulation with a ROM

[PULL 61/63] target/riscv: vector register gather instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-60-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 3 +

Re: [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls

On 26 Jun 2020, at 22:43, Alistair Francis wrote: > > From: Jessica Clarke > > Claiming an interrupt and changing the source priority both potentially > affect whether an interrupt is pending, thus we must re-compute xEIP. > Note that we don't put the sifive_plic_update inside

[PULL 60/63] target/riscv: vector slide instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-59-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++

[PULL 63/63] target/riscv: configure and turn on vector extension from command line

From: LIU Zhiwei Vector extension is default off. The only way to use vector extension is 1. use cpu rv32 or rv64 2. turn on it by command line "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size

[PULL 59/63] target/riscv: floating-point scalar move instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-58-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 49 + 2

[PATCH 0/3] Add strace support for printing arguments for a group of selected syscalls

This series covers strace support for following syscalls: *truncate() *munlock() *clock_gettimeofday() *ftruncate()*munlockall() *clock_getitimer() *getsid() *clock_getres() *clock_setitimer() *mlock()*clock_gettime() *mlockall()

[PULL 55/63] target/riscv: vector iota instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-54-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 +

[PULL 58/63] target/riscv: integer scalar move instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-57-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/internals.h| 6 +++ target/riscv/insn32.decode | 1 +

[PULL 56/63] target/riscv: vector element index instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-55-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++

Re: [PATCH v5 06/11] mac_oldworld: Rename ppc_heathrow_reset to ppc_heathrow_cpu_reset

On Fri, 26 Jun 2020, Mark Cave-Ayland wrote: On 16/06/2020 14:47, BALATON Zoltan wrote: This function resets a CPU not the whole machine so reflect that in its name. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé --- hw/ppc/mac_oldworld.c | 4 ++-- 1 file changed, 2

[PULL 57/63] target/riscv: integer extract instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-56-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 116 2

[PULL 52/63] target/riscv: vector mask population count vmpopc

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-51-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 +

[PULL 51/63] target/riscv: vector mask-register logical instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-50-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 +

[PULL 50/63] target/riscv: vector widening floating-point reduction instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-49-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2

[PULL 62/63] target/riscv: vector compress instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-61-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 +

[PULL 53/63] target/riscv: vmfirst find-first-set mask bit

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-52-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 +

[PULL 54/63] target/riscv: set-X-first mask bit

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-53-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 3 ++

[PULL 33/63] target/riscv: vector widening floating-point add/subtract instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-32-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode |

[PULL 49/63] target/riscv: vector single-width floating-point reduction instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-48-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 10 +++ target/riscv/insn32.decode |

[PULL 48/63] target/riscv: vector wideing integer reduction instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-47-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode |

[PULL 26/63] target/riscv: vector single-width saturating add and subtract

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-25-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10

[PULL 27/63] target/riscv: vector single-width averaging add and subtract

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-26-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode |

[PULL 47/63] target/riscv: vector single-width integer reduction instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-46-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode

[PULL 32/63] target/riscv: vector single-width floating-point add/subtract instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-31-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode |

[PULL 25/63] target/riscv: vector integer merge and move instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-24-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode |

[PULL 31/63] target/riscv: vector narrowing fixed-point clip instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-30-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 13 +++ target/riscv/insn32.decode |

[PULL 24/63] target/riscv: vector widening integer multiply-add instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-23-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 22 target/riscv/insn32.decode

[PULL 45/63] target/riscv: widening floating-point/integer type-convert instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-44-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode |

[PULL 46/63] target/riscv: narrowing floating-point/integer type-convert instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-45-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode |

[PULL 41/63] target/riscv: vector floating-point compare instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-40-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 37 + target/riscv/insn32.decode |

[PULL 29/63] target/riscv: vector widening saturating scaled multiply-add

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-28-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode |

[PULL 44/63] target/riscv: vector floating-point/integer type-convert instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-43-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode

[PULL 30/63] target/riscv: vector single-width scaling shift instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-29-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode |

[PULL 23/63] target/riscv: vector single-width integer multiply-add instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-22-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode

[PULL 43/63] target/riscv: vector floating-point merge instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-42-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 2

[PULL 10/63] target/riscv: add fault-only-first unit stride load

From: LIU Zhiwei The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair

[PULL 28/63] target/riscv: vector single-width fractional multiply with rounding and saturation

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-27-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2

[PULL 09/63] target/riscv: add vector index load and store instructions

From: LIU Zhiwei Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson

[PULL 42/63] target/riscv: vector floating-point classify instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-41-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 ++ target/riscv/internals.h| 5

[PULL 40/63] target/riscv: vector floating-point sign-injection instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-39-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 19 ++ target/riscv/insn32.decode |

[PULL 08/63] target/riscv: add vector stride load and store instructions

From: LIU Zhiwei Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in

[PULL 38/63] target/riscv: vector floating-point square-root instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-37-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 3

[PULL 21/63] target/riscv: vector integer divide instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-20-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode

[PULL 22/63] target/riscv: vector widening integer multiply instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-21-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 19 + target/riscv/insn32.decode

[PULL 19/63] target/riscv: vector integer min/max instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-18-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 33 target/riscv/insn32.decode

[PULL 20/63] target/riscv: vector single-width integer multiply instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-19-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 33 + target/riscv/insn32.decode |

[PULL 18/63] target/riscv: vector integer comparison instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-17-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode

[PULL 16/63] target/riscv: vector single-width bit shift instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-15-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode

[PULL 35/63] target/riscv: vector widening floating-point multiply

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-34-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 5 + target/riscv/insn32.decode |

[PULL 39/63] target/riscv: vector floating-point min/max instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-38-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode

[PULL 34/63] target/riscv: vector single-width floating-point multiply/divide instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-33-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode

[PULL 37/63] target/riscv: vector widening floating-point fused multiply-add instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-36-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 17 + target/riscv/insn32.decode |

[PULL 15/63] target/riscv: vector bitwise logical instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-14-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode

[PULL 03/63] target/riscv: add vector extension field in CPURISCVState

From: LIU Zhiwei The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis

[PULL 06/63] target/riscv: add vector configure instruction

From: LIU Zhiwei vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair

[PULL 36/63] target/riscv: vector single-width floating-point fused multiply-add instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-35-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 49 + target/riscv/insn32.decode |

[PULL 04/63] target/riscv: implementation-defined constant parameters

From: LIU Zhiwei vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id:

[PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-13-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode |

[PULL 05/63] target/riscv: support vector extension csr

From: LIU Zhiwei The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id:

[PULL 07/63] target/riscv: add an internals.h header

From: LIU Zhiwei The internals.h keeps things that are not relevant to the actual architecture, only to the implementation, separate. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-6-zhiwei_...@c-sky.com Signed-off-by:

[PULL 13/63] target/riscv: vector widening integer add and subtract

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-12-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 49 +++ target/riscv/insn32.decode

[PULL 01/63] riscv: plic: Honour source priorities

From: Jessica Clarke The source priorities can be used to order sources with respect to other sources, not just as a way to enable/disable them based off a threshold. We must therefore always claim the highest-priority source, rather than the first source we find. Signed-off-by: Jessica Clarke

[PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls

From: Jessica Clarke Claiming an interrupt and changing the source priority both potentially affect whether an interrupt is pending, thus we must re-compute xEIP. Note that we don't put the sifive_plic_update inside sifive_plic_claim so that the logging of a claim (and the resulting IRQ) happens

[PULL 17/63] target/riscv: vector narrowing integer right shift instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20200623215920.2594-16-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 6

[PULL 11/63] target/riscv: add vector amo operations

From: LIU Zhiwei Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei

[PULL 12/63] target/riscv: vector single-width integer add and subtract

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20200623215920.2594-11-zhiwei_...@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/helper.h | 25 ++ target/riscv/insn32.decode | 10

[PULL 00/63] riscv-to-apply queue

The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26 18:22:36 +0100) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv

Re: [PATCH] hw/arm: Add 'virtm' hardware

On Fri, 26 Jun 2020 at 21:14, Keith Packard wrote: > > Max Filippov writes: > > > Most of them are due to unsupported/differently implemented > > syscalls. > > Yeah, I think that was the basis of my confusion -- qemu-arm is not a > bare metal environment, and my work is focused on enabling

[PATCH 2/3] linux-user: Add strace support for printing arguments of syscalls used to lock and unlock memory

This patch implements strace argument printing functionality for following syscalls: * mlock, munlock, mlockall, munlockall - lock and unlock memory int mlock(const void *addr, size_t len) int munlock(const void *addr, size_t len) int mlockall(int flags) int

[PATCH 1/3] linux-user: Add strace support for printing arguments of truncate()/ftruncate() and getsid()

This patch implements strace argument printing functionality for following syscalls: * truncate, ftruncate - truncate a file to a specified length int truncate(const char *path, off_t length) int ftruncate(int fd, off_t length) man page:

[PATCH 3/3] linux-user: Add strace support for printing arguments of some clock and time functions

This patch implements strace argument printing functionality for following syscalls: * clock_getres, clock_gettime, clock_settime - clock and time functions int clock_getres(clockid_t clockid, struct timespec *res) int clock_gettime(clockid_t clockid, struct timespec *tp)

Re: [RFC v2 1/1] memory: Delete assertion in memory_region_unregister_iommu_notifier

Hi, Eugenio, (CCing Eric, Yan and Michael too) On Fri, Jun 26, 2020 at 08:41:22AM +0200, Eugenio Pérez wrote: > diff --git a/memory.c b/memory.c > index 2f15a4b250..7f789710d2 100644 > --- a/memory.c > +++ b/memory.c > @@ -1915,8 +1915,6 @@ void memory_region_notify_one(IOMMUNotifier *notifier,

Re: [PATCH v6 1/9] hw/i2c/core: Add i2c_try_create_slave() and i2c_realize_and_unref()

On Fri, Jun 26, 2020 at 8:27 PM Peter Maydell wrote: > On Tue, 23 Jun 2020 at 08:27, Philippe Mathieu-Daudé wrote: > > Extract i2c_try_create_slave() and i2c_realize_and_unref() > > from i2c_create_slave(). > > We can now set properties on a I2CSlave before it is realized. > > > > This is in

Re: [PATCH v2 0/2] linux-user/sparc64: Translate flushw opcode

On 6/25/20 2:12 AM, Laurent Vivier wrote: > I send a modified version according to Richard's comments of the original > series sent by Giuseppe Musacchio (aka LemonBoy). > > v2: split patch in two patches > update comment style > > I didn't really test the new patches (except a build and

Re: [PATCH 0/6] target/riscv: NaN-boxing for multiple precison

Patchew URL: https://patchew.org/QEMU/20200626205917.4545-1-zhiwei_...@c-sky.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN

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