Added fallthrough comment on line 270 to fix compiler warning
Signed-off-by: Rohit Shinde
---
qapi/opts-visitor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/opts-visitor.c b/qapi/opts-visitor.c
index 43cf60d3a0..3422ff265e 100644
--- a/qapi/opts-visitor.c
+++
On Sat, Aug 15, 2020 at 1:29 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/14/20 7:52 PM, Frank Chang wrote:
> > probe_pages(env, base + stride * i, nf * esz, ra, access_type);
> > and
> > target_ulong addr = base + stride * i + k * esz;
> >
> > If we pass
On 2020/8/14 22:50, Li Qiang wrote:
> Pan Nengyuan 于2020年8月14日周五 下午6:18写道：
>>
>> Fix a memleak in test_socket_unix_abstract_good().
>>
>> Reported-by: Euler Robot
>> Signed-off-by: Pan Nengyuan
>> ---
>
> Hi Nengyuan,
> I have sent this two month ago:
>
Patchew URL:
https://patchew.org/QEMU/1597458180-16945-1-git-send-email-zhengch...@huawei.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST
Patchew URL:
https://patchew.org/QEMU/1597458180-16945-1-git-send-email-zhengch...@huawei.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST
Patchew URL:
https://patchew.org/QEMU/1597458180-16945-1-git-send-email-zhengch...@huawei.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1597458180-16945-1-git-send-email-zhengch...@huawei.com
Subject: [PATCH v2
On 8/13/2020 8:48 PM, Andrew Jones wrote:
> On Thu, Aug 13, 2020 at 06:26:53PM +0800, Peng Liang wrote:
>> Some CPU features are dependent on other CPU features. For example,
>> ID_AA64PFR0_EL1.FP field and ID_AA64PFR0_EL1.AdvSIMD must have the same
>> value, which means FP and ADVSIMD are
On 8/13/2020 8:21 PM, Andrew Jones wrote:
> On Thu, Aug 13, 2020 at 06:26:50PM +0800, Peng Liang wrote:
>> The implementation of CPUClass::parse_features only supports CPU
>> features in "feature=value" format. However, libvirt maybe send us a
>> CPU feature string in "+feature/-feature" format.
On 8/13/2020 8:56 PM, Andrew Jones wrote:
> On Thu, Aug 13, 2020 at 06:26:55PM +0800, Peng Liang wrote:
>> Add CPU features to the result of query-cpu-model-expansion so that
>> other applications (such as libvirt) can know the supported CPU
>> features.
>>
>> Signed-off-by: zhanghailiang
>>
On 8/13/2020 7:00 PM, Cornelia Huck wrote:
> On Thu, 13 Aug 2020 18:26:54 +0800
> Peng Liang wrote:
>
>> Introduce KVM_CAP_ARM_CPU_FEATURE to check whether KVM supports to set
>> CPU features in ARM.
>>
>> Signed-off-by: zhanghailiang
>> Signed-off-by: Peng Liang
>> ---
>>
v1 -> v2:
use g_rand_new() to generate rand_buf
move RAMBLOCK_FOREACH_MIGRATABLE into migration/ram.h
add skip_sample_ramblock to filter sampled ramblock
fix multi-numa vm coredump when query dirtyrate
rename qapi interface and rename some structures and functions
succeed
From: Zheng Chuan
RAMBLOCK_FOREACH_MIGRATABLE is need in dirtyrate measure,
move the existing definition up into migration/ram.h
Signed-off-by: Zheng Chuan
---
migration/dirtyrate.c | 1 +
migration/ram.c | 11 +--
migration/ram.h | 10 ++
3 files changed, 12
From: Zheng Chuan
Implement get_sample_page_period() and set_sample_page_period() to
sleep specific time between sample actions.
Signed-off-by: Zheng Chuan
Signed-off-by: YanYing Zhuang
---
migration/dirtyrate.c | 23 +++
migration/dirtyrate.h | 2 ++
2 files changed, 25
From: Zheng Chuan
Add get_dirtyrate_thread() functions
Signed-off-by: Zheng Chuan
Signed-off-by: YanYing Zhuang
---
migration/Makefile.objs | 1 +
migration/dirtyrate.c | 64 +
migration/dirtyrate.h | 44 ++
From: Zheng Chuan
In order to sample real RAM, skip ramblock with size below
MIN_RAMBLOCK_SIZE which is 128M as default.
Signed-off-by: Zheng Chuan
---
migration/dirtyrate.c | 24
migration/dirtyrate.h | 5 +
2 files changed, 29 insertions(+)
diff --git
From: Zheng Chuan
Compare page hash results for recorded sampled page.
Signed-off-by: Zheng Chuan
Signed-off-by: YanYing Zhuang
---
migration/dirtyrate.c | 73 +++
1 file changed, 73 insertions(+)
diff --git a/migration/dirtyrate.c
From: Zheng Chuan
Implement qmp_cal_dirty_rate()/qmp_get_dirty_rate() function which could be
called
Signed-off-by: Zheng Chuan
---
migration/dirtyrate.c | 56 +++
qapi/migration.json | 42 ++
2 files
From: Zheng Chuan
Add dirtyrate statistics to record/update dirtyrate info.
Signed-off-by: Zheng Chuan
---
migration/dirtyrate.c | 30 ++
migration/dirtyrate.h | 10 ++
2 files changed, 40 insertions(+)
diff --git a/migration/dirtyrate.c
From: Zheng Chuan
Record hash results for each sampled page.
Signed-off-by: Zheng Chuan
Signed-off-by: YanYing Zhuang
---
migration/dirtyrate.c | 135 ++
migration/dirtyrate.h | 7 +++
2 files changed, 142 insertions(+)
diff --git
From: Zheng Chuan
Add RamlockDirtyInfo to store sampled page info of each ramblock.
Signed-off-by: Zheng Chuan
---
migration/dirtyrate.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/migration/dirtyrate.h b/migration/dirtyrate.h
index 914c363..9650566 100644
---
From: Zheng Chuan
Implement calculate_dirtyrate() function.
Signed-off-by: Zheng Chuan
Signed-off-by: YanYing Zhuang
---
migration/dirtyrate.c | 46 --
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/migration/dirtyrate.c
Patchew URL:
https://patchew.org/QEMU/20200815013145.539409-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200815013145.539409-1-richard.hender...@linaro.org
Subject: [PATCH 00/20]
Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
indicating which kind of register and in which order.
Model do_zzz_fn on the other do_foo functions that take an
argument set and verify sve enabled.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 43
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 4
target/arm/translate-a64.c | 16
target/arm/vec_helper.c| 29 +
3 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
Unify add/sub helpers and add a parameter for rounding.
This will allow saturating non-rounding to reuse this code.
Signed-off-by: Richard Henderson
---
target/arm/vec_helper.c | 80 +++--
1 file changed, 29 insertions(+), 51 deletions(-)
diff --git
> -Original Message-
> From: Derek Su [mailto:jwsu1...@gmail.com]
> Sent: Thursday, August 13, 2020 6:28 PM
> To: Lukas Straub
> Cc: Derek Su ; qemu-devel@nongnu.org; Zhanghailiang
> ; chy...@qnap.com; quint...@redhat.com;
> dgilb...@redhat.com; ctch...@qnap.com
> Subject: Re: [PATCH v1
The crypto overhead of emulating pauth can be significant for
some workloads. Add two boolean properties that allows the
feature to be turned off, on with the architected algorithm,
or on with an implementation defined algorithm.
We need two intermediate booleans to control the state while
Hey Philippe,
Thanks for the detailed comments! I have a couple of questions.
1. I'll modify the patch to just include a fallthrough comment instead
of an attribute. How do I include the v4 version number in the patch? Do I
erase the last commit on my branch or fork from the master and
Patchew URL:
https://patchew.org/QEMU/159744083536.39197.13827776633866601278.st...@naples-babu.amd.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana
> ---
> accel/kvm/kvm-cpus.h | 7 +++
> accel/stubs/kvm-stub.c | 22 --
> include/sysemu/kvm.h | 7 ---
> 3 files changed, 7 insertions(+), 29 deletions(-)
Reviewed-by: Richard
This is the only user of the function.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b0fa38db1c..d310709de3 100644
---
The pSeries machine does not support asymmetrical NUMA configurations.
CC: Eduardo Habkost
CC: Marcel Apfelbaum
Signed-off-by: Daniel Henrique Barboza
---
hw/core/numa.c | 7 +++
hw/ppc/spapr.c | 1 +
include/hw/boards.h | 1 +
3 files changed, 9 insertions(+)
diff --git
Model after gen_gvec_fn_zzz et al.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index ea6058f7ef..3361e1c01f 100644
---
The ibm,max-associativity-domains is considering that only a single
associativity domain can exist in the same NUMA level. This is true
today because we do not support any type of NUMA distance user
customization, and all nodes are in the same distance to each other.
To enhance NUMA distance
Missed out on compressing the second half of a predicate
with length vl % 512 > 256.
Adjust all of the x + (y << s) to x | (y << s) as a
general style fix.
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 30 +-
1 file
On Fri, Aug 14, 2020 at 11:15 AM Paolo Bonzini wrote:
>
> Hi Paolo,
I don't know how much of this is already meant to work, but I run into
several issues when compiling the latest code from the meson-poc-next
branch.
1. MSYS2-based Windows build: The guide to compile e.g., qemu-system-ppc on
Philippe Mathieu-Daudé 于2020年8月14日周五 下午4:33写道：
>
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
> ---
> hw/ide/pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ide/pci.c
We want to ensure that access is checked by the time we ask
for a specific fp/vector register. We want to ensure that
we do not emit two lots of code to raise an exception.
But sometimes it's difficult to cleanly organize the code
such that we never pass through sve_check_access exactly once.
On Sat, Aug 15, 2020 at 2:36 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/13/20 7:48 PM, Frank Chang wrote:
> > esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro:
> >
> >> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)\
> >> void HELPER(NAME)(void *vd, void * v0,
The interface for object_property_add_bool is simpler,
making the code easier to understand.
Reviewed-by: Andrew Jones
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu64.c
Philippe Mathieu-Daudé 于2020年8月14日周五 下午4:29写道：
>
> As it is not obvious the default size for the null block driver
> is 1 GiB, replace the obfuscated '1 << 30' magic value by a
> definition using IEC binary prefixes.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
> ---
>
The architected pauth algorithm is quite slow without
hardware support, and boot times for kernels that enable
use of the feature have been significantly impacted.
Version 1 blurb at
https://lists.nongnu.org/archive/html/qemu-devel/2020-08/msg02172.html
which contains larger study of the
Fixed in QEMU 5.1 release.
** Changed in: qemu
Status: Fix Committed => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1877688
Title:
9p virtfs device reports error when
Patchew URL:
https://patchew.org/QEMU/20200815151245.10640-1-rohit.shinde12...@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
Philippe Mathieu-Daudé 于2020年8月14日周五 下午4:31写道：
>
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
> ---
> hw/ide/ahci.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ide/ahci.c
Without hardware acceleration, a cryptographically strong
algorithm is too expensive for pauth_computepac.
Even with hardware accel, we are not currently expecting
to link the linux-user binaries to any crypto libraries,
and doing so would generally make the --static build fail.
So choose XXH64
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana
> ---
> accel/stubs/hax-stub.c| 10 --
> include/sysemu/hax.h | 17 -
> target/i386/hax-all.c | 1 -
> target/i386/hax-cpus.c| 1 -
> target/i386/hax-cpus.h| 16
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 53 +-
1 file changed, 18 insertions(+), 35 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 3361e1c01f..3a90a645fd 100644
---
On 8/14/20 6:40 PM, Bin Meng wrote:
> From: Bin Meng
>
> Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
> controller. The SDHCI compatible registers start from offset 0x200,
> which are called Slot Register Set (SRS) in its datasheet.
>
> This creates a Cadence SDHCI model
On 8/14/20 6:40 PM, Bin Meng wrote:
> From: Bin Meng
>
> sdhci_poweron_reset() might be needed for any SDHCI compatible
> device that is built on top of the generic SDHCI device.
NAck. Please use device_legacy_reset() instead.
In next patch:
device_legacy_reset(DEVICE(>slot));
Thanks,
+Sai Pavan
On 8/14/20 6:40 PM, Bin Meng wrote:
> From: Bin Meng
>
> At present the function switch status data structure bit [399:376]
> are wrongly pupulated. These 3 bytes encode function switch status
> for the 6 function groups, with 4 bits per group, starting from
> function group 6 at bit
Philippe Mathieu-Daudé 于2020年8月14日周五 下午4:31写道：
>
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
> ---
> hw/ide/core.c | 23 ---
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff
Hi,
This series implements a new approach to the NUMA code in
the spapr machine. We're now able to make an attempt to
try to take user input in consideration, instead of ignoring
any user input regarding NUMA distance.
This series was rebased upon David's ppc-for-5.2 tree. More
information about
Patchew URL:
https://patchew.org/QEMU/20200815151148.10571-1-rohit.shinde12...@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
Public bug reported:
Issue discovered while trying to build pikvm (1)
Long story short: when using qemu-arm-static 5.1, gcc exits whith
message:
Allocating guest commpage: Operation not permitted
when using qemu-arm-static v5.0, gcc "works"
Steps to reproduce will follow
(1)
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 14 ++
target/arm/translate-a64.c | 34 ++
target/arm/vec_helper.c| 25 +
3 files changed, 73 insertions(+)
diff --git a/target/arm/helper.h
Wrote too much with punpk1 with vl % 512 != 0.
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index b8651ae173..c983cd4356
This update provides more in depth information about the
choices and drawbacks of the new NUMA support for the
spapr machine.
Signed-off-by: Daniel Henrique Barboza
---
docs/specs/ppc-spapr-numa.rst | 213 ++
1 file changed, 213 insertions(+)
diff --git
Additional info,
error message text ( "Allocating guest commpage" ) found in this commit:
https://fossies.org/diffs/qemu/5.0.0_vs_5.1.0-rc0/linux-user/elfload.c-diff.html
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
Public bug reported:
I have written a program that used CGA Mode 6 (640x200 black and white).
However qemu-system-i386 only displays the first 100 pixels, effectively
limiting the resolution of mode 6 to 640x100. When running the same
program on a real computer it uses the whole 640x200 pixels.
Steps to reproduce
1. Download and extract attached tarball.
$ make # will build the docker container
$ make run # will enter the container
# once in the container, run
# /qemu-arm-static-50 /bin/bash /runme.sh
** Attachment added: "qemu-1891748-1.tgz"
Model after gen_gvec_fn_zzz et al.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 35 ---
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index aa7ed070e3..535d086838
The value of ibm,associativity-reference-points is in sync with
what Skiboot does. It's a three level NUMA configuration where
the first two levels references the same associativity index
(0x4), meaning that the next distance after the local_distance
(10) is two orders away (a '40' value in the
On 8/14/20 6:40 PM, Bin Meng wrote:
> From: Bin Meng
>
> Per the SD spec, Standard Capacity SD Memory Card (SDSC) supports
> capacity up to and including 2 GiB.
>
Fixes: 2d7adea4fe ("hw/sd: Support SDHC size cards")
> Signed-off-by: Bin Meng
> ---
>
> hw/sd/sd.c | 2 +-
> 1 file changed, 1
On Sat, Aug 15, 2020 at 9:42 AM Zhanghailiang
wrote:
>
> > -Original Message-
> > From: Derek Su [mailto:jwsu1...@gmail.com]
> > Sent: Thursday, August 13, 2020 6:28 PM
> > To: Lukas Straub
> > Cc: Derek Su ; qemu-devel@nongnu.org; Zhanghailiang
> > ; chy...@qnap.com;
On Sat, Aug 15, 2020 at 2:36 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/13/20 7:48 PM, Frank Chang wrote:
> > esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro:
> >
> >> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)\
> >> void HELPER(NAME)(void *vd, void * v0,
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana
> ---
> accel/stubs/Makefile.objs | 1 -
> accel/stubs/hvf-stub.c | 30 --
> include/sysemu/hvf.h | 8
> target/i386/hvf/hvf-cpus.h | 8
>
The changes to come to NUMA support are all guest visible. In
theory we could just create a new 5_1 class option flag to
avoid the changes to cascade to 5.1 and under. The reality is that
these changes are only relevant if the machine has more than one
NUMA node. There is no need to change guest
We have several places around hw/ppc files where we use the
same code to set the ibm,associativity array. This patch
creates a helper called spapr_set_associativity() to do
that in a single place. It'll also make it saner to change
the value of ibm,associativity in the next patches.
After this
Philippe Mathieu-Daudé 于2020年8月14日周五 下午4:34写道：
>
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
> ---
> hw/scsi/scsi-disk.c | 44 +++-
> 1 file changed, 23 insertions(+), 21
NVLink2 GPUs are allocated in their own NUMA node, at maximum
distance from every other resource in the board. The existing
logic makes some assumptions that don't scale well:
- only NVLink2 GPUs will ever require such mechanism, meaning
that the GPU logic is tightly coupled with the NUMA setup
On 8/14/20 6:40 PM, Bin Meng wrote:
> From: Bin Meng
>
> Microchip PolarFire SoC integrates one Cadence SDHCI controller.
> On the Icicle Kit board, one eMMC chip and an external SD card
> connect to this controller depending on different configuration.
>
> As QEMU does not support eMMC yet, we
Philippe Mathieu-Daudé 于2020年8月14日周五 下午4:30写道：
>
> Use self-explicit definitions instead of magic '512' value.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
> ---
> hw/ide/atapi.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git
The gvec operation was added after the initial implementation
of the SEL instruction and was missed in the conversion.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 31 ---
1 file changed, 8 insertions(+), 23 deletions(-)
diff --git
We can't use the input from machine->numa_state->nodes directly
in the pSeries machine because PAPR does not work with raw distance
values, like ACPI SLIT does. We need to determine common
associativity domains, based on similar performance/distance of the
resources, and set these domains in the
The existing clr functions have only one vector argument, and so
can only clear in place. The existing movz functions have two
vector arguments, and so can clear while moving. Merge them, with
a flag that controls the sense of active vs inactive elements
being cleared.
Signed-off-by: Richard
Rather than require the user to fill in the immediate (shl or shr),
create full formats that include the immediate.
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 35 ---
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 10
target/arm/translate-a64.c | 33 ++
target/arm/vec_helper.c| 48 ++
3 files changed, 81 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.h
This is v3 with no change w.r.t. v1/v2 (except this time you correctly
Cc'ed the maintainers). Maybe something is wrong in your setup?
On 8/15/20 5:12 PM, Rohit Shinde wrote:
> Added the fallthrough comment so that the compiler doesn't emit an error on
> compiling with the -Wimplicit-fallthrough
Add left-shift to match the existing right-shift.
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 5c9890db8b..76ea405922 100644
--- a/include/qemu/int128.h
+++
When you repost a patch, please add a version. This is patch v2.
Next (once you read my v1 comments) should be v3.
Watch out, v1 correctly Cc'ed the maintainers, this v2 doesn't.
On 8/15/20 5:11 PM, Rohit Shinde wrote:
> Added the fallthrough comment so that the compiler doesn't emit an error on
Hi Rohit,
Congratulation for your first patch! It is in very
good shape already :)
It is easier for the reviewers if you start the patch subject with
the name of the subsystem concerned, or the file modified:
"qapi/opts-visitor: Add missing fallthrough annotations"
On 8/15/20 3:00 PM, Rohit
apic_id contains all the information required to build CPUID_8000_001E.
Also remove the restriction on number bits on core_id and node_id.
Remove all the hardcoded values and replace with generalized
fields.
Refer the Processor Programming Reference (PPR) documentation
available from the bugzilla
Currently in 'megasas_map_sgl' when 'iov_count=0' will just return
success however the 'cmd' doens't contain any iov. This will cause
the assert in 'scsi_dma_complete' failed. This is because in
'dma_blk_cb' the 'dbs->sg_cur_index == dbs->sg->nsg' will be true
and just call 'dma_complete'. However
From: Cornelia Huck
Add 5.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 14 +-
hw/i386/pc_q35.c
On Fri, Aug 14, 2020 at 12:28:25PM -0700, Richard Henderson wrote:
> On 8/11/20 9:49 AM, Andrew Jones wrote:
> > Yes, except you need to drop the ARM_FEATURE_SPE define and use the ID
> > register bit instead like "sve_supported" does.
>
> On a related note, I think we have a latent bug, or at
Currently in 'megasas_map_sgl' when 'iov_count=0' will just return
success however the 'cmd' doens't contain any iov. This will cause
the assert in 'scsi_dma_complete' failed. This is because in
'dma_blk_cb' the 'dbs->sg_cur_index == dbs->sg->nsg' will be true
and just call 'dma_complete'. However
This patch puts all the pieces together to finally allow user
input when defining the NUMA topology of the spapr guest.
The logic is centered in the new spapr_init_numa_assoc_domains()
function. This is called once at machine_init(), if we're not
using legacy_numa mode, to initiate the
Added the fallthrough comment so that the compiler doesn't emit an error on
compiling with the -Wimplicit-fallthrough flag.
Signed-off-by: Rohit Shinde
---
qapi/opts-visitor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/qapi/opts-visitor.c b/qapi/opts-visitor.c
index
Patchew URL:
https://patchew.org/QEMU/20200815130046.5344-1-rohit.shinde12...@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
Added the fallthrough comment so that the compiler doesn't emit an error on
compiling with the -Wimplicit-fallthrough flag.
Signed-off-by: Rohit Shinde
---
qapi/opts-visitor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/qapi/opts-visitor.c b/qapi/opts-visitor.c
index
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> +static void generic_handle_interrupt(CPUState *cpu, int mask)
> +{
> +cpu->interrupt_request |= mask;
> +
> +if (!qemu_cpu_is_self(cpu)) {
> +qemu_cpu_kick(cpu);
> +}
> +}
> +
> +void cpu_interrupt(CPUState *cpu, int mask)
> +{
> +
Oh, sorry to forget to CC Alexander Bulekov.
Thanks,
Li Qiang
Li Qiang 于2020年8月15日周六 下午10:20写道：
>
> Currently in 'megasas_map_sgl' when 'iov_count=0' will just return
> success however the 'cmd' doens't contain any iov. This will cause
> the assert in 'scsi_dma_complete' failed. This is because
Wrote too much with low-half zip (zip1) with vl % 512 != 0.
Adjust all of the x + (y << s) to x | (y << s) as a style fix.
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 25 ++---
1 file changed, 14 insertions(+), 11
Remove node_id, nr_nodes and nodes_per_pkg from topology. Use
die_id, nr_dies and dies_per_pkg which is already available.
Removes the confusion over two variables.
With node_id removed in topology the uninitialized memory issue
with -device and CPU hotplug will be fixed.
Link:
This series fixes couple of issues with recent topology related code.
1. Modify AMD topology to use socket/dies/core/thread model
2. Error out if the user does not pass the dies information if EPYC cpu is numa
configured.
3. Remove the node_id references in topology and use die_id instead.
Update the EPYC topology to use socket/dies/core/thread model. The EPYC
model does not use the smp dies to build the topology. Instead, it uses
numa nodes to build the topology. Internally both are similar concept
which divides the cores on L3 boundary. Combining both into one terminology
makes it
Move the check for !S into do__flags, which allows to merge in
do_vecop4_p. Split out gen_gvec_fn_ppp without sve_access_check,
to mirror gen_gvec_fn_zzz.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 111 ++---
1 file changed, 43
On 8/12/20 11:32 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana
> ---
> accel/stubs/Makefile.objs | 1 -
> accel/stubs/whpx-stub.c | 47
> ---
> include/sysemu/whpx.h | 19 ---
> target/i386/whpx-cpus.h | 17
On 8/14/20 6:40 PM, Bin Meng wrote:
> From: Bin Meng
>
> Connect a DMA controller to Microchip PolarFire SoC. Note interrupt
> has not been connected due to missing information in the manual how
> interrupts are routed to PLIC.
>
> On the Icicle Kit board, the HSS firmware utilizes the on-chip
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