Re: Contributor wanting to get started with simple contributions

Hey John, Sorry to bother you! I just wanted to know if you had any thoughts on the mail I sent. Is there anything I can pick up right now with regards to the Python package? You mentioned that linting is something that needs to be completed before we go ahead, so maybe I can start with that?

Re: [RFC PATCH v3 00/34] Hexagon patch series

On 8/18/20 8:50 AM, Taylor Simpson wrote: > This series adds support for the Hexagon processor with Linux user support > > See patch 02/34 Hexagon README for detailed information. > > Once the series is applied, the Hexagon port will pass "make check-tcg". > The series also includes

Re: [RFC PATCH v3 34/34] Hexagon build infrastructure

On 8/18/20 8:50 AM, Taylor Simpson wrote: > Add file to default-configs > Change configure > Add target/hexagon/Makefile.objs > Change scripts/qemu-binfmt-conf.sh > > We can build a hexagon-linux-user target and run programs on the Hexagon > scalar core. With hexagon-linux-clang installed, "make

Re: [RFC PATCH v3 33/34] Hexagon (tests/tcg/hexagon) TCG tests

On 8/18/20 8:50 AM, Taylor Simpson wrote: > Modify tests/tcg/configure.sh > Add reference files to tests/tcg/hexagon > Add Hexagon-specific tests > > Signed-off-by: Taylor Simpson > --- Looks ok. Could you please work with Alex Bennee to set up a tests/docker/dockerfile/ script containing the

Re: [RFC PATCH v3 32/34] Hexagon (linux-user/hexagon) Linux user emulation

On 8/18/20 8:50 AM, Taylor Simpson wrote: > Implementation of Linux user emulation for Hexagon > Some common files modified in addition to new files in linux-user/hexagon > > Signed-off-by: Taylor Simpson > --- Looks plausible. Reviewed-by: Richard Henderson r~

Re: [RFC PATCH v3 31/34] Hexagon (target/hexagon) translation

On 8/18/20 8:50 AM, Taylor Simpson wrote: > Read the instruction memory > Create a packet data structure > Generate TCG code for the start of the packet > Invoke the generate function for each instruction > Generate TCG code for the end of the packet > > Signed-off-by: Taylor Simpson > --- >

[PATCH v6 07/12] migration/dirtyrate: Compare page hash results for recorded sampled page

Compare page hash results for recorded sampled page. Signed-off-by: Chuan Zheng Signed-off-by: YanYing Zhuang --- migration/dirtyrate.c | 63 +++ 1 file changed, 63 insertions(+) diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c index

[PATCH v6 12/12] migration/dirtyrate: Add trace_calls to make it easier to debug

Add trace_calls to make it easier to debug Signed-off-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert --- migration/dirtyrate.c | 9 + migration/trace-events | 8 2 files changed, 17 insertions(+) diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c index

[PATCH v6 10/12] migration/dirtyrate: Implement calculate_dirtyrate() function

Implement calculate_dirtyrate() function. Signed-off-by: Chuan Zheng Signed-off-by: YanYing Zhuang --- migration/dirtyrate.c | 45 +++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c index

[PATCH v6 03/12] migration/dirtyrate: Add RamblockDirtyInfo to store sampled page info

Add RamblockDirtyInfo to store sampled page info of each ramblock. Signed-off-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert --- migration/dirtyrate.h | 18 ++ 1 file changed, 18 insertions(+) diff --git a/migration/dirtyrate.h b/migration/dirtyrate.h index

[PATCH v6 11/12] migration/dirtyrate: Implement qmp_cal_dirty_rate()/qmp_get_dirty_rate() function

Implement qmp_cal_dirty_rate()/qmp_get_dirty_rate() function which could be called Signed-off-by: Chuan Zheng --- migration/dirtyrate.c | 62 +++ qapi/migration.json | 50 + 2 files changed, 112

[PATCH v6 09/12] migration/dirtyrate: Implement set_sample_page_period() and get_sample_page_period()

Implement set_sample_page_period()/get_sample_page_period() to sleep specific time between sample actions. Signed-off-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert --- migration/dirtyrate.c | 24 migration/dirtyrate.h | 6 ++ 2 files changed, 30

[PATCH v6 06/12] migration/dirtyrate: Record hash results for each sampled page

Record hash results for each sampled page, crc32 is taken to calculate hash results for each sampled length in TARGET_PAGE_SIZE. Signed-off-by: Chuan Zheng Signed-off-by: YanYing Zhuang --- migration/dirtyrate.c | 125 ++ 1 file changed, 125

[PATCH v6 04/12] migration/dirtyrate: Add dirtyrate statistics series functions

Add dirtyrate statistics functions to record/update dirtyrate info. Signed-off-by: Chuan Zheng --- migration/dirtyrate.c | 32 migration/dirtyrate.h | 12 2 files changed, 44 insertions(+) diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c

[PATCH v6 05/12] migration/dirtyrate: move RAMBLOCK_FOREACH_MIGRATABLE into ram.h

RAMBLOCK_FOREACH_MIGRATABLE is need in dirtyrate measure, move the existing definition up into migration/ram.h Signed-off-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert --- migration/dirtyrate.c | 1 + migration/ram.c | 11 +-- migration/ram.h | 10 ++ 3 files

[PATCH v6 02/12] migration/dirtyrate: add DirtyRateStatus to denote calculation status

add DirtyRateStatus to denote calculating status. Signed-off-by: Chuan Zheng Reviewed-by: Dr. David Alan Gilbert --- migration/dirtyrate.c | 22 ++ qapi/migration.json | 17 + 2 files changed, 39 insertions(+) diff --git a/migration/dirtyrate.c

[PATCH v6 00/12] *** A Method for evaluating dirty page rate ***

v5 -> v6: fix coding style according to review use TARGET_PAGE_SIZE and TARGET_PAGE_BITS instead of self-defined macros return start-time and calc-time by qmp command v4 -> v5: fix git apply failed due to meson-build add review-by for patches in v3 v3 -> v4: use crc32 to

[PATCH v6 01/12] migration/dirtyrate: setup up query-dirtyrate framwork

Add get_dirtyrate_thread() functions to setup query-dirtyrate framework. Signed-off-by: Chuan Zheng Signed-off-by: YanYing Zhuang Reviewed-by: Dr. David Alan Gilbert --- migration/dirtyrate.c | 38 ++ migration/dirtyrate.h | 29 +

[PATCH v6 08/12] migration/dirtyrate: skip sampling ramblock with size below MIN_RAMBLOCK_SIZE

In order to sample real RAM, skip ramblock with size below MIN_RAMBLOCK_SIZE which is set as 128M. Signed-off-by: Chuan Zheng --- migration/dirtyrate.c | 19 +++ migration/dirtyrate.h | 5 + 2 files changed, 24 insertions(+) diff --git a/migration/dirtyrate.c

Re: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

On 8/18/20 8:50 AM, Taylor Simpson wrote: > +++ b/target/hexagon/helper.h > @@ -15,6 +15,8 @@ > * along with this program; if not, see . > */ > > +#include "gen_tcg.h" Why would you need this here? Definitely looks wrong. r~

Re: [RFC PATCH v3 29/34] Hexagon (target/hexagon) TCG generation

On 8/18/20 8:50 AM, Taylor Simpson wrote: > +/* Fill in the table with NULLs because not all the opcodes have DEF_QEMU */ > +semantic_insn_t opcode_genptr[] = { > +#define OPCODE(X) NULL > +#include "opcodes_def_generated.h" > +NULL > +#undef OPCODE > +}; > + > +/*

Re: [RFC PATCH v3 28/34] Hexagon (target/hexagon) TCG generation helpers

On 8/18/20 8:50 AM, Taylor Simpson wrote: > Helpers for reading and writing registers > Helpers for load-locked/store-conditional > > Signed-off-by: Taylor Simpson > --- > target/hexagon/genptr_helpers.h | 244 > > target/hexagon/op_helper.c | 18

Re: [RFC PATCH v3 27/34] Hexagon (target/hexagon) instruction classes

On 8/18/20 8:50 AM, Taylor Simpson wrote: > +} iclass_t; ... > +extern const char *find_iclass_slots(opcode_t opcode, int itype); ... > +typedef struct { > +const char * const slots; > +} iclass_info_t; I'll note that you aren't following our CODING_STYLE for types. Which of these need to

Re: [RFC PATCH v3 26/34] Hexagon (target/hexagon) macros referenced in instruction semantics

On 8/18/20 8:50 AM, Taylor Simpson wrote: > +/* > + * Section 5.5 of the Hexagon V67 Programmer's Reference Manual > + * > + * Slot 1 store with slot 0 load > + * A slot 1 store operation with a slot 0 load operation can appear in a > packet. > + * The packet attribute :mem_noshuf inhibits the

Re: [RFC PATCH v3 25/34] Hexagon (target/hexagon) macros to interface with the generator

On 8/18/20 8:50 AM, Taylor Simpson wrote: > +#define DECL_REG(NAME, NUM, X, OFF) \ > +TCGv NAME = tcg_temp_local_new(); \ > +int NUM = REGNO(X) + OFF > + > +#define DECL_REG_WRITABLE(NAME, NUM, X, OFF) \ > +TCGv NAME = tcg_temp_local_new(); \ > +int NUM = REGNO(X) + OFF; \ > +

QEMU | Pipeline #183317910 has failed for master | 39335fab

Your pipeline has failed. Project: QEMU ( https://gitlab.com/qemu-project/qemu ) Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master ) Commit: 39335fab ( https://gitlab.com/qemu-project/qemu/-/commit/39335fab59e11cfda9b7cf63929825db2dd3a3e0 ) Commit Message: Merge

Re: [PATCH v2 44/45] target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon floating-point VMUL, VMLA and VMLS to use gvec, > and use this to implement fp16 support. > > Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson > +/* a->vm is M:Vm, which encodes both register and index */ > +idx =

[PATCH v3 5/5] qemu-iotests: Simplify FilePath __init__

Use list comprehension instead of append loop. Signed-off-by: Nir Soffer Reviewed-by: Max Reitz --- tests/qemu-iotests/iotests.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 7a20c9..cd0abf37e5

[PATCH v3 4/5] qemu-iotests: Merge FilePaths and FilePath

FilePath creates now one temporary file: with FilePath("a") as a: Or more: with FilePath("a", "b", "c") as (a, b, c): This is also the behavior of the file_path() helper, used by some of the tests. Now we have only 2 helpers for creating temporary files instead of 3. Signed-off-by:

Re: [PATCH v2 43/45] target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations

On 8/28/20 11:33 AM, Peter Maydell wrote: > +#define float16_nop(N, M, S) (M) > +#define float32_nop(N, M, S) (M) > +#define float64_nop(N, M, S) (M) > > +DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16, H2) > +DO_FMUL_IDX(gvec_fmul_idx_s, nop, float32, H4) > +DO_FMUL_IDX(gvec_fmul_idx_d, nop,

[PATCH v3 3/5] qemu-iotests: Support varargs syntax in FilePaths

Accept variable number of names instead of a sequence: with FilePaths("a", "b", "c") as (a, b, c): The disadvantage is that base_dir must be used as kwarg: with FilePaths("a", "b", base_dir=soc_dir) as (sock1, sock2): But this is more clear and calling optional argument as positional

[PATCH v3 2/5] qemu-iotests: Fix FilePaths docstring

When this class was extracted from FilePath, the docstring was not updated for generating multiple files, and the example usage was referencing unrelated file. While fixing the docstring, add example for creating sockets, which should use iotests.sock_dir instead of the default base_dir. Fixes:

[PATCH v3 1/5] qemu-iotests: Fix FilePaths cleanup

If os.remove() fails to remove one of the paths, for example if the file was removed by the test, the cleanup loop would exit silently, without removing the rest of the files. Fixes: de263986b5dc Signed-off-by: Nir Soffer Reviewed-by: Max Reitz --- tests/qemu-iotests/iotests.py | 8 1

[PATCH v3 0/5] iotest.FilePath fixes and cleanups

Fix some issues introduced when iotests.FilePaths was added and merge it back into FilePath keeping the option to create multiple file names. Changes since v2: - Improve dosting to show how sockets should be created [Max] v2 was here:

Re: [PATCH v2 42/45] target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations

On 8/28/20 11:33 AM, Peter Maydell wrote: > In the gvec helper functions for indexed operations, for AArch32 > Neon the oprsz (total size of the vector) can be less than 16 bytes > if the operation is on a D reg. Since the inner loop in these > helpers always goes from 0 to segment, we must clamp

Re: [PATCH v2 41/45] target/arm: Implement fp16 for Neon VRINTX

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon VRINTX insn to use gvec, and use this to implement > fp16 support for it. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 3 +++ > target/arm/vec_helper.c | 3 +++ > target/arm/translate-neon.c.inc

Re: [PATCH v2 40/45] target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon VRINT-with-specified-rounding-mode insns to gvec, > and use this to implement the fp16 versions. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 4 +- > target/arm/vec_helper.c | 21 +++ >

Re: [PATCH v2 39/45] target/arm: Implement fp16 for Neon VCVT with rounding modes

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon VCVT with-specified-rounding-mode instructions > to gvec, and use this to implement fp16 support for them. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 5 ++ > target/arm/vec_helper.c | 23

Re: [PATCH v2 38/45] target/arm: Implement fp16 for Neon VCVT fixed-point

On 8/28/20 11:33 AM, Peter Maydell wrote: > Implement fp16 for the Neon VCVT insns which convert between > float and fixed-point. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 5 + > target/arm/neon-dp.decode | 8 +++- > target/arm/vec_helper.c

Re: [PATCH v2 37/45] target/arm: Convert Neon VCVT fixed-point to gvec

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon VCVT float<->fixed-point insns to a > gvec style, in preparation for adding fp16 support. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 5 + > target/arm/vec_helper.c | 20 +++

Re: [PATCH v2 36/45] target/arm: Implement fp16 for Neon float-integer VCVT

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon float-integer VCVT insns to gvec, and use this > to implement fp16 support for them. > > Note that unlike the VFP int<->fp16 VCVT insns we converted > earlier and which convert to/from a 32-bit integer, these > Neon insns convert

Re: [PATCH v2 35/45] target/arm: Implement fp16 for Neon pairwise fp ops

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon pairwise fp ops to use a single gvic-style > helper to do the full operation instead of one helper call > for each 32-bit part. This allows us to use the same > framework to implement the fp16. > > Signed-off-by: Peter Maydell > --- >

Re: [PULL 00/18] Linux user for 5.2 patches

On Fri, 28 Aug 2020 at 14:39, Laurent Vivier wrote: > > The following changes since commit 25f6dc28a3a8dd231c2c092a0e65bd796353c769: > > Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-08-26' = > into staging (2020-08-26 10:28:36 +0100) > > are available in the Git

Re: [PATCH v2 34/45] target/arm: Implement fp16 for Neon VRSQRTS

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon VRSQRTS insn to using a gvec helper, > and use this to implement the fp16 case. > > As with VRECPS, we adjust the phrasing of the new implementation > slightly so that the fp32 version parallels the fp16 one. > > Signed-off-by: Peter

Re: [PATCH v2 33/45] target/arm: Implement fp16 for Neon VRECPS

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon VRECPS insn to using a gvec helper, and > use this to implement the fp16 case. > > The phrasing of the new float32_recps_nf() is slightly different from > the old recps_f32() so that it parallels the f16 version; for f16 we > can't

Re: [PATCH 16/20] target/arm: Fix sve_zip_p vs odd vector lengths

On Fri, 28 Aug 2020 at 20:26, Richard Henderson wrote: > > On 8/25/20 6:49 AM, Peter Maydell wrote: > > Why is it OK to only check vd==vn etc rather than checking for > > overlap the way the old code did ? The commit message doesn't > > mention this. > > We only ever pass pred_full_reg_offset, so

QEMU | Pipeline #183302307 has failed for master | a4e236b7

Your pipeline has failed. Project: QEMU ( https://gitlab.com/qemu-project/qemu ) Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master ) Commit: a4e236b7 ( https://gitlab.com/qemu-project/qemu/-/commit/a4e236b7d4badcd7383ed3cb86655e9bba0583cf ) Commit Message: Merge

Re: [PATCH v2 32/45] target/arm: Implement fp16 for Neon fp compare-vs-0

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the neon floating-point vector compare-vs-0 insns VCEQ0, > VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to > implement the fp16 case. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 15

Re: [PATCH v2 31/45] target/arm: Implement fp16 for Neon VFMA, VMFS

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the neon floating-point vector operations VFMA and VFMS > to use a gvec helper, and use this to implement the fp16 case. > > This is the last use of do_3same_fp() so we can now delete > that function. > > Signed-off-by: Peter Maydell > --- >

Re: [PATCH v2 24/45] target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec

On 8/28/20 2:40 PM, Peter Maydell wrote: > The other approach would be to standardize on "the decodetree pattern > always converts the size to the data-type size, regardless of how > it's encoded in the insn fields", and then you could check against > MO_16 here. Would that be better ? That might

Re: [PATCH v2 24/45] target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec

On Fri, 28 Aug 2020 at 21:10, Richard Henderson wrote: > > On 8/28/20 11:33 AM, Peter Maydell wrote: > > We already have gvec helpers for floating point VRECPE and > > VRQSRTE, so convert the Neon decoder to use them and > > add the fp16 support. > > > > Signed-off-by: Peter Maydell > > --- > >

[REPORT] Nightly Performance Tests - Friday, August 28, 2020

Host CPU : Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz Host Memory : 15.49 GB Start Time (UTC) : 2020-08-28 21:30:02 End Time (UTC) : 2020-08-28 21:35:21 Execution Time : 0:05:18.871569 Status : FAILURE

Re: [PATCH v3] virtio-rng: return available data with O_NONBLOCK

On Wed, 2020-08-26 at 08:26 -0400, Michael S. Tsirkin wrote: > On Tue, Aug 11, 2020 at 04:42:32PM +0200, Laurent Vivier wrote: > > On 11/08/2020 16:28, mwi...@suse.com wrote: > > > From: Martin Wilck > > > > > > If a program opens /dev/hwrng with O_NONBLOCK and uses poll() and > > > non-blocking

Re: [PATCH] meson: move zlib detection to meson

Il ven 28 ago 2020, 23:13 罗勇刚(Yonggang Luo) ha scritto: > - --disable-zlib-test) zlib="no" >> + --disable-zlib-test) >> > Why not remove this no-op > Because I did not want to introduce visible changes. Paolo

Re: [PULL 0/8] migration and virtiofsd queue

On Fri, 28 Aug 2020 at 13:47, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > The following changes since commit 3e39dac0354c39b4b647940e42360c6b1f3edc02: > > Merge remote-tracking branch > 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2020-08-28

Re: [PATCH] meson: move zlib detection to meson

On Sat, Aug 29, 2020 at 1:39 AM Paolo Bonzini wrote: > Meson includes the same logic that tries to look for -lz if > pkg-config (and cmake) cannot find zlib. The undocumented > --disable-zlib-test option becomes a no-op. > > Signed-off-by: Paolo Bonzini > --- > Makefile| 2 +- >

[Bug 1823790] Re: QEMU mishandling of SO_PEERSEC forces systemd into tight loop

Could you try the attached patch? ** Patch added: "SO_PEERGROUPS.patch" https://bugs.launchpad.net/qemu/+bug/1823790/+attachment/5405549/+files/SO_PEERGROUPS.patch -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

Re: [PATCH v2 30/45] target/arm: Implement fp16 for Neon VMLA, VMLS operations

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon floating-point VMLA and VMLS insns over to using a > gvec helper, and use this to implement the fp16 case. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 6 + > target/arm/vec_helper.c | 42

Re: [PATCH v2 29/45] target/arm: Implement fp16 for Neon VMAXNM, VMINNM

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon floating point VMAXNM and VMINNM insns to > using a gvec helper and use this to implement the fp16 case. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 6 ++ > target/arm/vec_helper.c | 6

Re: [PATCH v2 28/45] target/arm: Implement fp16 for Neon VMAX, VMIN

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon float-point VMAX and VMIN insns over to using > a gvec helper, and use this to implement the fp16 case. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 6 ++ > target/arm/vec_helper.c | 6 ++

Re: [PATCH v2 27/45] target/arm: Implement fp16 for VACGE, VACGT

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the neon floating-point vector absolute comparison ops > VACGE and VACGT over to using a gvec hepler and use this to > implement the fp16 case. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.h | 6 ++ >

Re: [PATCH v2 26/45] target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons

On 8/28/20 11:33 AM, Peter Maydell wrote: > Convert the Neon floating-point vector comparison ops VCEQ, > VCGE and VCGT over to using a gvec helper and use this to > implement the fp16 case. > > (We put the float16_ceq() etc functions above the DO_2OP() > macro definition because later when we

Re: [PATCH v2 25/45] target/arm: Implement fp16 for Neon VABS, VNEG of floats

On 8/28/20 11:33 AM, Peter Maydell wrote: > Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so > that we can implement the fp16 version of the insns. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-neon.c.inc | 34 +++-- > 1 file

Re: [PATCH v1 2/2] target/microblaze: Improve transaction failure handling

On 8/28/20 4:39 AM, Edgar E. Iglesias wrote: > +if ((access_type == MMU_INST_FETCH && cpu->cfg.iopb_bus_exception) || > +(access_type != MMU_INST_FETCH && cpu->cfg.dopb_bus_exception)) { > +cpu_restore_state(cs, retaddr, true); > +env->sregs[SR_ESR] = access_type ==

[Bug 1823790] Re: QEMU mishandling of SO_PEERSEC forces systemd into tight loop

SO_PEERGROUPS is not implemented and processed as an "int" (this explains the ERANGE) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1823790 Title: QEMU mishandling of SO_PEERSEC forces systemd

Re: [PATCH v2 24/45] target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec

On 8/28/20 11:33 AM, Peter Maydell wrote: > We already have gvec helpers for floating point VRECPE and > VRQSRTE, so convert the Neon decoder to use them and > add the fp16 support. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-neon.c.inc | 29 +++-- > 1

Re: [PATCH v2 23/45] target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL

On 8/28/20 11:33 AM, Peter Maydell wrote: > Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC > macro: VADD, VSUB, VABD, VMUL. > > For VABD this requires us to implement a new gvec_fabd_h helper > using the machinery we have already for the other helpers. > > Signed-off-by:

Re: [PATCH v2 22/45] fpu: Add float16 comparison functions

On 8/28/20 11:33 AM, Peter Maydell wrote: > Add comparison functions for float16 to match the existing float32 > and float64 ones: > > float16_eq() > float16_le() > float16_lt() > float16_unordered() > float16_eq_quiet() > float16_le_quiet() > float16_lt_quiet() >

Re: [Fwd] Issue 25164 in oss-fuzz: qemu: Fuzzing build failure

On 28/08/20 20:33, Alexander Bulekov wrote: >> Create a fuzz.cmd that includes the correct path to fuzz.ld in the >> source tree (using configure_file) and pass this file to the linker >> using @tests/libqtest/fuzz/fuzz.cmd in link_args (and also >> link_depends). See libblock and block for an

[PATCH v4 2/7] usb/hcd-xhci: Move qemu-xhci device to hcd-xhci-pci.c

Move pci specific devices to new file. This set the environment to move all pci specific hooks in hcd-xhci.c to hcd-xhci-pci.c. Signed-off-by: Sai Pavan Boddu --- hw/usb/Kconfig| 6 + hw/usb/Makefile.objs | 1 + hw/usb/hcd-xhci-pci.c | 66

[PATCH v4 0/7] Make hcd-xhci independent of pci hooks

This patch series attempts to make 'hcd-xhci' an independent model so it can be used by both pci and system-bus interface. Changes for V2: Make XHCIState non-qom Use container_of functions for retriving pci device instance Initialize the AddressSpace pointer in PATCH 1/3 itself

[PATCH v4 4/7] usb: hcd-xhci-sysbus: Attach xhci to sysbus device

Use XHCI as sysbus device, add memory region property to get the address space instance for dma read/write. Signed-off-by: Sai Pavan Boddu --- hw/usb/Kconfig | 5 +++ hw/usb/Makefile.objs | 1 + hw/usb/hcd-xhci-sysbus.c | 99

[PATCH v4 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

This patch starts making the hcd-xhci.c pci free, as part of this restructuring dma read/writes are handled without passing pci object. Signed-off-by: Sai Pavan Boddu --- hw/usb/hcd-xhci.c | 24 +++- hw/usb/hcd-xhci.h | 3 +++ 2 files changed, 14 insertions(+), 13

Re: [PATCH 16/20] target/arm: Fix sve_zip_p vs odd vector lengths

On 8/25/20 6:49 AM, Peter Maydell wrote: > On Sat, 15 Aug 2020 at 02:32, Richard Henderson > wrote: >> >> Wrote too much with low-half zip (zip1) with vl % 512 != 0. >> >> Adjust all of the x + (y << s) to x | (y << s) as a style fix. >> >> Reported-by: Laurent Desnogues >> Signed-off-by:

[PATCH v4 3/7] usb/hcd-xhci: Split pci wrapper for xhci base model

This patch sets the base to use xhci as sysbus model, for which pci specific hooks are moved to hcd-xhci-pci.c. As a part of this requirment msi/msix interrupts handling is moved under XHCIPCIState. Made required changes for qemu-xhci-nec. Signed-off-by: Sai Pavan Boddu ---

[PATCH v4 7/7] Versal: Connect DWC3 controller with virt-versal

From: Vikram Garhwal Connect dwc3 controller and usb2-reg module to virt-versal. Configure it as dual port host controller. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu --- hw/arm/xlnx-versal-virt.c| 59 hw/arm/xlnx-versal.c

[PATCH v4 5/7] misc: Add versal-usb2-regs module

This is a dummy module to emulate control registers of versal usb2 controller. Signed-off-by: Sai Pavan Boddu Signed-off-by: Vikram Garhwal --- hw/misc/Makefile.objs | 1 + hw/misc/xlnx-versal-usb2-regs.c | 224

[PATCH v4 6/7] usb: Add DWC3 model

From: Vikram Garhwal This patch adds skeleton model of dwc3 usb controller attached to xhci-sysbus device. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu --- hw/usb/Makefile.objs | 1 + hw/usb/hcd-dwc3.c | 606 ++

Re: [PATCH] ninjatool: quote dollars in variables

Le 27/08/2020 à 11:14, Paolo Bonzini a écrit : > ... and actually it's fixed in 0.55.1. We can therefore just update the > submodule and declare 0.55.1 the minimum required version for QEMU. > Updating the meson submodule to 0.55.1 has fixed the problem for me. Thanks, Laurent

Re: [PATCH v1 2/2] target/microblaze: Improve transaction failure handling

On Fri, Aug 28, 2020 at 4:41 AM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > When the CPU has exceptions disabled, avoid unwinding CPU > state and clobbering registers if we're not going to raise > any exception. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis

QEMU | Pipeline #183242166 has failed for master | ea1bb830

Your pipeline has failed. Project: QEMU ( https://gitlab.com/qemu-project/qemu ) Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master ) Commit: ea1bb830 ( https://gitlab.com/qemu-project/qemu/-/commit/ea1bb830cb021cca2e361091cf728aaabc8c0654 ) Commit Message: Merge

[PATCH v2 38/45] target/arm: Implement fp16 for Neon VCVT fixed-point

Implement fp16 for the Neon VCVT insns which convert between float and fixed-point. Signed-off-by: Peter Maydell --- target/arm/helper.h | 5 + target/arm/neon-dp.decode | 8 +++- target/arm/vec_helper.c | 4 target/arm/translate-neon.c.inc | 5 + 4

Re: [PATCH v1 1/2] target/microblaze: Use CPU properties to conditionalize bus exceptions

On Fri, Aug 28, 2020 at 4:41 AM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Use CPU properties, instead of PVR fields, to conditionalize > bus exceptions. > > Fixes: 2867a96ffb ("target/microblaze: Add props enabling exceptions on > failed bus accesses") > Signed-off-by: Edgar E.

[PATCH v2 37/45] target/arm: Convert Neon VCVT fixed-point to gvec

Convert the Neon VCVT float<->fixed-point insns to a gvec style, in preparation for adding fp16 support. Signed-off-by: Peter Maydell --- target/arm/helper.h | 5 + target/arm/vec_helper.c | 20 +++ target/arm/translate-neon.c.inc | 35

[PATCH v2 40/45] target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode

Convert the Neon VRINT-with-specified-rounding-mode insns to gvec, and use this to implement the fp16 versions. Signed-off-by: Peter Maydell --- target/arm/helper.h | 4 +- target/arm/vec_helper.c | 21 +++ target/arm/vfp_helper.c | 17 -

[PATCH v2 33/45] target/arm: Implement fp16 for Neon VRECPS

Convert the Neon VRECPS insn to using a gvec helper, and use this to implement the fp16 case. The phrasing of the new float32_recps_nf() is slightly different from the old recps_f32() so that it parallels the f16 version; for f16 we can't assume that flush-to-zero is always enabled.

[PATCH v2 39/45] target/arm: Implement fp16 for Neon VCVT with rounding modes

Convert the Neon VCVT with-specified-rounding-mode instructions to gvec, and use this to implement fp16 support for them. Signed-off-by: Peter Maydell --- target/arm/helper.h | 5 ++ target/arm/vec_helper.c | 23 +++ target/arm/translate-neon.c.inc | 103

[PATCH v2 45/45] target/arm: Enable FP16 in '-cpu max'

Set the MVFR1 ID register FPHP and SIMDHP fields to indicate that our "-cpu max" has v8.2-FP16. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 10 -- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git

[PATCH v2 32/45] target/arm: Implement fp16 for Neon fp compare-vs-0

Convert the neon floating-point vector compare-vs-0 insns VCEQ0, VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell --- target/arm/helper.h | 15 +++ target/arm/vec_helper.c | 25

[PATCH v2 30/45] target/arm: Implement fp16 for Neon VMLA, VMLS operations

Convert the Neon floating-point VMLA and VMLS insns over to using a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell --- target/arm/helper.h | 6 + target/arm/vec_helper.c | 42 +

[PATCH v2 44/45] target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS

Convert the Neon floating-point VMUL, VMLA and VMLS to use gvec, and use this to implement fp16 support. Signed-off-by: Peter Maydell --- target/arm/translate-neon.c.inc | 114 1 file changed, 57 insertions(+), 57 deletions(-) diff --git

[PATCH v2 29/45] target/arm: Implement fp16 for Neon VMAXNM, VMINNM

Convert the Neon floating point VMAXNM and VMINNM insns to using a gvec helper and use this to implement the fp16 case. Signed-off-by: Peter Maydell --- target/arm/helper.h | 6 ++ target/arm/vec_helper.c | 6 ++ target/arm/translate-neon.c.inc | 23

[PATCH v2 27/45] target/arm: Implement fp16 for VACGE, VACGT

Convert the neon floating-point vector absolute comparison ops VACGE and VACGT over to using a gvec hepler and use this to implement the fp16 case. Signed-off-by: Peter Maydell --- target/arm/helper.h | 6 ++ target/arm/vec_helper.c | 26 ++

[PATCH v2 42/45] target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations

In the gvec helper functions for indexed operations, for AArch32 Neon the oprsz (total size of the vector) can be less than 16 bytes if the operation is on a D reg. Since the inner loop in these helpers always goes from 0 to segment, we must clamp it based on oprsz to avoid processing a full 16

[PATCH v2 28/45] target/arm: Implement fp16 for Neon VMAX, VMIN

Convert the Neon float-point VMAX and VMIN insns over to using a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell --- target/arm/helper.h | 6 ++ target/arm/vec_helper.c | 6 ++ target/arm/translate-neon.c.inc | 5 ++--- 3 files

[PATCH v2 36/45] target/arm: Implement fp16 for Neon float-integer VCVT

Convert the Neon float-integer VCVT insns to gvec, and use this to implement fp16 support for them. Note that unlike the VFP int<->fp16 VCVT insns we converted earlier and which convert to/from a 32-bit integer, these Neon insns convert to/from 16-bit integers. So we can use the existing vfp

[PATCH v2 26/45] target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons

Convert the Neon floating-point vector comparison ops VCEQ, VCGE and VCGT over to using a gvec helper and use this to implement the fp16 case. (We put the float16_ceq() etc functions above the DO_2OP() macro definition because later when we convert the compare-against-zero instructions we'll want

[PATCH v2 43/45] target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations

Add gvec helpers for doing Neon-style indexed non-fused fp multiply-and-accumulate operations. Signed-off-by: Peter Maydell --- target/arm/helper.h | 10 ++ target/arm/vec_helper.c | 27 ++- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git

[PATCH v2 35/45] target/arm: Implement fp16 for Neon pairwise fp ops

Convert the Neon pairwise fp ops to use a single gvic-style helper to do the full operation instead of one helper call for each 32-bit part. This allows us to use the same framework to implement the fp16. Signed-off-by: Peter Maydell --- target/arm/helper.h | 7 +

[PATCH v2 21/45] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers

Implement the VFP fp16 variant of VMOV that transfers a 16-bit value between a general purpose register and a VFP register. Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later only we have no need to replicate the old "updates CPSR.NZCV" behaviour that the singleprec version of

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