> -Original Message-
> From: Jason Wang
> Sent: Tuesday, January 5, 2021 12:17 PM
> To: Zhang, Chen ; qemu-dev de...@nongnu.org>; Eric Blake ; Dr. David Alan
> Gilbert ; Markus Armbruster
> Cc: Zhang Chen
> Subject: Re: [PATCH 1/3] qapi/net: Add new QMP command for COLO
> passthrough
+Alistair Francis
On Sat, Dec 19, 2020 at 8:24 AM Vitaly Wool wrote:
>
> Add command line parameter to microchip_pfsoc machine to be able
> to specify XIP kernel image file. To pass over XIP image file, it
> will be enough to run
>
> $ qemu-system-riscv64 -M microchip-icicle-kit,xipImage= ...
>
>
Guarding MAP_JIT with
if (!splitwx) {
flags |= MAP_JIT;
}
is better because MAP_JIT tells the kernel that we want a RWX mapping
which is not the case. On iOS, special entitlements are needed for
MAP_JIT.
-j
On Mon, Dec 14, 2020 at 6:03 AM Richard Henderson
wrote:
>
> Cribbed from code post
On Wed, Dec 16, 2020 at 06:07:58AM -0300, Gustavo Romero wrote:
> From: Michael Roth
>
> Some prefixed instructions (Type 0 and 1, e.g. 8-byte Load/Store or 8LS),
> have a completely seperate namespace for their primary opcodes.
>
> Other prefixed instructions (Type 2 and 3, e.g. Modified Load/S
[Expired for btrfs-progs (Ubuntu) because there has been no activity for
60 days.]
** Changed in: btrfs-progs (Ubuntu)
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bu
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1877418
Title:
qemu-nbd fr
On 2021/1/5 上午11:28, Zhang, Chen wrote:
-Original Message-
From: Jason Wang
Sent: Wednesday, December 30, 2020 11:57 AM
To: Zhang, Chen ; qemu-dev ; Eric Blake ; Dr. David Alan
Gilbert ; Markus Armbruster
Cc: Zhang Chen
Subject: Re: [PATCH 1/3] qapi/net: Add new QMP command for COL
On Wed, Dec 23, 2020 at 2:26 PM Bin Meng wrote:
>
> From: Bin Meng
>
> U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
> in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
> bandgap has stabilized.
>
> With this change, the latest upstream U-Boot (v2021.01-rc3)
On Wed, Dec 23, 2020 at 10:00 AM Bin Meng wrote:
>
> From: Bin Meng
>
> When write is disabled, the write to flash should be avoided
> in flash_write8().
>
> Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
> Signed-off-by: Bin Meng
> Reviewed-by: Philippe Mathieu-Daudé
On Tue, Jan 5, 2021 at 11:46 AM Bin Meng wrote:
>
> Hello,
>
> On Tue, Dec 22, 2020 at 2:45 PM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > When write is disabled, the write to flash should be avoided
> > in flash_write8().
> >
> > Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI fl
Hello,
On Tue, Dec 22, 2020 at 2:45 PM Bin Meng wrote:
>
> From: Bin Meng
>
> When write is disabled, the write to flash should be avoided
> in flash_write8().
>
> Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
> Signed-off-by: Bin Meng
>
> ---
>
> (no changes since
> -Original Message-
> From: Dr. David Alan Gilbert
> Sent: Monday, January 4, 2021 9:07 PM
> To: Zhang, Chen
> Cc: Jason Wang ; qemu-dev de...@nongnu.org>; Eric Blake ; Markus Armbruster
> ; Zhang Chen
> Subject: Re: [PATCH 0/3] Bypass specific network traffic in COLO
>
> * Zhang C
> -Original Message-
> From: Jason Wang
> Sent: Wednesday, December 30, 2020 11:57 AM
> To: Zhang, Chen ; qemu-dev de...@nongnu.org>; Eric Blake ; Dr. David Alan
> Gilbert ; Markus Armbruster
> Cc: Zhang Chen
> Subject: Re: [PATCH 1/3] qapi/net: Add new QMP command for COLO
> passthro
On Fri, Dec 18, 2020 at 5:48 AM Atish Patra wrote:
>
> Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
> lesser. However, Linux kernel can address only 1GB of memory for RV32.
> Thus, it can not map anything beyond 3GB (assuming 2GB is the starting
> address).
> As a resu
Hi Atish,
On Tue, Jan 5, 2021 at 4:24 AM Atish Patra wrote:
>
> On Tue, 2020-12-29 at 12:49 +0800, Bin Meng wrote:
> > Hi Atish,
> >
> > On Wed, Dec 23, 2020 at 9:20 AM Bin Meng wrote:
> > >
> > > Hi Atish,
> > >
> > > On Wed, Dec 23, 2020 at 3:59 AM Atish Patra
> > > wrote:
> > > >
> > > > On
On Fri, Dec 18, 2020 at 1:55 PM wrote:
> From: Warner Losh
>
> Here's the first round of bsd-user patches. There's on the order of 280
> that
> we've done, but that's too much to review all at once. In addition, 3.1
> release
> was the last rebase point that we've been successful with for a numb
macOS 11/iOS 14 added preadv/pwritev APIs. Due to weak linking, configure
will succeed with CONFIG_PREADV even when targeting a lower OS version.
We therefore need to check at run time if we can actually use these APIs.
Signed-off-by: Joelle van Dyne
---
block/file-posix.c | 33 +
Signed-off-by: Joelle van Dyne
---
configure | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 09dd22ebad..79dc9811e8 100755
--- a/configure
+++ b/configure
@@ -7033,9 +7033,12 @@ if test "$cross_compile" = "yes"; then
echo "system = 'dar
This introduces support for building for iOS hosts. When the correct Xcode
toolchain is used, iOS host will be detected automatically.
* block: disable features not supported by iOS sandbox
* slirp: disable SMB features for iOS
* osdep: disable system() calls for iOS
Signed-off-by: Joelle van Dyn
iOS does not support ucontext natively for aarch64 and the sigaltstack is
also unsupported (even worse, it fails silently, see:
https://openradar.appspot.com/13002712 )
As a workaround we include a library implementation of ucontext and add it
as a build option.
Signed-off-by: Joelle van Dyne
--
The iOS toolchain does not use the host prefix naming convention. So we
need to enable cross-compile options while allowing the PREFIX to be
blank.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Joelle van Dyne
---
configure | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff
Based-on: 20201214140314.18544-1-richard.hender...@linaro.org
([PATCH v4 00/43] Mirror map JIT memory for TCG)
These set of changes brings QEMU TCG to iOS devices and future Apple Silicon
devices. They were originally developed last year and have been working in the
UTM app. Recently, we ported th
A future libslirp update will use libresolv on Darwin systems, so we add the
flags in QEMU build now.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Joelle van Dyne
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 900dbc36c8..d8951d4d6c 100644
-
Some hosts (iOS) have a sandboxed filesystem and do not provide low-level
APIs for interfacing with host block devices.
Signed-off-by: Joelle van Dyne
---
configure| 4
meson.build | 1 +
qapi/block-core.json | 10 +++---
block/file-posix.c | 10 +-
4 fi
Tested-by: Joelle van Dyne
It works for me. But one thing is that if you build it with the macOS
11.x SDK it won't run on < 11.x. This is why apple recommends
something like:
if (__builtin_available(macOS 11, *)) {
pthread_jit_write_protect_np();
}
You still need a c
On 2021/1/5 8:35, Igor Mammedov wrote:
> On Wed, 30 Dec 2020 16:22:08 -0500
> "Michael S. Tsirkin" wrote:
>
>> On Tue, Dec 29, 2020 at 02:41:42PM +0100, Igor Mammedov wrote:
>>> On Wed, 23 Dec 2020 17:08:31 +0800
>>> Jiahui Cen wrote:
>>>
There may be some differences in pci resource
Hi, Philippe and Peter,
On Tue, Jan 5, 2021 at 2:30 AM Philippe Mathieu-Daudé wrote:
>
> On 1/4/21 7:24 PM, Philippe Mathieu-Daudé wrote:
> > On 1/4/21 6:39 PM, Philippe Mathieu-Daudé wrote:
> >> On 1/4/21 4:01 PM, Peter Maydell wrote:
> >>> On Mon, 4 Jan 2021 at 13:59, Philippe Mathieu-Daudé
>
On Wed, 30 Dec 2020 16:22:08 -0500
"Michael S. Tsirkin" wrote:
> On Tue, Dec 29, 2020 at 02:41:42PM +0100, Igor Mammedov wrote:
> > On Wed, 23 Dec 2020 17:08:31 +0800
> > Jiahui Cen wrote:
> >
> > > There may be some differences in pci resource assignment between guest os
> > > and firmware.
On Wed, 30 Dec 2020 16:17:14 -0500
"Michael S. Tsirkin" wrote:
> On Tue, Dec 29, 2020 at 02:47:35PM +0100, Igor Mammedov wrote:
> > On Wed, 23 Dec 2020 17:08:33 +0800
> > Jiahui Cen wrote:
> >
> > > The overlap check of IO resource window would fail when Linux kernel
> > > registers an IO res
On 12/16/20 9:24 AM, Richard Henderson wrote:
> On 10/21/20 12:38 PM, Philippe Mathieu-Daudé wrote:
>> - Use _aligned_malloc for qemu_try_memalign on win32
>> - Assert qemu_try_memalign() alignment is a power of 2
>>
>> Since v4:
>> - Drop superfluous assert (Richard)
>>
>> Philippe Mathieu-Daudé (
Ping?
On 12/10/20 3:14 PM, Richard Henderson wrote:
> Eliminating these cleans up the backend a bit, allows the
> code generator more freedom to properly place the inputs.
>
>
> r~
>
>
> Richard Henderson (2):
> tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP
> tcg: Introduce INDEX_op_qemu_st
On Mon, 4 Jan 2021 at 23:23, BALATON Zoltan wrote:
>
> The code mapping all PCI interrupts to a single CPU IRQ works but is
> not trivial so document it in a comment.
>
> Signed-off-by: BALATON Zoltan
> ---
> hw/ppc/ppc440_pcix.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-
This fixes the build for older ppc64 kernel headers.
Fixes: 6addf06a3c4
Cc: Josh Kunz
Cc: Shu-Chun Weng
Cc: Laurent Vivier
Signed-off-by: Richard Henderson
---
linux-user/ioctls.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index 661b5daa9f.
On Mon, 4 Jan 2021 13:29:06 -0500
Eduardo Habkost wrote:
> On Mon, Jan 04, 2021 at 01:54:32PM +0100, Vitaly Kuznetsov wrote:
> > Igor Mammedov writes:
> >
> > >> >
> > >> > +/* Hyper-V features enabled with 'hyperv=on' */
> > >> > +x86mc->default_hyperv_features = BIT(HYPERV_FEAT_RE
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> Directly check if the CPU supports 64-bit with the recently
> added cpu_type_is_64bit() helper (inlined).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/mips/boston.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> 'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
> the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
> CPU definitions do.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/mips-defs.h |
Hi Francisco,
On Tue, Jan 5, 2021 at 12:00 AM Francisco Iglesias
wrote:
>
> Hi Bin,
>
> On [2020 Dec 31] Thu 19:29:49, Bin Meng wrote:
> > From: Bin Meng
> >
> > This adds the ISSI SPI flash support. The number of dummy cycles in
> > fast read, fast read dual output and fast read quad output com
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> MIPS 64-bit ISA is introduced with MIPS3.
>
> Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
> and the cpu_type_is_64bit() method to check if a CPU supports
> this ISA (thus is 64-bit).
>
> Suggested-by: Jiaxun Yang
> Signed-off-
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> Remove a comment added 12 years ago but never used (commit
> b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/mips-defs.h | 6 --
> 1 file changed, 6 deletions
This fixes a long standing issue with MorphOS booting on sam460ex
which turns out to be because of suspicious values written to PCI
config address that apparently works on real machine but caused wrong
access on this device model. This replaces a previous work around for
this with a better fix that
Use the PCI_BUS type cast macro to convert result of
qdev_get_child_bus(). Also remove the check for NULL afterwards which
should not be needed because sysbus_create_simple() uses error_abort
and PCI_BUS macro also checks its argument by default so this
shouldn't fail here.
Signed-off-by: BALATON
The trace event for pci_host_config_write() was also using the trace
event for read. Add corresponding trace and correct this.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc440_pcix.c | 2 +-
hw/ppc/trace-events | 1 +
2 files changed, 2 insertions(+), 1 delet
Changes from v3:
- removed first two patches changing Kconfig because the FDT one seems
to be needed so we should not remove those from KConfig and there was
some question about patch 1
- added a new patch to use type cast macro in sam460ex.c
- the other 3 patches should be the same as in v3
Re
The code mapping all PCI interrupts to a single CPU IRQ works but is
not trivial so document it in a comment.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_pcix.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index e
On Mon, 04 Jan 2021 13:54:32 +0100
Vitaly Kuznetsov wrote:
> Igor Mammedov writes:
>
> >> >
> >> > +/* Hyper-V features enabled with 'hyperv=on' */
> >> > +x86mc->default_hyperv_features = BIT(HYPERV_FEAT_RELAXED) |
> >> > +BIT(HYPERV_FEAT_VAPIC) | BIT(HYPERV_FEAT_TIME) |
> >>
On Mon, 14 Dec 2020 15:50:29 -0500
Eduardo Habkost wrote:
> From: Daniel P. Berrangé
>
> The i440fx and Q35 machine types are both hardcoded to use the legacy
> SMBIOS 2.1 entry point. This is a sensible conservative choice because
> SeaBIOS only supports SMBIOS 2.1
>
> EDK2, however, can also
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 4 ++--
target/mips/translate.c | 2 +-
2 files chang
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h| 4 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/cp0_timer.c| 4 +-
target/mips/helper.c
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mi
Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mi
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 4 +-
target/mips/mips-defs.h| 4 +-
linux
Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index c3b94c68e1b..467f
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mi
Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mi
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 5 +
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 555e165fb01.
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 4 +--
target/mips/translate.c | 54 -
3 files changed, 30 insertion
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 8
target/mips/translate_init.c.inc | 14 +++---
Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-def
v3: Replace ISA_MIPS3 by ISA_MIPS64 (Richard)
v2: Do not use MIPS3 for 64R1 (Jiaxun)
Missing review: 1, 3, 4, 5
As we don't need to duplicate 32/64-bit ISA defititions,
this series remove the duplicated 64-bit variants,
simplifying the overall.
Regards,
Phil.
$ git backport-diff -u v2 -r ..v3
On Tue, Dec 29, 2020 at 02:20:01PM +0100, Igor Mammedov wrote:
> On Mon, 14 Dec 2020 15:50:26 -0500
> Eduardo Habkost wrote:
>
> > This includes code previously submitted[1] by Daniel P. Berrangé
> > to add a "smbios-ep" machine property on PC.
> >
> > SMBIOS 3.0 is necessary to support more tha
On Mon, Jan 04, 2021 at 03:42:23PM +, Stefan Hajnoczi wrote:
> On Mon, Dec 14, 2020 at 12:10:15PM +0100, Igor Mammedov wrote:
> > On Wed, 16 Sep 2020 10:51:49 +0100
> > Stefan Hajnoczi wrote:
> >
> > > Let -object memory-backend-file work on read-only files when the
> > > readonly=on option i
On 12/7/20 2:20 PM, Stefan Hajnoczi wrote:
Add a function to remove previously-added abrt handler functions.
Now that a symmetric pair of add/remove functions exists we can also
balance the SIGABRT handler installation. The signal handler was
installed each time qtest_add_abrt_handler() was ca
Is anybody already going to merge this? If not, I can merge it.
On Mon, Jan 04, 2021 at 05:13:17PM +, Stefan Hajnoczi wrote:
> v3:
> * Produce an error when -device nvdimm,unarmed=off is used with -object
>memory-backend-file,readonly=on instead of silently switching on
>unarmed. [Ig
On 04/01/21 18:24, Roman Bolshakov wrote:
Hi Paolo,
I'm sorry I didn't reply earlier. As I showed in an example to Peter
(https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg00085.html):
https://github.com/mesonbuild/meson/commit/ff5dc65ef841857dd306694dff1fb1cd2bf801e4
The approach doesn'
Alexander Graf writes:
> On 04.01.21 16:23, Alex Bennée wrote:
>> Roman Bolshakov writes:
>>
>>> Pages can't be both write and executable at the same time on Apple
>>> Silicon. macOS provides public API to switch write protection [1] for
>>> JIT applications, like TCG.
>>>
>>> 1.
>>> https://
On 11/11/2020 16:56, Stefan Hajnoczi wrote:
> SystemTap's dtrace(1) prints the following warning when it encounters
> long long arguments:
>
> Warning: /usr/bin/dtrace:trace/trace-dtrace-hw_virtio.dtrace:76: syntax
> error near:
> probe vhost_vdpa_dev_start
>
> Warning: Proceeding as if --
Now that the vfio-ccw code has a notifier interface to request that
a device be unplugged, let's wire that together.
Signed-off-by: Eric Farman
Reviewed-by: Cornelia Huck
---
hw/vfio/ccw.c | 40
1 file changed, 36 insertions(+), 4 deletions(-)
diff --gi
On Tue, 2020-12-29 at 12:49 +0800, Bin Meng wrote:
> Hi Atish,
>
> On Wed, Dec 23, 2020 at 9:20 AM Bin Meng wrote:
> >
> > Hi Atish,
> >
> > On Wed, Dec 23, 2020 at 3:59 AM Atish Patra
> > wrote:
> > >
> > > On Tue, 2020-12-22 at 13:35 +0800, Bin Meng wrote:
> > > > Hi Atish,
> > > >
> > > >
Signed-off-by: Eric Farman
---
.../infiniband/hw/vmw_pvrdma/pvrdma_ring.h| 14 +-
.../infiniband/hw/vmw_pvrdma/pvrdma_verbs.h | 2 +-
include/standard-headers/drm/drm_fourcc.h | 175 +-
include/standard-headers/linux/const.h| 36
include/standard-headers
Kernel commit a85cbe6159ff ("uapi: move constants from
to ") breaks our script
because of the unrecognized include. Let's add that to
our processing.
Signed-off-by: Eric Farman
---
scripts/update-linux-headers.sh | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/scripts/up
Conny, et al,
Here is an updated (final?) version of the QEMU series for the vfio-ccw
request notifier now that the kernel code landed upstream [1]. The actual
meat (patch 3) is identical to its counterpart in v2 [2].
Earlier versions didn't use update-linux-headers.sh; they just carried a
dummy
Hi Igor,
yes, that fixes my issue.
Regards, Torsten
Am 04.01.21 um 19:50 schrieb Igor Mammedov:
On Sun, 3 Jan 2021 18:28:11 +0100
Philippe Mathieu-Daudé wrote:
Cc'ing Gerd + patch author/reviewer.
On 1/2/21 2:11 PM, Torsten Wohlfarth wrote:
Hello,
i can't start any system if i use virgl.
On 12/7/20 2:20 PM, Stefan Hajnoczi wrote:
Tests that manage multiple processes may wish to kill QEMU before
destroying the QTestState. Expose a function to do that.
The vhost-user-blk-test testcase will need this.
Signed-off-by: Stefan Hajnoczi
---
tests/qtest/libqos/libqtest.h | 11 +
On 12/7/20 2:20 PM, Stefan Hajnoczi wrote:
Add an API that returns a new UNIX domain socket in the listen state.
The code for this was already there but only used internally in
init_socket().
This new API will be used by vhost-user-blk-test.
Signed-off-by: Stefan Hajnoczi
---
tests/qtest/l
On Sun, 3 Jan 2021 18:28:11 +0100
Philippe Mathieu-Daudé wrote:
> Cc'ing Gerd + patch author/reviewer.
>
> On 1/2/21 2:11 PM, Torsten Wohlfarth wrote:
> > Hello,
> >
> > i can't start any system if i use virgl. I get the following error:
> >
> > qemu-x86_64: ../ui/console.c:1791: dpy_gl_ctx_cr
On Mon, Jan 04, 2021 at 01:46:29PM +0100, Halil Pasic wrote:
> On Sun, 3 Jan 2021 23:15:50 -0800
> Ram Pai wrote:
>
> > On Fri, Dec 18, 2020 at 12:41:11PM +0100, Cornelia Huck wrote:
> > > On Thu, 17 Dec 2020 15:15:30 +0100
> [..]
> > > > > > > > +int kvmppc_svm_init(SecurableGuestMemory *sgm, Er
On 04.01.21 16:23, Alex Bennée wrote:
Roman Bolshakov writes:
Pages can't be both write and executable at the same time on Apple
Silicon. macOS provides public API to switch write protection [1] for
JIT applications, like TCG.
1.
https://developer.apple.com/documentation/apple_silicon/port
On 1/4/21 7:24 PM, Philippe Mathieu-Daudé wrote:
> On 1/4/21 6:39 PM, Philippe Mathieu-Daudé wrote:
>> On 1/4/21 4:01 PM, Peter Maydell wrote:
>>> On Mon, 4 Jan 2021 at 13:59, Philippe Mathieu-Daudé wrote:
I don't have access to OSX host. I'll see to install an aarch32 chroot and
keep te
On Mon, Jan 04, 2021 at 01:54:32PM +0100, Vitaly Kuznetsov wrote:
> Igor Mammedov writes:
>
> >> >
> >> > +/* Hyper-V features enabled with 'hyperv=on' */
> >> > +x86mc->default_hyperv_features = BIT(HYPERV_FEAT_RELAXED) |
> >> > +BIT(HYPERV_FEAT_VAPIC) | BIT(HYPERV_FEAT_TIME) |
On 1/4/21 6:39 PM, Philippe Mathieu-Daudé wrote:
> On 1/4/21 4:01 PM, Peter Maydell wrote:
>> On Mon, 4 Jan 2021 at 13:59, Philippe Mathieu-Daudé wrote:
>>> I don't have access to OSX host. I'll see to install an aarch32 chroot and
>>> keep testing (not sure what can differ from an i386 guest).
>>
Hello,
I'm trying to start a TeamSpeak 3 Server inside my Docker container.
Yes, this application is publicly available on the developer website and is
free to install and use.
Feel free to ask more question or test in other to resolve this matter.
Thank you.
Regards,
--
You received this bu
On Mon, 4 Jan 2021 10:35:45 -0300
Daniel Henrique Barboza wrote:
> Hi,
>
> This question came up while I was investigating a Libvirt bug [1], where an
> user is removing
> VFs from the host while Libvirt domains was using them, causing Libvirt to
> remain in
> an inconsistent state. I'm trying
On Mon, 4 Jan 2021 at 17:49, Paolo Bonzini wrote:
> On 04/01/21 16:19, Peter Maydell wrote:
> > Does this work recursively? For instance monitor/qmp-cmds.c
> > needs the gnutls CFLAGS because:
> > * qmp-cmds.c includes ui/vnc.h
> > * ui/vnc.h includes include/crypto/tlssession.h
> > * includ
On 04/01/21 16:19, Peter Maydell wrote:
On Mon, 4 Jan 2021 at 14:40, Paolo Bonzini wrote:
On 04/01/21 14:21, Peter Maydell wrote:
The rest of QEMU should only ever be using QEMU's TLS abstractions
and not directly be tied to GNUTLS. So ideally the gnutls flags
should only ever be added in the
The alias is intended to indicate that the bswap is for the
entire target_long. This should avoid ifdefs on some targets.
Reviewed-by: Frank Chang
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/tcg/tcg-op.h b/include/tcg/
On 1/4/21 4:01 PM, Peter Maydell wrote:
> On Mon, 4 Jan 2021 at 13:59, Philippe Mathieu-Daudé wrote:
>> I don't have access to OSX host. I'll see to install an aarch32 chroot and
>> keep testing (not sure what can differ from an i386 guest).
>> If I can't find anything I'll resend the same series
In f47db80cc07, we handled odd-sized tail clearing for
the case of hosts that have vector operations, but did
not handle the case of hosts that do not have vector ops.
This was ok until e2e7168a214b, which changed the encoding
of simd_desc such that the odd sizes are impossible.
Add memset as a t
From: Zihao Yu
Out-of-range shifts have undefined results, but must not trap.
Mask off immediate shift counts to solve this problem.
This bug can be reproduced by running the following guest instructions:
xor %ecx,%ecx
sar %cl,%eax
cmovne %edi,%eax
After optimization, the tcg opcodes of
s/pull-tcg-20210104
for you to fetch changes up to a66424ba17d661007dc13d78c9e3014ccbaf0efb:
tcg: Add tcg_gen_bswap_tl alias (2021-01-04 06:32:58 -1000)
Fix vector clear issue.
Fix riscv host shift issue.
Add tcg_ge
On Sat, Jan 02, 2021 at 08:43:51PM +0100, Paolo Bonzini wrote:
> On 02/01/21 14:25, Peter Maydell wrote:
> > Question to Paolo -- it seems pretty fragile to have to explicitly
> > list "these source files need these extra CFLAGS" in half a dozen
> > meson.build files, because it's pretty non-obviou
On Mon, 4 Jan 2021 at 14:23, Stefan Hajnoczi wrote:
>
> The following changes since commit 41192db338588051f21501abc13743e62b0a5605:
>
> Merge remote-tracking branch
> 'remotes/ehabkost-gl/tags/machine-next-pull-request' into staging (2021-01-01
> 22:57:15 +)
>
> are available in the Git r
Check that -device nvdimm,unarmed=on is used when -object
memory-backend-file,readonly=on and document that -device
nvdimm,unarmed=on|off controls whether the NVDIMM appears read-only to
the guest.
Acked-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Liam Merwick
Signed
On Mon, 4 Jan 2021 at 16:30, Philippe Mathieu-Daudé wrote:
>
> On 1/4/21 5:12 PM, Peter Maydell wrote:
> > The qmp-cmds.c file currently includes ui/vnc.h, which (being located
> > in the ui/ directory rather than include) is really supposed to be
> > for use only by the ui subsystem.
>
> That mak
v3:
* Produce an error when -device nvdimm,unarmed=off is used with -object
memory-backend-file,readonly=on instead of silently switching on
unarmed. [Igor]
* Use Object *obj instead of Object *o [Igor]
* Do not dereference MEMORY_BACKEND_FILE(o)->readonly directly, use a
local variable
There is currently no way to open(O_RDONLY) and mmap(PROT_READ) when
creating a memory region from a file. This functionality is needed since
the underlying host file may not allow writing.
Add a bool readonly argument to memory_region_init_ram_from_file() and
the APIs it calls.
Extend memory_reg
Let -object memory-backend-file work on read-only files when the
readonly=on option is given. This can be used to share the contents of a
file between multiple guests while preventing them from consuming
Copy-on-Write memory if guests dirty the pages, for example.
Acked-by: Michael S. Tsirkin
Rev
On 1/4/21 5:12 PM, Peter Maydell wrote:
> The qmp-cmds.c file currently includes ui/vnc.h, which (being located
> in the ui/ directory rather than include) is really supposed to be
> for use only by the ui subsystem.
That makes me remember yet another cleanup series I started few months
ago to rem
1 - 100 of 143 matches
Mail list logo
