[Bug 1914849] [NEW] mprotect fails after MacOS 11.2 on arm mac

Public bug reported: I got the following error when I ran qemu on arm mac(MacOS 11.2). ``` $ ./qemu-system-x86_64 qemu-system-x86_64: qemu_mprotect__osdep: mprotect failed: Permission denied ** ERROR:../tcg/tcg.c:844:tcg_region_init: assertion failed: (!rc) Bail out!

[PATCH 6/6] hw/block/nvme: support namespace attachment command

This patch supports Namespace Attachment command for the pre-defined nvme-ns device nodes. Of course, attach/detach namespace should only be supported in case 'subsys' is given. This is because if we detach a namespace from a controller, somebody needs to manage the detached, but allocated

[PATCH 5/6] hw/block/nvme: refactor nvme_select_ns_iocs

This patch has no functional changes. This patch just refactored nvme_select_ns_iocs() to iterate the attached namespaces of the controlller and make it invoke __nvme_select_ns_iocs(). Signed-off-by: Minwoo Im --- hw/block/nvme.c | 36 +--- 1 file changed, 21

[PATCH 4/6] hw/block/nvme: support allocated namespace type

>From NVMe spec 1.4b "6.1.5. NSID and Namespace Relationships" defines valid namespace types: - Unallocated: Not exists in the NVMe subsystem - Allocated: Exists in the NVMe subsystem - Inactive: Not attached to the controller - Active: Attached to the controller

[PATCH 3/6] hw/block/nvme: fix allocated namespace list to 256

Expand allocated namespace list (subsys->namespaces) to have 256 entries which is a value lager than at least NVME_MAX_NAMESPACES which is for attached namespace list in a controller. Allocated namespace list should at least larger than attached namespace list. n->num_namespaces =

[PATCH 1/6] hw/block/nvme: support namespace detach

Given that now we have nvme-subsys device supported, we can manage namespace allocated, but not attached: detached. This patch introduced a parameter for nvme-ns device named 'detached'. This parameter indicates whether the given namespace device is detached from a entire NVMe subsystem('subsys'

[PATCH 2/6] hw/block/nvme: fix namespaces array to 1-based

subsys->namespaces array used to be sized to NVME_SUBSYS_MAX_NAMESPACES. But subsys->namespaces are being accessed with 1-based namespace id which means the very first array entry will always be empty(NULL). Signed-off-by: Minwoo Im --- hw/block/nvme-subsys.h | 2 +- 1 file changed, 1

[PATCH 0/6] hw/block/nvme: support namespace attachment

Hello, This series supports namespace attachment: attach and detach. It means that this series also introduced a scheme for allocated namespace which is detached, but allocated in a NVMe subsystem. Given that now we have nvme-subsys device to specify a NVMe subsystem, it can manage detached

[PULL 46/46] accel: introduce AccelCPUClass extending CPUClass

From: Claudio Fontana add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. This will allow to separate the target cpu code that is specific to each accelerator, and register it automatically with object

[PULL 45/46] accel: replace struct CpusAccel with AccelOpsClass

From: Claudio Fontana This will allow us to centralize the registration of the cpus.c module accelerator operations (in accel/accel-softmmu.c), and trigger it automatically using object hierarchy lookup from the new accel_init_interfaces() initialization step, depending just on which

[PULL 44/46] accel: extend AccelState and AccelClass to user-mode

From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée [claudio: rebased on Richard's splitwx work] Signed-off-by: Claudio Fontana Message-Id: <20210204163931.7358-17-cfont...@suse.de> Signed-off-by: Richard Henderson --- include/hw/boards.h| 2 +-

[PULL 40/46] physmem: make watchpoint checking code TCG-only

From: Claudio Fontana cpu_check_watchpoint, watchpoint_address_matches are TCG-only. Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Message-Id: <20210204163931.7358-13-cfont...@suse.de> Signed-off-by: Richard Henderson --- softmmu/physmem.c | 141

[PULL 41/46] cpu: move adjust_watchpoint_address to tcg_ops

From: Claudio Fontana commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs") introduced this ARM-specific, TCG-specific hack to adjust the address, before checking it with cpu_check_watchpoint. Make adjust_watchpoint_address optional and move it to tcg_ops. Signed-off-by:

[PULL 35/46] cpu: Move debug_excp_handler to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20210204163931.7358-8-cfont...@suse.de> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- accel/tcg/cpu-exec.c

[PULL 42/46] cpu: move debug_check_watchpoint to tcg_ops

From: Claudio Fontana commit 568496c0c0f1 ("cpu: Add callback to check architectural") and commit 3826121d9298 ("target-arm: Implement checking of fired") introduced an ARM-specific hack for cpu_check_watchpoint. Make debug_check_watchpoint optional, and move it to tcg_ops. Signed-off-by:

[PULL 37/46] cpu: move cc->do_interrupt to tcg_ops

From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20210204163931.7358-10-cfont...@suse.de> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- accel/tcg/cpu-exec.c| 4 ++--

[PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped target code in CONFIG_TCG, reworded comments] Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Message-Id: <20210204163931.7358-5-cfont...@suse.de> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h |

[PULL 39/46] cpu: move do_unaligned_access to tcg_ops

From: Claudio Fontana make it consistently SOFTMMU-only. Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson [claudio: make the field presence in cpu.h unconditional, removing the ifdefs] Message-Id:

[PULL 34/46] cpu: Move tlb_fill to tcg_ops

From: Eduardo Habkost [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20210204163931.7358-7-cfont...@suse.de> Signed-off-by:

[PULL 24/46] tcg/tci: Implement 64-bit division

Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c| 28 ++-- tcg/tci/tcg-target.c.inc

[PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly

From: Claudio Fontana cc->do_interrupt is in theory a TCG callback used in accel/tcg only, to prepare the emulated architecture to take an interrupt as defined in the hardware specifications, but in reality the _do_interrupt style of functions in targets are also occasionally reused by KVM to

[PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass

From: Claudio Fontana we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations

[PULL 33/46] cpu: Move cpu_exec_* to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20210204163931.7358-6-cfont...@suse.de> Signed-off-by:

[PULL 29/46] cpu: Introduce TCGCpuOperations struct

From: Eduardo Habkost The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an

[PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn

From: Claudio Fontana move away TCG-only code, make it compile only on TCG. Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson [claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h] Signed-off-by: Claudio Fontana Message-Id: <20210204163931.7358-4-cfont...@suse.de>

[PULL 38/46] cpu: move cc->transaction_failed to tcg_ops

From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY] avoiding its use in headers used by common_ss code (should be poisoned).

[PULL 25/46] tcg/tci: Remove TODO as unused

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 8 1 file changed, 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5c84a1c979..e0d815e4b2 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -33,14 +33,6 @@ #include "tcg/tcg-op.h"

[PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16

As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 32

[PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64}

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 6819c97792..fe935e71a3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -618,7 +618,7 @@ uintptr_t

[PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG

From: Claudio Fontana for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana Reviewed-by: Alistair Francis Reviewed-by: Alex Bennée Message-Id: <20210204163931.7358-3-cfont...@suse.de> Signed-off-by: Richard Henderson ---

[PULL 22/46] tcg/tci: Use g_assert_not_reached

Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Tested-by: Alex Bennée Reviewed-by: Stefan Weil Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 15 +++ 1 file changed, 7 insertions(+), 8

[PULL 28/46] tcg/tci: Remove TCG_CONST

Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson

[PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64}

Eliminating a TODO for ld16s_i64. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index b64d611ec9..259a8538bf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@

[PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage

This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still

[PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64}

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index ee2cd7dfa2..eb70672efb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -625,6 +625,7 @@ uintptr_t

[PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*

We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c| 12 tcg/tci/tcg-target.c.inc | 8 2 files

[PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64}

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0f56702b93..7e108bcbb3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -455,6 +455,18

[PULL 20/46] tcg/tci: Move stack bounds check to compile-time

The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Tested-by: Alex Bennée Reviewed-by: Alex

[PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64}

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 55863f76a7..6819c97792 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -612,7 +612,7 @@ uintptr_t

[PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64}

Eliminating a TODO for ld16u_i32. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c31be1a1f4..b64d611ec9 100644 --- a/tcg/tci.c +++

[PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers

Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard

[PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 259a8538bf..55863f76a7 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -606,6 +606,7 @@ uintptr_t

[PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e8023b5384..740244cc54 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -117,11 +117,6 @@

[PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 740244cc54..005d2946c4 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -117,14 +117,6 @@

[PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers

For a 64-bit TCI, the upper bits of a 32-bit operation are undefined (much like a native ppc64 32-bit operation). It simplifies everything if we don't force-extend the result. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 66

[PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64}

Eliminating a TODO for ld8s_i32. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 7e108bcbb3..c31be1a1f4 100644 --- a/tcg/tci.c +++

[PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local

Each thread must have its own pc, even under TCI. Remove the GETPC ifdef, because GETPC is always available for helpers, and thus is always required. Move the assignment under INDEX_op_call, because the value is only visible when we make a call to a helper function. Reviewed-by: Alex Bennée

[PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32

From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reported-by: Alex Bennée Signed-off-by: Stefan Weil Message-Id:

[PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller

Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c3a8511dfe..e8023b5384 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -117,14 +117,6 @@

[PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps

Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd argument is an integer, not a temporary, which now tickles an assert added in e89b28a6350. Previously, the value computed into v2 would be garbage for rotli_vec, but as the value was unused it caused no harm. Signed-off-by: Richard

[PULL 04/46] configure: Fix --enable-tcg-interpreter

The configure option was backward, and we failed to pass the value on to meson. Fixes: 23a77b2d18b ("build-system: clean up TCG/TCI configury") Tested-by: Stefan Weil Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel P. Berrangé Signed-off-by: Philippe

[PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility

From: Philippe Mathieu-Daudé The code is currently comparing c2 to the type promotion of uint32_t and int32_t. That is, the conversion rules are as: (common_type) c2 == (common_type) (uint32_t) (is_unsigned ? (uint32_t)c2

[PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64

From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reported-by: Alex Bennée Signed-off-by: Stefan Weil Message-Id:

[PULL 02/46] exec/cpu-defs: Remove TCG backends dependency

From: Philippe Mathieu-Daudé "exec/cpu-defs.h" contains generic CPU definitions for the TCG frontends (mostly related to TLB). TCG backends definitions aren't relevant here. See tcg/README description: 4) Backend tcg-target.h contains the target specific definitions. tcg-target.c.inc

[PULL 00/46] tcg patch queue

The following changes since commit d0dddab40e472ba62b5f43f11cc7dba085dabe71: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-02-05 15:27:02 +) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210205 for you

Re: [PULL v3 00/27] Block patches

On Fri, 5 Feb 2021 at 16:45, Stefan Hajnoczi wrote: > > The following changes since commit e2c5093c993ef646e4e28f7aa78429853bcc06ac: > > iotests: 30: drop from auto group (and effectively from make check) > (2021-02-05 15:16:13 +) > > are available in the Git repository at: > >

Re: [Avocado-devel] acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?

Hi all, I will try to give my two cents: On Fri, Feb 05, 2021 at 03:31:40PM -0500, John Snow wrote: > On 2/5/21 11:43 AM, Philippe Mathieu-Daudé wrote: > > Cc'ing Avocado team & John (Python inferior exit delay?). > > > > On 1/28/21 11:10 AM, Thomas Huth wrote: > > > On 28/01/2021 10.45,

Re: Help with Windows XP in qemu-system-i386

> On Feb 5, 2021, at 3:49 PM, Michael S. Tsirkin wrote: > > On Fri, Feb 05, 2021 at 03:25:00PM -0500, Programmingkid wrote: >> Hi, I'm noticing that my Windows XP Service Pack 3 VM is causing >> qemu-system-i386 to experience 100% host cpu usage even when the guest is at >> idle. I was

Re: acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?

On 2/5/21 11:43 AM, Philippe Mathieu-Daudé wrote: Cc'ing Avocado team & John (Python inferior exit delay?). On 1/28/21 11:10 AM, Thomas Huth wrote: On 28/01/2021 10.45, Claudio Fontana wrote: is it just me, or is the CI sometimes failing with timeout? Fedora:

Re: [PATCH v2] qemu-nbd: Use SOMAXCONN for socket listen() backlog

On Fri, Feb 05, 2021 at 12:57:05PM -0600, Eric Blake wrote: > Our default of a backlog of 1 connection is rather puny, particularly > for scenarios where we expect multiple listeners to connect (such as > qemu-nbd -e X). This is especially important for Unix sockets, as a > definite benefit to

Re: [PATCH v16 23/23] accel-cpu: make cpu_realizefn return a bool

On 2/4/21 6:39 AM, Claudio Fontana wrote: > overall, all devices' realize functions take an Error **errp, but return void. > > hw/core/qdev.c code, which realizes devices, therefore does: > > local_err = NULL; > dc->realize(dev, _err); > if (local_err != NULL) { > goto fail; > } > >

Re: [PATCH v16 00/23] i386 cleanup PART 2

On 2/4/21 6:39 AM, Claudio Fontana wrote: > Claudio Fontana (18): > target/riscv: remove CONFIG_TCG, as it is always TCG > accel/tcg: split TCG-only code from cpu_exec_realizefn > target/arm: do not use cc->do_interrupt for KVM directly > cpu: move cc->do_interrupt to tcg_ops > cpu: move

Re: [PATCH v16 22/23] target/i386: fix host_cpu_adjust_phys_bits error handling

On 2/4/21 6:39 AM, Claudio Fontana wrote: > move the check for phys_bits outside of host_cpu_adjust_phys_bits, > because otherwise it is impossible to return an error condition > explicitly. > > Signed-off-by: Claudio Fontana > Reviewed-by: Philippe Mathieu-Daudé > Reviewed-by: Alex Bennée >

Re: [PATCH 2/4] hw/block/fdc: Remove the check_media_rate property

On 2/5/21 1:37 AM, Thomas Huth wrote: On 05/02/2021 01.40, John Snow wrote: On 2/3/21 12:18 PM, Thomas Huth wrote: This was only required for the pc-1.0 and earlier machine types. Now that these have been removed, we can also drop the corresponding code from the FDC device. Signed-off-by:

Re: [PATCH v16 21/23] accel: introduce new accessor functions

On 2/4/21 6:39 AM, Claudio Fontana wrote: > @@ -6725,10 +6722,8 @@ static void x86_cpu_initfn(Object *obj) > x86_cpu_load_model(cpu, xcc->model); > } > > -/* if required, do the accelerator-specific cpu initialization */ > -if (cc->accel_cpu) { > -

Re: [PATCH v16 19/23] i386: split cpu accelerators from cpu.c, using AccelCPUClass

On 2/4/21 6:39 AM, Claudio Fontana wrote: > +static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data) > +{ > +AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); > + > +acc->cpu_realizefn = host_cpu_realizefn; > +acc->cpu_instance_init = hvf_cpu_instance_init; > +}; Watch the stray ;

Re: [PATCH v2] qemu-nbd: Use SOMAXCONN for socket listen() backlog

On Fri, Feb 5, 2021 at 8:57 PM Eric Blake wrote: > > Our default of a backlog of 1 connection is rather puny, particularly > for scenarios where we expect multiple listeners to connect (such as > qemu-nbd -e X). This is especially important for Unix sockets, as a > definite benefit to clients:

Re: [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0

> On Feb 5, 2021, at 1:49 PM, Jonathan Cameron > wrote: > > On Fri, 5 Feb 2021 09:19:36 -0800 > Ben Widawsky wrote: > >> On 21-02-05 16:09:54, Jonathan Cameron wrote: >>> On Wed, 3 Feb 2021 23:53:53 -0500 >>> Chris Browy wrote: >>> Hi Jonathan, Thanks for the review

Re: [PATCH 00/24] hw/arm: New board model mps3-an524

On Fri, 5 Feb 2021 at 19:31, Philippe Mathieu-Daudé wrote: > > On Fri, Feb 5, 2021 at 8:21 PM Peter Maydell wrote: > > On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote: > > > On 2/5/21 5:59 PM, Peter Maydell wrote: > > > > (The selftest is part of the AN524 > > > > download so it's

Re: [PATCH 00/24] hw/arm: New board model mps3-an524

On Fri, Feb 5, 2021 at 8:21 PM Peter Maydell wrote: > On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote: > > On 2/5/21 5:59 PM, Peter Maydell wrote: > > > (The selftest is part of the AN524 > > > download so it's behind a EULA click-through and we can't put it > > > into an acceptance

Re: runaway avocado

On Mon, 26 Oct 2020 at 22:35, Peter Maydell wrote: > > So, I somehow ended up with this process still running on my > local machine after a (probably failed) 'make check-acceptance': > > petmay01 13710 99.7 3.7 2313448 1235780 pts/16 Sl 16:10 378:00 > ./qemu-system-aarch64 -display none -vga

Re: [PATCH 00/24] hw/arm: New board model mps3-an524

On Fri, 5 Feb 2021 at 18:05, Philippe Mathieu-Daudé wrote: > On 2/5/21 5:59 PM, Peter Maydell wrote: > > (The selftest is part of the AN524 > > download so it's behind a EULA click-through and we can't put it > > into an acceptance test. We might be able to get something > > based on Zephyr or

Re: [PATCH] arm: Update infocenter.arm.com URLs

On Fri, 5 Feb 2021 at 18:07, Philippe Mathieu-Daudé wrote: > > On 2/5/21 6:14 PM, Peter Maydell wrote: > > -/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller: > > +/* > > + * This is a model of the Arm PrimeCell PL080/PL081 DMA controller: > > * The PL080 TRM is: > > - *

Re: [PATCH] sockets: Use SOMAXCONN for Unix socket listen()

On 2/5/21 3:55 AM, Daniel P. Berrangé wrote: >> +++ b/util/qemu-sockets.c >> @@ -1059,7 +1059,7 @@ int unix_listen(const char *str, Error **errp) >> >> saddr = g_new0(UnixSocketAddress, 1); >> saddr->path = g_strdup(str); >> -sock = unix_listen_saddr(saddr, 1, errp); >> +sock =

[PATCH v2] qemu-nbd: Use SOMAXCONN for socket listen() backlog

Our default of a backlog of 1 connection is rather puny, particularly for scenarios where we expect multiple listeners to connect (such as qemu-nbd -e X). This is especially important for Unix sockets, as a definite benefit to clients: at least on Linux, a client trying to connect to a Unix

[QEMU TCG] Qeustion about the PCID Feature in TCG

Hi, I am running QEMU in TCG mode (my server doesn't have kvm support), and I am getting the memory traces in a x86 guest machine of all memory accesses, including the PCID (process-context identifier, and I need that for my current research), on a linux host. I have seen the TCG PCID feature flag

Re: [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0

On Fri, 5 Feb 2021 09:19:36 -0800 Ben Widawsky wrote: > On 21-02-05 16:09:54, Jonathan Cameron wrote: > > On Wed, 3 Feb 2021 23:53:53 -0500 > > Chris Browy wrote: > > > > > Hi Jonathan, > > > > > > Thanks for the review comments and we'll put out a v2 patch series > > > based on a genuine

Re: [PATCH v2] hw/scsi/scsi-disk: Fix out of bounds access in mode_sense_page()

On 04/02/21 23:50, Philippe Mathieu-Daudé wrote: diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c index ed52fcd49ff..93aec483e88 100644 --- a/hw/scsi/scsi-disk.c +++ b/hw/scsi/scsi-disk.c @@ -1089,7 +1089,7 @@ static int scsi_emulate_mechanism_status(SCSIDiskState *s, uint8_t *outbuf)

Re: [PATCH 2/9] tests/qtest: Restrict xlnx-can-test to TCG builds

On 2/5/21 5:57 PM, Peter Maydell wrote: > On Fri, 5 Feb 2021 at 14:43, Philippe Mathieu-Daudé wrote: >> >> The Xilinx CAN controller test is uses the ZCU102 board which is >> based on a ZynqMP SoC. In the default configuration - used by this >> test - this SoC creates 2 Cortex R5F cores. Such

Re: [PATCH 00/24] hw/arm: New board model mps3-an524

Patchew URL: https://patchew.org/QEMU/20210205170019.25319-1-peter.mayd...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210205170019.25319-1-peter.mayd...@linaro.org Subject: [PATCH 00/24] hw/arm: New

Re: [PATCH v2 5/5] travis.yml: Move the -fsanitize=thread testing to the gitlab-CI

Thomas Huth writes: > Use clang-10, so we can also use the --enable-tsan configure > option instead of only passing the flag via --extra-cflags. > > Signed-off-by: Thomas Huth Reviewed-by: Alex Bennée -- Alex Bennée

[PATCH v2 5/8] seccomp: Replace the word 'blacklist'

Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the word "blacklist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Reviewed-by: Daniel P. Berrangé Acked-by: Eduardo Otubo

[PATCH v2 2/8] tools/virtiofsd: Replace the word 'whitelist'

Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the words "whitelist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Daniel P.

[PATCH v2 6/8] qemu-options: Replace the word 'blacklist'

Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the word "blacklist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Signed-off-by: Philippe Mathieu-Daudé --- v2: Reword (danpb) ---

[PATCH v2 1/8] ui: Replace the word 'whitelist'

Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the words "whitelist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Reviewed-by: Gerd Hoffmann Signed-off-by: Philippe Mathieu-Daudé

Re: [PATCH 01/24] hw/arm/mps2-tz: Make SYSCLK frequency board-specific

On 2/5/21 5:59 PM, Peter Maydell wrote: > The AN524 has a different SYSCLK frequency from the AN505 and AN521; > make the SYSCLK frequency a field in the MPS2TZMachineClass rather > than a compile-time constant so we can support the AN524. > > Signed-off-by: Peter Maydell > --- >

Re: [PATCH 00/24] hw/arm: New board model mps3-an524

On 2/5/21 5:59 PM, Peter Maydell wrote: > This patchseries implements a new board model in the mps2/mps3 family, > based on Application Note AN524: > https://developer.arm.com/documentation/dai0524/latest/ > > Like the other MPS models, this board is an FPGA image; the AN524 > image is based on

[PATCH v2 0/8] misc: Replace the words 'blacklist/whitelist'

Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the words "blacklist" and "whitelist" appropriately. Since v1: - dropped qemu-guest-agent patches - addressed review comments - added R-b tags Missing review: PATCH #6

Re: [PATCH] arm: Update infocenter.arm.com URLs

On 2/5/21 6:14 PM, Peter Maydell wrote: > Update infocenter.arm.com URLs for various pieces of Arm > documentation to the new developer.arm.com equivalents. (There is a > redirection in place from the old URLs, but we might as well update > our comments in case the redirect ever disappears in

Re: [PATCH v4 5/5] qapi: More complex uses of QAPI_LIST_APPEND

On 1/26/21 3:31 AM, Markus Armbruster wrote: > Eric Blake writes: > >> These cases require a bit more thought to review; in each case, the >> code was appending to a list, but not with a FOOList **tail variable. >> >> Signed-off-by: Eric Blake >> Reviewed-by: Vladimir Sementsov-Ogievskiy >> >>

Re: [PATCH v2 2/5] travis.yml: Move the -fsanitize=undefined test to the gitlab-CI

Thomas Huth writes: > Add it to the existing Clang job and also add a job that covers the > linux-user code with this compiler flag. To make sure that the detected > problems are not simply ignored, let's also use "-fno-sanitize-recover=..." > now instead. > > Signed-off-by: Thomas Huth > ---

Re: [PATCH v2 30/36] block: bdrv_reopen_multiple: refresh permissions on updated graph

Am 27.11.2020 um 15:45 hat Vladimir Sementsov-Ogievskiy geschrieben: > Move bdrv_reopen_multiple to new paradigm of permission update: > first update graph relations, then do refresh the permissions. > > We have to modify reopen process in file-posix driver: with new scheme > we don't have

Re: [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0

On 21-02-05 16:09:54, Jonathan Cameron wrote: > On Wed, 3 Feb 2021 23:53:53 -0500 > Chris Browy wrote: > > > Hi Jonathan, > > > > Thanks for the review comments and we'll put out a v2 patch series > > based on a genuine git send-email flow in a day or so and plan to include > > - functionally

[PATCH 23/24] docs/system/arm/mps2.rst: Document the new mps3-an524 board

Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell --- docs/system/arm/mps2.rst | 24 ++-- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 8c5b5f1fe07..601ccea15cb 100644

Re: [PATCH v2 4/5] travis.yml: (Re-)move the --enable-debug jobs

Thomas Huth writes: > We already have similar jobs in the gitlab-CI ("build-some-softmmu" and > "build-user-plugins"), so let's switch one of them to use --enable-debug > instead of --enable-debug-tcg, then we can simply drop these jobs from > the Travis-CI. > > Signed-off-by: Thomas Huth

[PATCH v2 8/8] hw/vfio/pci-quirks: Replace the word 'blacklist'

Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the word "blacklist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Reviewed-by: Alex Williamson Acked-by: Alex Williamson

[PATCH 22/24] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524

The AN524 has a PL031 RTC, which we have a model of; provide it rather than an unimplemented-device stub. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index

Re: [PATCH v2 3/5] travis.yml: Move the --enable-modules test to the gitlab-CI

Thomas Huth writes: > Simply add the flag to an existing job, no need for yet another > job here. > > Reviewed-by: Wainer dos Santos Moschetta > Signed-off-by: Thomas Huth Reviewed-by: Alex Bennée -- Alex Bennée

[PATCH v2 4/8] scripts/device-crash-test: Replace the word 'whitelist'

Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the word "whitelist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Reviewed-by: Daniel P. Berrangé Signed-off-by: Philippe

Re: [PATCH v7 12/35] Hexagon (target/hexagon) instruction attributes

Hi Taylor, +Eric in case I'm wrong. On 1/30/21 12:15 AM, Taylor Simpson wrote: On 1/20/21 4:28 AM, Taylor Simpson wrote: > Signed-off-by: Taylor Simpson > --- > target/hexagon/attribs.h | 30 ++ > target/hexagon/attribs_def.h | 95

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