[PULL v9 06/13] sev: Add Error ** to sev_kvm_init()

This allows failures to be reported richly and idiomatically. Signed-off-by: David Gibson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cornelia Huck --- accel/kvm/kvm-all.c | 4 +++- accel/kvm/sev-stub.c | 2 +- include/sysemu/sev.h | 2 +-

[PULL v9 01/13] qom: Allow optional sugar props

From: Greg Kurz Global properties have an @optional field, which allows to apply a given property to a given type even if one of its subclasses doesn't support it. This is especially used in the compat code when dealing with the "disable-modern" and "disable-legacy" properties and the

[PULL v9 13/13] s390: Recognize confidential-guest-support option

At least some s390 cpu models support "Protected Virtualization" (PV), a mechanism to protect guests from eavesdropping by a compromised hypervisor. This is similar in function to other mechanisms like AMD's SEV and POWER's PEF, which are controlled by the "confidential-guest-support" machine

[PULL v9 02/13] confidential guest support: Introduce new confidential guest support class

Several architectures have mechanisms which are designed to protect guest memory from interference or eavesdropping by a compromised hypervisor. AMD SEV does this with in-chip memory encryption and Intel's TDX can do similar things. POWER's Protected Execution Framework (PEF) accomplishes a

[PULL v9 03/13] sev: Remove false abstraction of flash encryption

When AMD's SEV memory encryption is in use, flash memory banks (which are initialed by pc_system_flash_map()) need to be encrypted with the guest's key, so that the guest can read them. That's abstracted via the kvm_memcrypt_encrypt_data() callback in the KVM state.. except, that it doesn't

[PULL v9 04/13] confidential guest support: Move side effect out of machine_set_memory_encryption()

When the "memory-encryption" property is set, we also disable KSM merging for the guest, since it won't accomplish anything. We want that, but doing it in the property set function itself is thereoretically incorrect, in the unlikely event of some configuration environment that set the property

Re: [RFC PATCH v4 0/7] eBPF RSS support for virtio-net

On 2021/2/5 上午1:09, Andrew Melnychenko wrote: This set of patches introduces the usage of eBPF for packet steering and RSS hash calculation: * RSS(Receive Side Scaling) is used to distribute network packets to guest virtqueues by calculating packet hash * Additionally adding support for the

[PATCH v8 22/35] Hexagon (target/hexagon) generater phase 4 - decode tree

Python script that emits the decode tree in dectree_generated.h. Signed-off-by: Taylor Simpson --- target/hexagon/dectree.py | 351 ++ 1 file changed, 351 insertions(+) create mode 100755 target/hexagon/dectree.py diff --git

[PULL v9 13/13] s390: Recognize confidential-guest-support option

At least some s390 cpu models support "Protected Virtualization" (PV), a mechanism to protect guests from eavesdropping by a compromised hypervisor. This is similar in function to other mechanisms like AMD's SEV and POWER's PEF, which are controlled by the "confidential-guest-support" machine

[PATCH v8 29/35] Hexagon (target/hexagon) translation

Read the instruction memory Create a packet data structure Generate TCG code for the start of the packet Invoke the generate function for each instruction Generate TCG code for the end of the packet Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 93 ++

Re: [PATCH v2] travis-ci: Disable C++ on Aarch64 container

On 06/02/2021 21.05, Philippe Mathieu-Daudé wrote: Travis-CI seems to have enforced memory limit on containers, and the 'GCC check-tcg' job started to fail [*]: [2041/3679] Compiling C++ object libcommon.fa.p/disas_nanomips.cpp.o FAILED: libcommon.fa.p/disas_nanomips.cpp.o {standard

[PATCH v8 28/35] Hexagon (target/hexagon) TCG for floating point instructions

The imported code uses host floating point. We override them to use qemu softfloat Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 121 +++ 1 file changed, 121 insertions(+) diff --git a/target/hexagon/gen_tcg.h

[PULL v9 12/13] confidential guest support: Alter virtio default properties for protected guests

The default behaviour for virtio devices is not to use the platforms normal DMA paths, but instead to use the fact that it's running in a hypervisor to directly access guest memory. That doesn't work if the guest's memory is protected from hypervisor access, such as with AMD's SEV or POWER's PEF.

[PATCH v8 31/35] Hexagon (tests/tcg/hexagon) TCG tests - multiarch

Enable multiarch tests for Hexagon Modify tests/tcg/configure.sh Add reference files to tests/tcg/hexagon Signed-off-by: Taylor Simpson --- tests/tcg/configure.sh| 4 +- tests/tcg/hexagon/Makefile.target | 30 ++ tests/tcg/hexagon/float_convs.ref | 748

[PULL v9 00/13] Cgs patches

The following changes since commit 5b19cb63d9dfda41b412373b8c9fe14641bcab60: Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210205' in= to staging (2021-02-05 22:59:12 +) are available in the Git repository at: https://gitlab.com/dgibson/qemu.git tags/cgs-pull-request

[PATCH v8 20/35] Hexagon (target/hexagon) generator phase 2 - generate header files

Python scripts generate the following files helper_protos_generated.h.inc For each instruction we create DEF_HELPER function prototype helper_funcs_generated.c.inc For each instruction we create the helper function definition tcg_funcs_generated.c.inc For each

[PATCH v8 27/35] Hexagon (target/hexagon) TCG for instructions with multiple definitions

Helpers won't work if there are multiple definitions, so we override these instructions using #define fGEN_TCG_. Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 198 +++ 1 file changed, 198 insertions(+) create mode 100644

[PATCH v8 35/35] Add Dockerfile for hexagon

From: Alessandro Di Federico Signed-off-by: Alessandro Di Federico Tested-by: Taylor Simpson --- .../debian-hexagon-cross-build-local.docker| 18 +++ .../debian-hexagon-cross.build-toolchain.sh| 141 + .../docker/dockerfiles/debian-hexagon-cross.docker |

[PATCH v8 25/35] Hexagon (target/hexagon) instruction classes

Determine legal VLIW slots for each instruction Signed-off-by: Taylor Simpson --- target/hexagon/iclass.h| 50 ++ target/hexagon/iclass.c| 73 ++ target/hexagon/imported/iclass.def | 51

[PATCH v8 34/35] Hexagon build infrastructure

Add file to default-configs Add hexagon to meson.build Add hexagon to target/meson.build Add target/hexagon/meson.build Change scripts/qemu-binfmt-conf.sh We can build a hexagon-linux-user target and run programs on the Hexagon scalar core. With hexagon-linux-clang installed, "make check-tcg"

[PATCH v8 21/35] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree

Run the C preprocessor across the instruction definition and encoding files to expand macros and prepare the iset.py file. The resulting fill contains python data structures used to build the decode tree. Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé ---

[PATCH v8 24/35] Hexagon (target/hexagon) macros

macros to interface with the generator macros referenced in instruction semantics Signed-off-by: Taylor Simpson --- target/hexagon/macros.h | 592 1 file changed, 592 insertions(+) create mode 100644 target/hexagon/macros.h diff --git

[PATCH v8 30/35] Hexagon (linux-user/hexagon) Linux user emulation

Implementation of Linux user emulation for Hexagon Some common files modified in addition to new files in linux-user/hexagon Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- linux-user/hexagon/sockbits.h | 18 ++ linux-user/hexagon/syscall_nr.h | 322

[PATCH v8 26/35] Hexagon (target/hexagon) TCG generation

Include the generated files and set up the data structures Signed-off-by: Taylor Simpson --- target/hexagon/genptr.h | 25 target/hexagon/genptr.c | 331 2 files changed, 356 insertions(+) create mode 100644 target/hexagon/genptr.h create

[PATCH v8 23/35] Hexagon (target/hexagon) opcode data structures

Signed-off-by: Taylor Simpson --- target/hexagon/opcodes.h | 58 +++ target/hexagon/opcodes.c | 142 +++ 2 files changed, 200 insertions(+) create mode 100644 target/hexagon/opcodes.h create mode 100644 target/hexagon/opcodes.c diff

[PATCH v8 08/35] Hexagon (target/hexagon) GDB Stub

GDB register read and write routines Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/internal.h | 2 ++ target/hexagon/gdbstub.c | 47 +++ 2 files changed, 49 insertions(+)

[PATCH v8 09/35] Hexagon (target/hexagon) architecture types

Define types used in files imported from the Hexagon architecture library Signed-off-by: Taylor Simpson --- target/hexagon/hex_arch_types.h | 38 ++ 1 file changed, 38 insertions(+) create mode 100644 target/hexagon/hex_arch_types.h diff --git

[PATCH v8 32/35] Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc

Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/atomics.c | 139 ++ tests/tcg/hexagon/dual_stores.c | 60 ++ tests/tcg/hexagon/mem_noshuf.c| 328 tests/tcg/hexagon/misc.c | 380 ++

[PATCH v8 10/35] Hexagon (target/hexagon) instruction and packet types

The insn_t and packet_t are the interface between instruction decoding and TCG code generation Signed-off-by: Taylor Simpson --- target/hexagon/insn.h | 74 +++ 1 file changed, 74 insertions(+) create mode 100644 target/hexagon/insn.h diff --git

[PATCH v8 33/35] Hexagon (tests/tcg/hexagon) TCG tests - floating point

Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/fpstuff.c | 370 ++ tests/tcg/hexagon/Makefile.target | 1 + 2 files changed, 371 insertions(+) create mode 100644 tests/tcg/hexagon/fpstuff.c diff --git a/tests/tcg/hexagon/fpstuff.c

[PATCH v8 15/35] Hexagon (target/hexagon/arch.[ch]) utility functions

Signed-off-by: Taylor Simpson --- target/hexagon/arch.h | 34 ++ target/hexagon/arch.c | 300 ++ 2 files changed, 334 insertions(+) create mode 100644 target/hexagon/arch.h create mode 100644 target/hexagon/arch.c diff --git

[PATCH v8 16/35] Hexagon (target/hexagon/conv_emu.[ch]) utility functions

Signed-off-by: Taylor Simpson --- target/hexagon/conv_emu.h | 31 target/hexagon/conv_emu.c | 177 ++ 2 files changed, 208 insertions(+) create mode 100644 target/hexagon/conv_emu.h create mode 100644 target/hexagon/conv_emu.c diff --git

[PATCH v8 17/35] Hexagon (target/hexagon/fma_emu.[ch]) utility functions

Signed-off-by: Taylor Simpson --- target/hexagon/fma_emu.h | 36 +++ target/hexagon/fma_emu.c | 702 +++ 2 files changed, 738 insertions(+) create mode 100644 target/hexagon/fma_emu.h create mode 100644 target/hexagon/fma_emu.c diff --git

[PATCH v8 06/35] Hexagon (target/hexagon) register names

Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/hex_regs.h | 83 +++ 1 file changed, 83 insertions(+) create mode 100644 target/hexagon/hex_regs.h diff --git

[PATCH v8 05/35] Hexagon (disas) disassembler

Add hexagon to disas/meson.build Add disas/hexagon.c Add hexagon to include/disas/dis-asm.h Signed-off-by: Taylor Simpson Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé --- include/disas/dis-asm.h | 1 + disas/hexagon.c | 65

[PATCH v8 07/35] Hexagon (target/hexagon) scalar core helpers

The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson --- target/hexagon/helper.h| 88 target/hexagon/op_helper.c | 1064 2 files changed, 1152

[PATCH v8 00/35] Hexagon patch series

This series adds support for the Hexagon processor with Linux user support See patch 02 Hexagon README for detailed information. This series assumes int128_or() is implemented. https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg06004.html The series is also available at

[PATCH v8 19/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics

Run the C preprocessor across the instruction definition files and macro definition file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each

[PATCH v8 14/35] Hexagon (target/hexagon) instruction printing

Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/printinsn.h | 27 + target/hexagon/printinsn.c | 146 + 2 files changed, 173 insertions(+) create mode 100644 target/hexagon/printinsn.h create mode 100644

[PATCH v8 01/35] Hexagon Update MAINTAINERS file

Add Taylor Simpson as the Hexagon target maintainer Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d8b0bf..4130008 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -188,6

[PATCH v8 03/35] Hexagon (include/elf.h) ELF machine definition

Define EM_HEXAGON 164 Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/elf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/elf.h b/include/elf.h index 7a418ee..f4fa3c1 100644 ---

[PATCH v8 13/35] Hexagon (target/hexagon) instruction/packet decode

Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders

[PATCH v8 04/35] Hexagon (target/hexagon) scalar core definition

Add target state header, target definitions and initialization routines Signed-off-by: Taylor Simpson --- target/hexagon/cpu-param.h | 29 + target/hexagon/cpu.h | 159 +++ target/hexagon/cpu_bits.h | 58 + target/hexagon/internal.h | 35 +

[PATCH v8 11/35] Hexagon (target/hexagon) register fields

Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson --- target/hexagon/reg_fields.h | 36 target/hexagon/reg_fields_def.h.inc | 41 + target/hexagon/reg_fields.c

[PATCH v8 12/35] Hexagon (target/hexagon) instruction attributes

Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/attribs.h | 35 +++ target/hexagon/attribs_def.h.inc | 97 2 files changed, 132 insertions(+) create mode 100644 target/hexagon/attribs.h create

[PATCH v8 02/35] Hexagon (target/hexagon) README

Gives an introduction and overview to the Hexagon target Signed-off-by: Taylor Simpson --- target/hexagon/README | 235 ++ 1 file changed, 235 insertions(+) create mode 100644 target/hexagon/README diff --git a/target/hexagon/README

Re: [PULL v3 11/27] multi-process: setup PCI host bridge for remote device

On 06/02/2021 18.57, Philippe Mathieu-Daudé wrote: On 2/5/21 5:44 PM, Stefan Hajnoczi wrote: From: Jagannathan Raman PCI host bridge is setup for the remote device process. It is implemented using remote-pcihost object. It is an extension of the PCI host bridge setup by QEMU. Remote-pcihost

[PATCH v2 2/2] hw/ssi: xilinx_spips: Implement basic QSPI DMA support

From: Xuzhou Cheng ZynqMP QSPI supports SPI transfer using DMA mode, but currently this is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. Add a basic implementation of QSPI DMA functionality. Signed-off-by: Xuzhou Cheng

[PATCH v2 1/2] hw/ssi: xilinx_spips: Clean up coding convention issues

From: Xuzhou Cheng There are some coding convention warnings in xilinx_spips.c, as reported by: $ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c Let's clean them up. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell ---

[PATCH v2 0/2] ZynqMP QSPI supports SPI transfer using DMA mode, but currently this

From: Bin Meng is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. Add a basic implementation of QSPI DMA functionality. Changes in v2: - Remove unconnected TYPE_STREAM_SINK link property - Add a TYPE_MEMORY_REGION link property,

Re: [PATCH 0/3] hw/sd: sd: erase operation fixes

On Thu, Jan 28, 2021 at 2:43 PM Bin Meng wrote: > > From: Bin Meng > > This includes several fixes related to erase operation of a SD card. > > Based-on: > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=226785 > > > Bin Meng (3): > hw/sd: sd: Fix address check in sd_erase() >

[RFC PATCH 5/5] Enable the MTE support for KVM guest

Signed-off-by: Haibo Xu --- hw/arm/virt.c | 22 +++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 623d5e9397..c2358cf4c5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -79,6 +79,7 @@ #include "hw/virtio/virtio-iommu.h"

Re: [PATCH 3/3] virtio-net: graceful fallback to vhost=off for tap netdev

On 2021/2/5 下午9:38, Michael S. Tsirkin wrote: On Thu, Feb 04, 2021 at 10:29:15PM +0200, Yuri Benditovich wrote: Currently virtio-net silently clears features if they are not supported by respective vhost. This may create migration problems in future if vhost features on the source and

[PATCH v2 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec

The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson ---

[PATCH v2 11/16] tcg/s390x: Implement vector shift operations

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 12 ++--- tcg/s390x/tcg-target.c.inc | 93 +- 3 files changed, 99 insertions(+), 7 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h

[PATCH v2 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 7 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index dd11972ed2..13b9918276 100644 --- a/tcg/s390x/tcg-target.h +++

Re: [PATCH 3/3] virtio-net: graceful fallback to vhost=off for tap netdev

On 2021/2/5 上午4:29, Yuri Benditovich wrote: Currently virtio-net silently clears features if they are not supported by respective vhost. This may create migration problems in future if vhost features on the source and destination are different. Implement graceful fallback to no-vhost mode when

[PATCH v2 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations

These logical and arithmetic operations are optional but trivial. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 10 +- tcg/s390x/tcg-target.c.inc | 34 +- 3 files changed, 39

[PATCH v2 04/16] tcg/s390x: Add host vector framework

Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h

[PATCH v2 02/16] tcg/s390x: Change FACILITY representation

We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2:

[PATCH v2 01/16] tcg/s390x: Rename from tcg/s390

This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- meson.build | 2 -- tcg/{s390 => s390x}/tcg-target-con-set.h | 0 tcg/{s390 =>

[PATCH v2 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec

Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 35 ++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index

[PATCH v2 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec

NEON has 3 instructions implementing this 4 argument operation, with each insn overlapping a different logical input onto the destination register. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 22

[PATCH v2 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec

This is saturating add and subtract, signed and unsigned. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 24 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h

[RFC PATCH 2/5] Add basic MTE support to KVM guest

Enable the virt machine feature "mte" to work with KVM guest. This feature is still hiden from the user in this patch, and will be available in a later patch. Signed-off-by: Haibo Xu --- hw/arm/virt.c | 22 +++--- target/arm/cpu.c | 2 +- target/arm/kvm.c | 9

[PATCH v2 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec

This consists of the three immediate shifts: shli, shri, sari. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 27 +++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h

[RFC PATCH 3/5] Add APIs to get/set MTE tags

MTE spec provide instructions to retrieve the memory tags: (1) LDG, at 16 bytes granularity, and available in both user and kernel space; (2) LDGM, at 256 bytes granularity in maximum, and only available in kernel space To improve the performance, KVM has exposed the LDGM capability to

Re: [PATCH v3 00/70] TCI fixes and cleanups

Patchew URL: https://patchew.org/QEMU/20210208023752.270606-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210208023752.270606-1-richard.hender...@linaro.org Subject: [PATCH v3 00/70]

[PATCH v2 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations

These logical and arithmetic operations are optional, but are trivial to accomplish with the existing infrastructure. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.h | 10 +- tcg/arm/tcg-target.c.inc | 38

[RFC PATCH 1/5] Update Linux headers with new MTE support

Signed-off-by: Haibo Xu --- linux-headers/linux/kvm.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 020b62a619..6a291a9a35 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1056,6 +1056,7

[PATCH v2 06/15] tcg/arm: Implement minimal vector operations

Implementing dup2, add, sub, and, or, xor as the minimal set. This allows us to actually enable neon in the header file. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 3 + tcg/arm/tcg-target-con-str.h | 2 + tcg/arm/tcg-target.h | 6 +-

[RFC PATCH 0/5] target/arm: Add MTE support to KVM guest

This series add support for MTE(Memory Tagging Extension)[1] in KVM guest. It's based on Steven Price's kernel KVM patches V7[2], and has been tested to ensure that test case[3] can be passed in a KVM guest. Basic pre-copy migration test also passed between two MTE enabled kvm guest. This is a

Re: [PATCH] vhost: Unbreak SMMU and virtio-iommu on dev-iotlb support

On 2021/2/5 下午11:31, Peter Xu wrote: On Fri, Feb 05, 2021 at 09:33:29AM +0100, Auger Eric wrote: Hi, On 2/5/21 4:16 AM, Jason Wang wrote: On 2021/2/5 上午3:12, Peter Xu wrote: Previous work on dev-iotlb message broke vhost on either SMMU Have a quick git grep and it looks to me v3 support

[PATCH v2 05/15] tcg/arm: Implement tcg_out_dup*_vec

Most of dupi is copied from tcg/aarch64, which has the same encoding for AdvSimdExpandImm. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 283 +-- 1 file changed, 275 insertions(+), 8 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc

[PATCH v2 13/16] tcg: Expand usadd/ussub with umin/umax

For usadd, we only have to consider overflow. Since ~B + B == -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 37

[PATCH v2 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec

This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index

[PATCH v2 02/15] tcg/arm: Add host vector framework

Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h |

[PATCH v2 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 25 + 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 3026a4d8c4..efa32f348c 100644 ---

[PATCH v2 00/16] tcg/s390x: host vector support

Changes for v2: * Rebase on master, now that all prereq are upstream. r~ Richard Henderson (16): tcg/s390x: Rename from tcg/s390 tcg/s390x: Change FACILITY representation tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg tcg/s390x: Add host vector framework tcg/s390x:

[RFC PATCH 4/5] Add migration support for KVM guest with MTE

To make it easier to keep the page tags sync with the page data, tags for one page are appended to the data during ram save iteration. This patch only add the pre-copy migration support. Post-copy and compress as well as zero page saving are not supported yet. Signed-off-by: Haibo Xu ---

[PATCH v2 00/15] tcg/arm: host neon support

Generate NEON instructions for tcg vector operations. Changes for v2: * Rebase on master, now that all prereq are upstream. r~ Richard Henderson (15): tcg: Change parameters for tcg_target_const_match tcg/arm: Add host vector framework tcg/arm: Implement tcg_out_ld/st for vector types

[PATCH v2 08/16] tcg/s390x: Implement minimal vector operations

Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 154 - 1 file changed, 150 insertions(+), 4 deletions(-) diff --git

[PATCH v2 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 117 + 1 file changed, 105 insertions(+), 12 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4656efea83..df10ee0feb 100644 ---

[PATCH v3 63/70] tcg/tci: Implement movcond

When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c| 16 +++-

[PATCH v2 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec

This is minimum and maximu, signed and unsigned. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 24 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index

[PATCH v2 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg

They are rightly values in the same enumeration. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 28 +++- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git

[PATCH v2 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 20 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target-con-set.h

[PATCH v3 62/70] tcg/tci: Implement goto_ptr

This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Signed-off-by:

[PATCH v2 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec

Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.opc.h | 1 + tcg/arm/tcg-target.c.inc | 15

[PATCH v2 04/15] tcg/arm: Implement tcg_out_mov for vector types

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 50 +++- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index ca9a71ca64..20088ac61a 100644 --- a/tcg/arm/tcg-target.c.inc +++

[PATCH v2 06/16] tcg/s390x: Implement tcg_out_mov for vector types

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 72 +++--- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index df10ee0feb..fdf7475b2d 100644 --- a/tcg/s390x/tcg-target.c.inc

[PATCH v3 55/70] tcg/tci: Split out tcg_out_op_v

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f93772f01f..eeafec6d44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc

[PATCH v2 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 6 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index cfbadad72c..94d768f249 100644 --- a/tcg/arm/tcg-target.h +++

[PATCH v2 03/15] tcg/arm: Implement tcg_out_ld/st for vector types

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 70 1 file changed, 64 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9bb354abce..ca9a71ca64 100644 --- a/tcg/arm/tcg-target.c.inc +++

[PATCH v2 07/16] tcg/s390x: Implement tcg_out_dup*_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 - 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index fdf7475b2d..01118d9993 100644 ---

[PATCH v3 51/70] tcg/tci: Split out tcg_out_op_rrrrrr

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++ 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8cc63124d4..f7595fbd65 100644 --- a/tcg/tci/tcg-target.c.inc +++

[PATCH v3 70/70] gitlab: Enable cross-i386 builds of TCI

We're currently only testing TCI with a 64-bit host -- also test with a 32-bit host. Enable a selection of softmmu and user-only targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each. Signed-off-by: Richard Henderson --- .gitlab-ci.d/crossbuilds.yml| 17

[PATCH v2 01/15] tcg: Change parameters for tcg_target_const_match

Change the return value to bool, because that's what is should have been from the start. Pass the ct mask instead of the whole TCGArgConstraint, as that's the only part that's relevant. Change the value argument to int64_t. We will need the extra width for 32-bit hosts wanting to match vector

[Bug 1914696] Re: aarch64: migration failed: Segmentation fault (core dumped)

https://patchew.org/QEMU/20210203161340.55210-1-aa...@os.amperecomputing.com/ works for me. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to the bug report. https://bugs.launchpad.net/bugs/1914696 Title: aarch64: migration failed:

[PATCH v3 49/70] tcg/tci: Split out tcg_out_op_rrrbb

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8eda159dde..6c743a8fbd 100644 --- a/tcg/tci/tcg-target.c.inc +++

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