Vladimir Sementsov-Ogievskiy writes:
> Hmm. An idea. What we want: read more than one character at a time, as
> it's inefficient. May be instead of modifying monitor_can_read() and
> therefore influence monitor behavior in unpredictable way, we'd better
> add a separate read-cache, and just read
Cc: ACPI maintainers for additional expertise.
Daniel Henrique Barboza writes:
> Hi,
>
> Recent changes in pseries code (not yet pushed, available at David's
> ppc-for-6.0) are using the QAPI event MEM_UNPLUG_ERROR to report memory
> hotunplug errors in the pseries machine.
>
> The pseries
From: Bin Meng
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
Changes in v2:
-
Thank you very much.
Best regards.
Peter Maydell 于2021年3月5日周五 下午7:57写道：
> On Thu, 25 Feb 2021 at 05:36, schspa wrote:
> >
> > At the moment the following QEMU command line triggers an assertion
> > failure On xlnx-versal SOC:
> > qemu-system-aarch64 \
> > -machine xlnx-versal-virt
On 3/5/21 3:54 PM, Keith Packard via wrote:
I don't know of any implementation in hardware or software that supports
modifying this value. I'm not sure we need to support this in the
semihosting code for qemu as I'm pretty sure getting qemu to support
dynamic XLEN values would be a large project
On Fri, Mar 5, 2021 at 4:10 PM Samuel Thibault
wrote:
> Doug Evans, le ven. 05 mars 2021 16:05:05 -0800, a ecrit:
> > Given that the code is not supposed to be able to know brackets were
> present
> > (they're stripped off early on), what does the above mean w.r.t. the
> guest?
> > For the host
Doug Evans, le ven. 05 mars 2021 16:05:05 -0800, a ecrit:
> Given that the code is not supposed to be able to know brackets were present
> (they're stripped off early on), what does the above mean w.r.t. the guest?
> For the host we can have "" mean listen on both IPv4 and IPv6
> (by default,
On Fri, Mar 5, 2021 at 1:28 PM Samuel Thibault
wrote:
> Daniel P. Berrangé, le mer. 03 mars 2021 18:11:41 +, a ecrit:
> > On Wed, Mar 03, 2021 at 10:06:50AM -0800, Doug Evans wrote:
> > > On Sun, Feb 28, 2021 at 1:40 PM Samuel Thibault <
> samuel.thiba...@gnu.org>
> > > wrote:
> > >
> > > >
There is no reason to not have memory_region_to_absolute_addr()
work with a const MemoryRegion. Else we get:
softmmu/memory.c: error: passing argument 1 of ‘memory_region_to_absolute_addr’
discards ‘const’ qualifier from pointer target type
[-Werror=discarded-qualifiers]
| myaddr =
Peter Maydell writes:
> For semihosting for Arm what matters is "what state is the core
> in at the point where it makes the semihosting SVC/HLT/etc insn?".
Ok, that means we *aren't* talking about -mabi=ilp32, which is good --
in my current picolibc implementation, the semihosting code uses a
Currently AdressSpace are display in 'info mtree' based on
the physical address of their first MemoryRegion. This is
rather confusing.
Provide a 'base' address argument to mtree_print_mr() and
use it in mtree_info() to display AdressSpace always based
at address 0.
Display behavior of
The 'base' argument of mtree_print_mr() actually represents
an offset, not a base address. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/memory.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/softmmu/memory.c b/softmmu/memory.c
index
Hi,
I have been confused for some years by AddressSpace being displayed
based on the physical address of their first MemoryRegion.
The actual fix is quite trivial for my needs, but I might not see
all the possible side effects. Altough the change are restricted
to mtree_info() which is only
On Fri, 5 Mar 2021 at 20:22, Keith Packard wrote:
>
> Peter Maydell writes:
>
> > Also, you don't seem to have the correct "is the CPU in
> > 32-bit or 64-bit mode" test here: you cannot rely on target_ulong
> > being the right size, you must make a runtime check.
>
> Do you mean whether a dual
itory at:
>
> https://gitlab.com/cohuck/qemu.git tags/s390x-20210305
>
> for you to fetch changes up to 39d5d1404ed695f4a1cd2b117a6cf2d92dd8e8b9:
>
> target/s390x/kvm: Simplify debug code (2021-03-04 14:19:08 +0100)
>
> --
On Fri, Mar 5, 2021 at 1:51 PM Doug Evans wrote:
> On Fri, Mar 5, 2021 at 1:28 PM Samuel Thibault
> wrote:
>
>> Daniel P. Berrangé, le mer. 03 mars 2021 18:11:41 +, a ecrit:
>> > On Wed, Mar 03, 2021 at 10:06:50AM -0800, Doug Evans wrote:
>> > > On Sun, Feb 28, 2021 at 1:40 PM Samuel
On Fri, Mar 05, 2021 at 11:16:34AM +0100, David Hildenbrand wrote:
> Let's provide a way to control the use of RAM_NORESERVE via memory
> backends using the "reserve" property which defaults to true (old
> behavior).
>
> Only POSIX supports setting the flag (and Linux support is checked at
>
On Fri, Mar 5, 2021 at 1:28 PM Samuel Thibault
wrote:
> Daniel P. Berrangé, le mer. 03 mars 2021 18:11:41 +, a ecrit:
> > On Wed, Mar 03, 2021 at 10:06:50AM -0800, Doug Evans wrote:
> > > On Sun, Feb 28, 2021 at 1:40 PM Samuel Thibault <
> samuel.thiba...@gnu.org>
> > > wrote:
> > >
> > > >
On Tue, Mar 02, 2021 at 06:35:44PM +0100, Halil Pasic wrote:
> Since the virtio-gpu-ccw device depends on the hw-display-virtio-gpu
> module, which provides the type virtio-gpu-device, packaging the
> hw-display-virtio-gpu module as a separate package that may or may not
> be installed along with
Daniel P. Berrangé, le mer. 03 mars 2021 18:11:41 +, a ecrit:
> On Wed, Mar 03, 2021 at 10:06:50AM -0800, Doug Evans wrote:
> > On Sun, Feb 28, 2021 at 1:40 PM Samuel Thibault
> > wrote:
> >
> > > > + Examples:
> > > > + hostfwd_add net0 tcp:127.0.0.1:10022-:22
> > > > + hostfwd_add net0
Hi,
On 3/4/21 9:39 AM, Joel Stanley wrote:
Test MTD images from the OpenBMC project on AST2400 and AST2500 SoCs
from ASPEED, by booting Palmetto and Romulus BMC machines.
The images are fetched from OpenBMC's release directory on github.
Co-developed-by: Cédric Le Goater
Reviewed-by: Cédric
Hi,
On 3/4/21 9:39 AM, Joel Stanley wrote:
This tests a Debian multi-soc arm32 Linux kernel on the AST2600 based
Tacoma BMC machine.
There is no root file system so the test terminates when boot reaches
the stage where it attempts and fails to mount something.
Signed-off-by: Joel Stanley
---
Peter Maydell writes:
> Also, you don't seem to have the correct "is the CPU in
> 32-bit or 64-bit mode" test here: you cannot rely on target_ulong
> being the right size, you must make a runtime check.
Do you mean whether a dual aarch64/arm core is in arm or aarch64 mode,
or whether an aarch64
Alex Bennée writes:
> I'm not sure this every worked properly and it's certainly not
> exercised by check-tcg or Peter's semihosting tests. Hoist it into
> it's own helper function and attempt to validate the results in the
> linux-user semihosting test at the least.
The patch is mostly code
On 3/5/21 3:48 AM, Kevin Wolf wrote:
> The 'name' option for NBD exports is optional. Add a note that the
> default for the option is the node name (people could otherwise expect
> that it's the empty string like for qemu-nbd).
>
> Signed-off-by: Kevin Wolf
> ---
>
Public bug reported:
Whilst creating a flash device is recommended, -bios is extremely
useful in many cases as it automatically searches $PREFIX/share/qemu
rather than requiring the caller (be it a human or a script) to work out
where that directory is for the QEMU being called and prepend it to
On Fri, Mar 5, 2021 at 6:31 AM Alex Bennée wrote:
>
> Hi,
>
> Another week another testing/next roll. The series includes a couple
> of my proposed documentation tweaks (including the re-org of the devel
> manual). We also enable testing for the hexagon linux-user target to
> avoid bitrot. I've
On Fri, 5 Mar 2021 at 15:11, Markus Armbruster wrote:
>
> The following changes since commit fe352f5c0056b4d21ae033ec49acc0bce9897e53:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210304-pull-request'
> into staging (2021-03-04 12:58:50 +)
>
> are available in the Git
On 2/23/21 3:12 AM, Philippe Mathieu-Daudé wrote:
Fix a trivial incorrect usage of variable argument macros detected
by Coverity (missing_va_end: va_end was not called for ap).
Fixes: Coverity CID 1446720 (VARARGS)
Fixes: e3c00c2ed75 ("Hexagon (target/hexagon) opcode data structures")
Patchew URL:
https://patchew.org/QEMU/20210305183857.3120188-1-wuhao...@google.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210305183857.3120188-1-wuhao...@google.com
Subject: [PATCH 0/4] hw/misc: Add NPCM7XX
On 2/19/21 5:57 AM, Philippe Mathieu-Daudé wrote:
Commit 3e7a84eeccc ("Hexagon build infrastructure") added Hexagon
definitions that should be poisoned on target independent device
code, but forgot to update "exec/poison.h". Do it now.
Signed-off-by: Philippe Mathieu-Daudé
---
On 3/4/21 9:37 AM, Taylor Simpson wrote:
Fixes: a646e99cb90 ("Hexagon (target/hexagon) macros")
Eliminate the following Coverity CIDs (Bad bit shift operation)
325227
325292
325425
325526
325561
325564
325578
325637
325736
325748
325786
This patch adds fan_splitters (split IRQs) in NPCM7XX boards. Each fan
splitter corresponds to 1 PWM output and can connect to multiple fan
inputs (MFT devices).
In NPCM7XX boards(NPCM750 EVB and Quanta GSJ boards), we initializes
these splitters and connect them to their corresponding modules
This patch adds testing of PWM fan RPMs in the existing npcm7xx pwm
test. It tests whether the MFT module can measure correct fan values
for a PWM fan in NPCM7XX boards.
Reviewed-by: Doug Evans
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
---
tests/qtest/npcm7xx_pwm-test.c | 205
This patch adds GPIOs in NPCM7xx PWM module for its duty values.
The purpose of this is to connect it to the MFT module to provide
an input for measuring a PWM fan's RPM. Each PWM module has
NPCM7XX_PWM_PER_MODULE of GPIOs, each one corresponds to
one PWM instance and can connect to multiple fan
Hi,
Recent changes in pseries code (not yet pushed, available at David's
ppc-for-6.0) are using the QAPI event MEM_UNPLUG_ERROR to report memory
hotunplug errors in the pseries machine.
The pseries machine is also using a timeout to cancel CPU hotunplugs that
takes too long to finish (in which
On 3/5/21 9:31 AM, Nicolas Surbayrole wrote:
The guest binary and libraries are not always mapped with the
executable bit in the host process. The guest may read a
/proc/self/maps with no executable address range. The
patch bases the perm fields against the guest permission inside
Qemu.
Patchew URL:
https://patchew.org/QEMU/20210305170045.869437-1-kbast...@mail.uni-paderborn.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210305170045.869437-1-kbast...@mail.uni-paderborn.de
Subject: [PATCH v3
This patch adds Multi Function Timer (MFT) module for NPCM7XX Soc.
This module is mainly used to configure PWM fans. It has just enough
functionality to make the PWM fan kernel module work.
The module takes two input, the max_rpm of a fan (modifiable via QMP)
and duty cycle (a GPIO from the PWM
Richard Henderson writes:
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Patchew URL:
https://patchew.org/QEMU/20210305171515.1038-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210305171515.1038-1-peter.mayd...@linaro.org
Subject: [PULL 00/49] target-arm
This patch set implements the Tachometer (a.k.a Multi Functional Timer/MFT)
device in NPCM7XX SoC. This device is used by NPCM7XX boards to measure
the RPM of PWM fans.
To provide the RPM of a certain fan, since RPM = MAX_RPM * duty_percentage.
We convert the duty output in NPCM7XX PWM module
Richard Henderson writes:
> Use explicit casts for ext32u opcodes, and allow truncation
> to happen for other users.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
On Fri, 5 Mar 2021 at 18:07, Laurent Vivier wrote:
> Le 05/03/2021 à 18:53, Peter Maydell a écrit :
> > Alternatively, if anybody has a bright idea for how to get the kernel
> > to tell us how it's invoking us (ELF auxv entry???) maybe we could make
> > a proposal to the kernel folks.
>
> My
Le 05/03/2021 à 18:53, Peter Maydell a écrit :
> On Sun, 14 Feb 2021 at 15:34, Michael Tokarev wrote:
>> As known for a long time, qemu's linux-user, when invoked in context of
>> binfmt-misc mechanism,
>> does not preserve the original argv[0] element, so some software which
>> relies on
Richard Henderson writes:
> Use explicit casts for ext16s opcodes.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
There is a bug in qcow2: host cluster can be discarded (refcount
becomes 0) and reused during data write. In this case data write may
pollute another cluster (recently allocated) or even metadata.
To fix the issue let's track inflight writes to host cluster in the
hash table and consider new
We are going to reuse the script to generate a qcow2_ function in
further commit. Prepare the script now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/block-coroutine-wrapper.py | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
Richard Henderson writes:
> Use explicit casts for ext8s opcodes.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Richard Henderson writes:
> This includes bswap16 and bswap32.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Simple test:
- start writing to allocated cluster A
- discard this cluster
- write to another unallocated cluster B (it's allocated in same place
where A was allocated)
- continue writing to A
For now last action pollutes cluster B which is a bug fixed by the
following commit.
For now,
Richard Henderson writes:
> Use explicit casts for ext16u opcodes, and allow truncation
> to happen with the store for st16 opcodes, and with the call
> for bswap16 opcodes.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Compressed writes are unaligned to 512, which works very slow in
O_DIRECT mode. Let's use the cache.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/coroutines.h | 3 +
block/qcow2.h | 4 ++
block/qcow2-refcount.c | 10 +++
block/qcow2.c | 158
Richard Henderson writes:
> In all cases restricted to 64-bit hosts, tcg_read_r is
> identical. We retain the 64-bit symbol for the single
> case of INDEX_op_qemu_st_i64.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
On 3/2/21 6:57 PM, Richard Henderson wrote:
> Use the provided cpu_ldst.h interfaces. This fixes the build vs
> the unconverted uses of g2h(), adds missed memory trace events,
> and correctly recognizes when a SIGSEGV belongs to the guest via
> set_helper_retaddr().
>
> Fixes: 3e8f1628e864
>
Richard Henderson writes:
> This includes ext8s, ext8u, ext16s, ext16u.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
On Sun, 14 Feb 2021 at 15:34, Michael Tokarev wrote:
> As known for a long time, qemu's linux-user, when invoked in context of
> binfmt-misc mechanism,
> does not preserve the original argv[0] element, so some software which relies
> on argv[0] is
> not functioning under qemu-user. When run
The AN505 and AN521 don't have any read-only memory, but the AN524
does; add a flag to ROMInfo to mark a region as ROM.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210215115138.20465-19-peter.mayd...@linaro.org
---
hw/arm/mps2-tz.c | 6 ++
1 file changed, 6
Instead of hardcoding the MachineClass default_ram_size and
default_ram_id fields, set them on class creation by finding the
entry in the RAMInfo array which is marked as being the QEMU system
RAM.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
Richard Henderson writes:
> This includes add, sub, mul, and, or, xor.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Richard Henderson writes:
> Use explicit casts for ext32s opcodes.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
The AN505 and AN521 have the same device layout, but the AN524 is
somewhat different. Allow for more than one PPCInfo array, which can
be selected based on the board type.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210215115138.20465-16-peter.mayd...@linaro.org
The armv7m_load_kernel() function takes a mem_size argument which it
expects to be the size of the memory region at guest address 0. (It
uses this argument only as a limit on how large a raw image file it
can load at address zero).
Instead of hardcoding this value, find the RAMInfo corresponding
Richard Henderson writes:
> Use explicit casts for ext8u opcodes, and allow truncation
> to happen with the store for st8 opcodes.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Richard Henderson writes:
> The use in tcg_tb_lookup is given a random pc that comes from the pc
> of a signal handler. Do not assert that the pointer is already within
> the code gen buffer at all, much less the writable mirror of it.
>
> Fixes: db0c51a3803
> Signed-off-by: Richard Henderson
Add support for the mps3-an524 board; this is an SSE-200 based FPGA
image, like the existing mps2-an521. It has a usefully larger amount
of RAM, and a PL031 RTC, as well as some more minor differences.
In real hardware this image runs on a newer generation of the FPGA
board, the MPS3 rather than
We create an OR gate to wire together the overflow IRQs for all the
UARTs on the board; this has to have twice the number of inputs as
there are UARTs, since each UART feeds it a TX overflow and an RX
overflow interrupt line. Replace the hardcoded '10' with a
calculation based on the size of the
Richard Henderson writes:
> Use the provided cpu_ldst.h interfaces. This fixes the build vs
> the unconverted uses of g2h(), adds missed memory trace events,
> and correctly recognizes when a SIGSEGV belongs to the guest via
> set_helper_retaddr().
>
> Fixes: 3e8f1628e864
> Tested-by:
Richard Henderson writes:
> Allow other places in tcg to restart with a smaller tb.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
The AN524 has a USB controller (an ISP1763); we don't have a model of
it but we should provide a stub "unimplemented-device" for it. This
is slightly complicated because the USB controller shares a PPC port
with the ethernet controller.
Implement a make_* function which provides creates a
The AN524 has more interrupt lines than the AN505 and AN521; make
numirq board-specific rather than a compile-time constant.
Since the difference is small (92 on the current boards and 95 on the
new one) we don't dynamically allocate the cpu_irq_splitter[] array
but leave it as a fixed length
On Thu, Mar 04, 2021 at 06:11:26PM +, Alex Bennée wrote:
>
> Stefan Hajnoczi writes:
>
> > On Wed, Mar 03, 2021 at 05:01:05PM -0500, Michael S. Tsirkin wrote:
> >> On Wed, Mar 03, 2021 at 02:50:11PM +, Alex Bennée wrote:
> >> Also, are we sure it's ok to send the messages and then send
Implement cache for small sequential unaligned writes, so that they may
be cached until we get a complete cluster and then write it.
The cache is intended to be used for backup to qcow2 compressed target
opened in O_DIRECT mode, but can be reused for any similar (even not
block-layer related)
The mps2-tz code uses PPCPortInfo data structures to define what
devices are present and how they are wired up. Currently we use
these to specify device types and addresses, but hard-code the
interrupt line wiring in each make_* helper function. This works for
the two boards we have at the
The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The
FPGAIO device is similar on both sets of boards, but the LED0
register has correspondingly more bits that have an effect. Add a
device property for number of LEDs.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
The guest binary and libraries are not always mapped with the
executable bit in the host process. The guest may read a
/proc/self/maps with no executable address range. The
patch bases the perm fields against the guest permission inside
Qemu.
Signed-off-by: Nicolas Surbayrole
---
The AN524 has a different SYSCLK frequency from the AN505 and AN521;
make the SYSCLK frequency a field in the MPS2TZMachineClass rather
than a compile-time constant so we can support the AN524.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
We are going to implement compressed write cache to improve performance
of compressed backup when target is opened in O_DIRECT mode. We
definitely want to flush the cache at backup finish, and if flush fails
it should be reported as block-job failure, not simply ignored in
bdrv_close(). So, teach
MPS3 boards have an extra SWITCH register in the FPGAIO block which
reports the value of some switches. Implement this, governed by a
property the board code can use to specify whether whether it exists.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard
On 05/03/21 17:52, Daniele Buono wrote:
diff --git a/net/slirp.c b/net/slirp.c
index be914c0be0..82e05d2c01 100644
--- a/net/slirp.c
+++ b/net/slirp.c
@@ -174,23 +174,42 @@ static int64_t net_slirp_clock_get_ns(void *opaque)
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
+typedef
Currently the MPS2 SCC device implements a fixed number of OSCCLK
values (3). The variant of this device in the MPS3 AN524 board has 6
OSCCLK values. Switch to using a PROP_ARRAY, which allows board code
to specify how large the OSCCLK array should be as well as its
values.
With a
The series inherits "[PATCH 0/7] qcow2: compressed write cache"
(changed a lot, the cache is rewritten), and
"[PATCH v2(RFC) 0/3] qcow2: fix parallel rewrite and "
(the fix solution is taken from v1 instead, as the are problems with v2,
described in cover letter)
Core changes in v3:
- cache is
The macro draw_line_func is used only once; just expand it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20210215103215.4944-10-peter.mayd...@linaro.org
---
hw/display/omap_lcdc.c | 4 +---
1 file changed, 1 insertion(+), 3
The function tc6393xb_draw_graphic32() is called in exactly one place,
so just inline the function body at its callsite. This allows us to
drop the template header entirely.
The code move includes a single added space after 'for' to fix
the coding style.
Signed-off-by: Peter Maydell
We only include the template header once, so just inline it into the
source file for the device.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20210215103215.4944-9-peter.mayd...@linaro.org
---
hw/display/omap_lcd_template.h | 154
Update old infocenter.arm.com URLs to the equivalent developer.arm.com
ones (the old URLs should redirect, but we might as well avoid the
redirection notice, and the new URLs are pleasantly shorter).
This commit covers the links to the MPS2 board TRM, the various
Application Notes, the IoTKit and
From: Philippe Mathieu-Daudé
We hint the 'has_rpu' property is no longer required since commit
6908ec448b4 ("xlnx-zynqmp: Properly support the smp command line
option") which was released in QEMU v2.11.0.
Beside, this device is marked 'user_creatable = false', so the
only thing that could be
The AN505 and AN521 have the same layout of RAM; the AN524 does not.
Replace the current hard-coding of where the RAM is and which parts
of it are behind which MPCs with a data-driven approach.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
From: Doug Evans
Reviewed-by: Hao Wu
Reviewed-by: Avi Fishman
Reviewed-by: Peter Maydell
Signed-off-by: Doug Evans
Message-id: 20210218212453.831406-4-...@google.com
Signed-off-by: Peter Maydell
---
tests/qtest/npcm7xx_emc-test.c | 862 +
Add brief documentation of the new mps3-an524 board.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210215115138.20465-24-peter.mayd...@linaro.org
---
docs/system/arm/mps2.rst | 24 ++--
1 file changed, 18
From: Doug Evans
This is a 10/100 ethernet device that has several features.
Only the ones needed by the Linux driver have been implemented.
See npcm7xx_emc.c for a list of unimplemented features.
Reviewed-by: Hao Wu
Reviewed-by: Avi Fishman
Signed-off-by: Doug Evans
Message-id:
Move the specification of the IRQ information for the uart, ethernet,
dma and spi devices to the data structures. (The other devices
handled by the PPCPortInfo structures don't have any interrupt lines
we need to wire up.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
From: Philippe Mathieu-Daudé
The STATUS register will be reset to IDLE in
cnpcm7xx_smbus_enter_reset(), no need to preset
it in instance_init().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Hao Wu
Message-id: 20210228224813.312532-1-f4...@amsat.org
Signed-off-by: Peter Maydell
---
The AN524 has a PL031 RTC, which we have a model of; provide it
rather than an unimplemented-device stub.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210215115138.20465-23-peter.mayd...@linaro.org
---
hw/arm/mps2-tz.c | 22
The AN524 version of the SCC interface has different behaviour for
some of the CFG registers; implement it.
Each board in this family can have minor differences in the meaning
of the CFG registers, so rather than trying to specify all the
possible semantics via individual device properties, we
-riscv-to-apply-20210304' into staging (2021-03-05
10:47:46 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210305
for you to fetch changes up to 2c669ff88ec6733420a000103a2b8b9e93df4945:
hw/arm/mps2: Update old
From: Rebecca Cran
Enable FEAT_SSBS for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran
Reviewed-by: Richard Henderson
Message-id: 20210216224543.16142-4-rebe...@nuviainc.com
[PMM: fix typo causing compilation failure]
Signed-off-by: Peter Maydell
---
target/arm/cpu.c | 4
1 file
On the MPS2 boards, the first 32 interrupt lines are entirely
internal to the SSE; interrupt lines for devices outside the SSE
start at 32. In the application notes that document each FPGA image,
the interrupt wiring is documented from the point of view of the CPU,
so '0' is the first of the
In the mps2-tz board code, we handle devices whose interrupt lines
must be wired to all CPUs by creating IRQ splitter devices for the
AN521, because it has 2 CPUs, but wiring the device IRQ directly to
the SSE/IoTKit input for the AN505, which has only 1 CPU.
We can avoid making an explicit check
From: Marcin Juszkiewicz
Let add 'max' cpu while work goes on adding newer CPU types than
Cortex-A72. This allows us to check SVE etc support.
Signed-off-by: Marcin Juszkiewicz
Acked-by: Leif Lindholm
Reviewed-by: Philippe Mathieu-Daudé
Message-id:
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