The AN547 configures the SSE-300 with a different initsvtor0
setting from its default; make this a board-specific setting.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-42-peter.
From: Philippe Mathieu-Daudé
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
A KVM-only build won't be able to run TCG cpus, move the
v7A CPU definitions to cpu_tcg.c.
Add support for the mps3-an547 board; this is an SSE-300 based
FPGA image that runs on the MPS3.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-43-peter.mayd...@linaro.org
---
hw/arm/mps2-tz.c | 146
Add a simple qtest to exercise the new system counter device in the
SSE-300.
We'll add tests of the system timer device here too, so this includes
scaffolding (register definitions, etc) for those.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daud
The AN547 runs the APB peripherals outside the SSE-300 on a different
and slightly slower clock than it runs the SSE-300 with. Support
making the APB peripheral clock frequency board-specific. (For our
implementation only the UARTs actually take a clock.)
Signed-off-by: Peter Maydell
Tested-by:
On Mar 8 16:37, Stefan Hajnoczi wrote:
> On Tue, Mar 02, 2021 at 12:10:37PM +0100, Klaus Jensen wrote:
> > +static void nvme_dsm_cancel(BlockAIOCB *aiocb)
> > +{
> > +NvmeDSMAIOCB *iocb = container_of(aiocb, NvmeDSMAIOCB, common);
> > +
> > +/* break loop */
> > +iocb->curr.len = 0;
>
Implement the minor changes required to the SCC block for AN547 images:
* CFG2 and CFG5 exist (like AN524)
* CFG3 is reserved (like AN524)
* CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this
in the TODO comment
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Revie
Now we have sufficiently parameterised the code, we can add SSE-300
support by adding a new entry to the armsse_variants[] array.
Note that the main watchdog (unlike the s32k watchdog) in the SSE-300
is a different device from the CMSDK watchdog; we don't have a model
of it so we leave it as a TYP
Add brief documentation of the new mps3-an547 board.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20210219144617.4782-44-peter.mayd...@linaro.org
---
docs/system/arm/mps2.rst | 6 --
1 file changed, 4 insertions(+), 2 deleti
The SSE-300 has four timers of type TYPE_SSE_TIMER; add support in
the code for having these in an ARMSSEDeviceInfo array.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-34-peter.
Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register
block. Because this block is per-CPU and does not clash with any of the
SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the
existing has_cachectrl, has_cpusectrl and has_cpuid, rather than
trying to add per-CPU
For the AN547 image, the FPGAIO block has an extra DBGCTRL register,
which is used to control the SPNIDEN, SPIDEN, NPIDEN and DBGEN inputs
to the CPU. These signals control when the CPU permits use of the
external debug interface. Our CPU models don't implement the
external debug interface, so we
The SSE-300 has a system counter device; add support for SSE
variants having this device.
As with the existing devices like the cache control block, CPUID
block, etc, we don't try to make the MMIO addresses configurable. We
can do that if and when we need to model a future SSE variant which
has t
Move the PPUs into the data-driven device placement framework.
We don't implement them, so they are just TYPE_UNIMPLEMENTED stubs.
Because the SSE-200 and the IotKit diverge here (the IoTKit does
not have the PPUs) we need to separate out the ARMSSEDeviceInfo
for the two variants, and only add the
The AN547 puts the combined UART overflow IRQ at 48, not 47 like the
other images. Make this setting board-specific.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-37-peter.mayd..
The SSE-300 has a slightly different set of shared-per-CPU interrupts,
allow the irq_is_common[] array to be different per SSE variant.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4
Move the sysctl register block into the data-driven device placement
framework.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-29-peter.mayd...@linaro.org
---
hw/arm/armsse.c | 44 ---
On 08/03/21 18:29, Anthony PERARD wrote:
If nothing else works then I guess it's okay, but why can't you do the
xen_block_drive_destroy from e.g. an unrealize callback?
I'm not sure if that's possible.
xen_block_device_create/xen_block_device_destroy() is supposed to be
equivalent to do those
The SSE uses 32 interrupts for its own devices, and then passes through
its expansion IRQ inputs to the CPU's interrupts 33 and upward.
Add a define for the number of IRQs the SSE uses for itself, instead
of hardcoding 32.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-b
We forgot to implement a TYPE_UNIMPLEMENTED_DEVICE stub
for the SYS_PPU in the SSE-200, which is at 0x50022000.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-31-peter.mayd...@linaro.org
---
include/hw/arm/armsse.h
Move the CMSDK watchdog device handling into the data-driven device
placement framework. This is slightly more complicated because these
devices might wire their IRQs up to the NMI line, and because one of
them uses the slow 32KHz clock rather than the main clock.
Signed-off-by: Peter Maydell
Te
From: Xuzhou Cheng
Now that the Xilinx CSU DMA model is implemented, the existing
DMA related dead codes in the ZynqMP QSPI are useless and should
be removed. The maximum register number is also updated to only
include the QSPI registers.
Signed-off-by: Xuzhou Cheng
Signed-off-by: Bin Meng
Rev
Move the CMSDK dualtimer device handling into the data-driven
device placement framework.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-25-peter.mayd...@linaro.org
---
hw/arm/armsse.c | 35 +
The SSE-300 is mostly the same as the SSE-200, but it has moved some
of the devices in the memory map and uses different device types in
some cases. To accommodate this, add a framework where the placement
and wiring of some devices can be specified in a data table.
This commit adds the framework
The SSE-300 has only one CPU and so no INITSVTOR1. It does
have INITSVTOR0, but unlike the SSE-200 this register now
has a LOCK bit which can be set to 1 to prevent any further
writes to the register. Implement these differences.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Rev
The #defines INTERNAL and CASCADING represent different possible
values for the TCCR.CSS register field; prefix them with CSS_ to make
this more obvious, before we add more defines to represent the
other possible values of the field in the next commit.
Signed-off-by: Peter Maydell
Reviewed-by: Ph
The SSE-200 and SSE-300 have different PID register values from the
IoTKit for the sysctl register block. We incorrectly implemented the
SSE-200 with the same PID values as IoTKit. Fix the SSE-200 bug and
report these register values for SSE-300.
Signed-off-by: Peter Maydell
Tested-by: Philippe
The SSE-300 has a new PWRCTRL register at offset 0x1fc (previously
reserved). This register controls accessibility of some registers
in the Power Policy Units (PPUs). Since QEMU doesn't implement
the PPUs, we don't need to implement any real behaviour for this
register, so we just handle the UNLOCK
The SSE-300 includes a counter module; implement a model of it.
This counter is documented in the SSE-123 Example Subsystem
Technical Reference Manual:
https://developer.arm.com/documentation/101370/latest/
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Hen
Move the CMSDK timer that uses the S32K slow clock into the data-driven
device placement framework.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20210219144617.4782-27-peter.mayd...@linaro.org
---
include/hw/arm/armsse.h | 3 +--
hw
From: Xuzhou Cheng
There are some coding convention warnings in xilinx_spips.c,
as reported by:
$ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c
Let's clean them up.
Signed-off-by: Xuzhou Cheng
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed
We model Arm "Subsystems for Embedded" SoC subsystems using generic
code which is split into various sub-devices which are configurable
by QOM properties to handle the behaviour differences between the SSE
subsystems we implement. Currently the only sub-device which needs
to change is the IOTKIT_S
The sysctl PDCM_PD_*_SENSE registers control various power domains in
the system and allow the guest to configure which conditions keep a
power domain awake and what power state to use when the domain is in
a low power state. QEMU doesn't model power domains, so for us these
registers are dummy re
From: Xuzhou Cheng
Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
link of GQSPI to CSU DMA.
Signed-off-by: Xuzhou Cheng
Signed-off-by: Bin Meng
Reviewed-by: Edgar E. Iglesias
Message-id: 20210303135254.3970-4-bmeng...@gmail.com
Signed-off-by: Peter Maydell
---
include/hw/
The SSE-300 has a new register block CPU_PWRCTRL. There is one
instance of this per CPU in the system (so just one for the SSE-300),
and as well as the usual CIDR/PIDR ID registers it has just one
register, CPUPWRCFG. This register allows the guest to configure
behaviour of the system in power-do
The Clock framework allows users to specify a callback which is
called after the clock's period has been updated. Some users need to
also have a callback which is called before the clock period is
updated.
As the first step in adding support for notifying Clock users on
pre-update events, add an
The version of the SYSINFO Register Block in the SSE-300 has
different CIDR/PIDR register values to the SSE-200; pass in
the sse-version property and use it to select the correct
ID register values.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Me
The SSE-300's iokit-sysctl device is similar to the SSE-200, but
some registers have moved address or have different behaviours.
In this commit we add case statements for the registers where
the SSE-300 and SSE-200 have the same behaviour. Some registers
are the same on all SSE versions and so need
Add a new callback event type ClockPreUpdate, which is called on
period changes before the period is updated.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Reviewed-by: Hao Wu
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-id: 20210219144617.4782-3-peter.
Move the sysinfo register block into the data-driven framework.
While we are moving the code for configuring this device around,
regularize on using &error_abortw when setting the integer
properties: they are all simple DEFINE_PROP_UINT32 properties so the
setting can never fail.
Signed-off-by: P
In the SSE-300, the format of the SYS_CONFIG0 register has changed again;
pass through the correct value to the SYSINFO register block device.
We drop the old SysConfigFormat enum, which was implemented in the
hope that different flavours of SSE would share the same format;
since they all seem to
The SSE-300 includes some timers which are a different kind to
those in the SSE-200. Model them.
These timers are documented in the SSE-123 Example Subsystem
Technical Reference Manual:
https://developer.arm.com/documentation/101370/latest/
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathi
1:41 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210308-1
for you to fetch changes up to da2140183ac3a04b1ccb861aeac1f2c048c71b66:
hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
(2021-03-08 17:2
The ARMSSE_CPUID and ARMSSE_MHU Kconfig stanzas are for the devices
implemented by hw/misc/cpuid.c and hw/misc/armsse-mhu.c. Move them
to hw/misc/Kconfig where they belong.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard H
Remove the is_sse200 flag in favour of just directly testing the new
sse_version field.
Since some of these registers exist in the SSE-300 but some do not or
have different behaviour, we expand out the if() statements in the
read and write functions into switch()es, so we have an easy place to
put
For SSE-300, the SYSINFO register block has two new registers:
* SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3;
since the SSE-300 can only be configured with a single CPU it
is always zero
* IIDR is the subsystem implementation identity register;
its value is set by th
Convert the apb_ppc0 and apb_ppc1 fields in the ARMSSE state struct
to use an array instead of two separate fields. We already had one
place in the code that wanted to be able to refer to the PPC by
index, and we're about to add more code like that.
Signed-off-by: Peter Maydell
Tested-by: Philip
On 3/8/21 12:46 PM, Thomas Huth wrote:
The status of the gitlab-CI files is currently somewhat confusing, and
it is often not quite clear whether a patch should go via my tree or
via the testing tree of Alex. That situation has grown historically...
Initially, I was the only one using the gitla
Add a clock_ns_to_ticks() function which does the opposite of
clock_ticks_to_ns(): given a duration in nanoseconds, it returns the
number of clock ticks that would happen in that time. This is useful
for devices that have a free running counter register whose value can
be calculated when it is rea
> Is there something we need to fix in the build system?
Maybe, I do not know how this dependency is validated. If the
directories used to validate dependencies differs from the directories
(or order) used at compile / link time than this can cause errors like
these.
However, what could also happ
In the SSE-300 the CPU_WAIT and NMI_ENABLE registers have
moved offsets, so they are now where the SSE-200's WICCTRL
and EWCTRL were. The SSE-300 does not have WICCTLR or EWCTRL
at all, and the old offsets are reserved:
OffsetSSE-200 SSE-300
---
0x118
On Mon, Mar 08, 2021 at 05:03:58PM +0100, Alexander Graf wrote:
>
>
> On 08.03.21 15:36, Greg KH wrote:
> >
> > On Mon, Mar 08, 2021 at 04:18:03PM +0200, Adrian Catangiu wrote:
> > > +static struct miscdevice sysgenid_misc = {
> > > + .minor = MISC_DYNAMIC_MINOR,
> > > + .name = "sysgeni
On Mon, Mar 08, 2021 at 03:38:49PM +0100, Paolo Bonzini wrote:
> On 08/03/21 15:32, Anthony PERARD wrote:
> > From: Anthony PERARD
> >
> > Whenever a Xen block device is detach via xenstore, the image
> > associated with it remained open by the backend QEMU and an error is
> > logged:
> > qe
The versions of the Secure Access Configuration Register Block
and Non-secure Access Configuration Register Block in the SSE-300
are the same as those in the SSE-200, but the CIDR/PIDR ID
register values are different.
Plumb through the sse-version property and use it to select
the correct ID regi
On Mon, Mar 08, 2021 at 12:08:29PM +0100, Kevin Wolf wrote:
> Am 06.03.2021 um 12:22 hat Peter Maydell geschrieben:
> > On Fri, 5 Mar 2021 at 16:55, Kevin Wolf wrote:
> > >
> > > The following changes since commit
> > > 9a7beaad3dbba982f7a461d676b55a5c3851d312:
> > >
> > > Merge remote-tracking
Alistair Francis writes:
> I have started on the effort, but I have not finished yet. Adding
> riscv_cpu_is_32bit() was the first step there and I have some more
> patches locally but I don't have anything working yet.
That's awesome. I think waiting until we see what APIs you're developing
for
Use the new clock_ns_to_ticks() function in npcm7xx_timer where
appropriate.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Hao Wu
Tested-by: Philippe Mathieu-Daudé
Message-id: 20210219144617.4782-5-peter.mayd...@linaro.org
---
hw/timer/
On Wed, 3 Mar 2021 at 13:53, Bin Meng wrote:
>
> From: Bin Meng
>
> ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
> is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
> crash. This is observed when testing VxWorks 7.
>
> We added a Xilinx CSU DMA model and
Daniel Henrique Barboza writes:
> On 3/6/21 3:57 AM, Markus Armbruster wrote:
>> Cc: ACPI maintainers for additional expertise.
>>
>> Daniel Henrique Barboza writes:
>>
>>> Hi,
>>>
>>> Recent changes in pseries code (not yet pushed, available at David's
>>> ppc-for-6.0) are using the QAPI even
user_creatable_add_opts() has only a single user left, which is a test
case. Rewrite the test to use user_creatable_add_type() instead (which
is the remaining function that doesn't require a QAPI schema) and drop
the QemuOpts related functions.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Re
Meson theoretically checks for that:
meson.build: zstd = dependency('libzstd', version: '>=1.4.0',
I suppose meson found the dependency, but the compile flags got the
wrong header. Is there something we need to fix in the build system?
--
You received this bug notification because you are a me
The following changes since commit 138d2931979cb7ee4a54a434a54088231f6980ff:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210308'
into staging (2021-03-08 11:57:36 +)
are available in the Git repository at:
git://repo.or.cz/qemu/kevin.git tags/for-ups
This switches qemu-img from a QemuOpts-based parser for --object to
user_creatable_process_cmdline() which uses a keyval parser and enforces
the QAPI schema.
Apart from being a cleanup, this makes non-scalar properties accessible.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
---
qemu-img.c
* Stefan Hajnoczi (stefa...@redhat.com) wrote:
> On Tue, Feb 09, 2021 at 07:02:07PM +, Dr. David Alan Gilbert (git) wrote:
> > diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
> > index d6085f7045..1deedd3407 100644
> > --- a/docs/interop/vhost-user.rst
> > +++ b/docs/inte
This adds a QAPI schema for the properties of the objects implementing
the confidential-guest-support interface.
pef-guest and s390x-pv-guest don't have any properties, so they only
need to be added to the ObjectType enum without adding a new branch to
ObjectOptions.
Signed-off-by: Kevin Wolf
Ac
On 08/03/2021 17.35, Philippe Mathieu-Daudé wrote:
On 3/8/21 4:46 PM, Thomas Huth wrote:
The status of the gitlab-CI files is currently somewhat confusing, and
it is often not quite clear whether a patch should go via my tree or
via the testing tree of Alex. That situation has grown historically
This switches the system emulator from a QemuOpts-based parser for
-object to user_creatable_parse_str() which uses a keyval parser and
enforces the QAPI schema.
Apart from being a cleanup, this makes non-scalar properties accessible.
This adopts a similar model as -blockdev uses: When parsing th
This switches qemu-nbd from a QemuOpts-based parser for --object to
user_creatable_process_cmdline() which uses a keyval parser and enforces
the QAPI schema.
Apart from being a cleanup, this makes non-scalar properties accessible.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Er
The implementation for --object can be shared between
qemu-storage-daemon and other binaries, so move it into a function in
qom/object_interfaces.c that is accessible from everywhere.
This also requires moving the implementation of qmp_object_add() into a
new user_creatable_add_qapi(), because qom
This switches the HMP command object_add from a QemuOpts-based parser to
user_creatable_add_from_str() which uses a keyval parser and enforces
the QAPI schema.
Apart from being a cleanup, this makes non-scalar properties and help
accessible. In order for help to be printed to the monitor instead o
This adds a QAPI schema for the properties of the input-* objects.
ui.json cannot be included in qom.json because the storage daemon can't
use it, so move GrabToggleKeys to common.json.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/common.json | 12
This switches qemu-io from a QemuOpts-based parser for --object to
user_creatable_process_cmdline() which uses a keyval parser and enforces
the QAPI schema.
Apart from being a cleanup, this makes non-scalar properties accessible.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eri
The system emulator has a more complicated way of handling command line
options in that it reorders options before it processes them. This means
that parsing object options and creating the object happen at two
different points. Split the parsing part into a separate function that
can be reused by
This is a version of user_creatable_process_cmdline() with an Error
parameter that never calls exit() and is therefore usable in HMP.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
include/qom/object_interfaces.h | 16
qom/object_interfaces.c
This code is going away anyway, but for a few more commits, we'll be in
a state where some binaries still use QemuOpts and others don't. If the
"object" QemuOptsList doesn't even exist, we don't have to remove (or
fail to remove, and therefore abort) a user creatable object from it.
Signed-off-by:
On Sat, 6 Mar 2021 at 15:18, Philippe Mathieu-Daudé wrote:
>
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> A KVM-only build won't be able to run TCG cpus, mov
This function is now unused and can be removed.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
include/qom/object_interfaces.h | 18 --
qom/object_interfaces.c | 32
2 files changed, 50 deletions(-)
diff --
This adds a QAPI schema for the properties of the throttle-group object.
The only purpose of the x-* properties is to make the nested options in
'limits' available for a command line parser that doesn't support
structs. Any parser that will use the QAPI schema will supports structs,
though, so the
This adds a QAPI schema for the properties of the filter-* objects.
Some parts of the interface (in particular NetfilterProperties.position)
are very unusual for QAPI, but for now just describe the existing
interface.
net.json can't be included in qom.json because the storage daemon
doesn't have
This adds a QAPI schema for the properties of the colo-compare object.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/qom.json | 49 +
1 file changed, 49 insertions(+)
diff --git a/qapi/qom.json b/qapi/qom.json
This QAPIfies --object and ensures that QMP and the command line option
behave the same.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
storage-daemon/qemu-storage-daemon.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a
This adds a QAPI schema for the properties of the pr-manager-helper
object.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/qom.json | 14 ++
1 file changed, 14 insertions(+)
diff --git a/qapi/qom.json b/qapi/qom.json
index 6fe775bd83..6afac9169f
This adds a QAPI schema for the properties of the dbus-vmstate object.
A list represented as a comma separated string is clearly not very
QAPI-like, but for now just describe the existing interface.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/qom.json | 1
This adds a QAPI schema for the properties of the secret* objects.
The 'loaded' property doesn't seem to make sense as an external
interface: It is automatically set to true in ucc->complete, and
explicitly setting it to true earlier just means that additional options
will be silently ignored.
In
This converts object-add from 'gen': false to the ObjectOptions QAPI
type. As an immediate benefit, clients can now use QAPI schema
introspection for user creatable QOM objects.
It is also the first step towards making the QAPI schema the only
external interface for the creation of user creatable
This adds a QAPI schema for the properties of the can-* objects.
can-bus doesn't have any properties, so it only needs to be added to the
ObjectType enum without adding a new branch to ObjectOptions.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/qom.json |
This adds a QAPI schema for the properties of the memory-backend-*
objects.
HostMemPolicy has to be moved to an include file that can be used by the
storage daemon, too, because ObjectOptions must be the same in all
binaries if we don't want to compile the whole code multiple times.
Signed-off-by
Add an ObjectOptions union that will eventually describe the options of
all user creatable object types. As unions can't exist without any
branches, also add the first object type.
This adds a QAPI schema for the properties of the iothread object.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
This adds a QAPI schema for the properties of the x-remote-object
object.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/qom.json | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/qapi/qom.json b/qapi/qom.json
index 6b9
This adds a QAPI schema for the properties of the rng-* objects.
The 'opened' property doesn't seem to make sense as an external
interface: It is automatically set to true in ucc->complete, and
explicitly setting it to true earlier just means that trying to set
additional options will result in an
This adds a QAPI schema for the properties of the authz-* objects.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/authz.json | 61 +---
qapi/qom.json| 10 +
storage-daemon/qapi/qapi-sche
The option has been deprecated in QEMU 5.0, remove it.
Signed-off-by: Kevin Wolf
Acked-by: Peter Krempa
Reviewed-by: Eric Blake
---
qapi/qom.json| 6 +-
docs/system/deprecated.rst | 5 -
docs/system/removed-features.rst | 5 +
qom/qom-qmp-cmds.c
This adds a QAPI schema for the properties of the tls-* objects.
The 'loaded' property doesn't seem to make sense as an external
interface: It is automatically set to true in ucc->complete, and
explicitly setting it to true earlier just means that additional options
will be silently ignored.
In o
This adds a QAPI schema for the properties of the cryptodev-* objects.
These interfaces have some questionable aspects (cryptodev-backend is
really an abstract base class without function, and the queues option
only makes sense for cryptodev-vhost-user), but as the goal is to
represent the existin
On Mon, 8 Mar 2021 21:39:49 +0530
Tarun Gupta wrote:
> VFIO migration support in QEMU is experimental as of now, which was done to
> provide soak time and resolve concerns regarding bit-stream.
> But, with the patches discussed in
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg784931.htm
This series adds a QAPI type for the properties of all user creatable
QOM types and finally makes the --object command line option (in all
binaries) and the object-add monitor commands (in QMP and HMP) use the
new ObjectOptions union.
This change improves things in more than just one way:
1. Docu
On Tue, 2 Mar 2021 at 11:09, Edgar E. Iglesias wrote:
>
> From: "Edgar E. Iglesias"
>
> Add a model of the Xilinx Versal Accelerator RAM (XRAM).
> This is mainly a stub to make firmware happy. The size of
> the RAMs can be probed. The interrupt mask logic is
> modelled but none of the interrups w
On Thu, Feb 25, 2021 at 09:12:39AM +0900, Akihiko Odaki wrote:
> Report the configured granularity for discard operation to the
> guest. If this is not set use the block size.
>
> Since until now we have ignored the configured discard granularity
> and always reported the block size, let's add
> '
On Wed, Feb 24, 2021 at 04:21:13PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/24/21 3:38 PM, Peter Maydell wrote:
> > On Wed, 24 Feb 2021 at 13:21, Daniel P. Berrangé
> > wrote:
> >>
> >> The following features have been deprecated for well over the 2
> >> release cycle we promise
> >>
> >> ``
Am 08.03.21 um 16:46 schrieb Roman Bolshakov:
> gnutls failures on macOS and FreeBSD (with clang as main compiler) won’t
> happen only if libtasn1 from master is used. Otherwise libtasn1 has to be
> compiled with -O1/-O0.
Of course it is also possible to patch older versions of libtasn1 to
mak
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