The Micron mt25ql02g is a 3V 2Gb serial NOR flash memory supporting
dual I/O and quad I/O, 4KB, 32KB, 64KB sector erase. It also supports
4B opcodes. The mt25qu02g operates at 1.8V.
From: Patrick Venture
The Quanta-Q71l BMC board is a board supported by OpenBMC.
Tested: Booted quanta-q71l firmware.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
Reviewed-by: Cédric Le Goater
Message-Id: <20210416162426.3217033-1-vent...@google.com>
Signed-off-by: Cédric Le Goater
Cc: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210407171637.43-3-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 3 ---
hw/arm/aspeed_ast2600.c | 4
hw/arm/aspeed_soc.c | 4
It will simplify extensions of the SMC model.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-Id: <20210407171637.43-15-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 2 +-
hw/ssi/aspeed_smc.c | 44
The AST2600 SPI controllers have a set of bits to request/grant DMA
access. Add a new SMC feature for these controllers and use it to
check access to the DMA registers.
Cc: Chin-Ting Kuo
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-Id:
From: Joel Stanley
Test MTD images from the OpenBMC project on AST2400 and AST2500 SoCs
from ASPEED, by booting Palmetto and Romulus BMC machines.
The images are fetched from OpenBMC's release directory on github.
Cc: Cleber Rosa
Cc: Wainer dos Santos Moschetta
Co-developed-by: Cédric Le
From: Joel Stanley
The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1,
SHA2, RSA and other cryptographic algorithms.
This initial model implements a subset of the device's functionality;
currently only MD5/SHA hashing, and on the ast2600's scatter gather
engine.
From: Joel Stanley
This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.
The tests are similar, but are cut/pasted instead of broken out into a
common function so the assert machinery produces useful output when a
The m25p80 test depends on the Aspeed SMC controller to test our
SPI-NOR flash support. Reflect this dependency by changing the name.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-Id: <20210407171637.43-17-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
From: Joel Stanley
This tests a Debian multi-soc arm32 Linux kernel on the AST2600 based
Tacoma BMC machine.
There is no root file system so the test terminates when boot reaches
the stage where it attempts and fails to mount something.
Cc: Cleber Rosa
Cc: Wainer dos Santos Moschetta
From: Joel Stanley
Add the hash and crypto engine model to the Aspeed socs.
Reviewed-by: Andrew Jeffery
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Klaus Heinrich Kiwi
Signed-off-by: Joel Stanley
Message-Id: <20210409000253.1475587-3-j...@jms.id.au>
From: Philippe Mathieu-Daudé
The flash mmio region is exposed as an AddressSpace.
AddressSpaces must not be sysbus-mapped, therefore map
the region using an alias.
Signed-off-by: Philippe Mathieu-Daudé
[ clg : Fix DMA_FLASH_ADDR() ]
Signed-off-by: Cédric Le Goater
Message-Id:
The Rainier BMC board is a board for the middle range POWER10 IBM systems.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-Id: <20210407171637.43-19-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 79 +
When we introduced support for the AST2600 SoC, the XDMA controller
was forgotten. It went unnoticed because it's not used under emulation.
But the register layout being different, the reset procedure is bogus
and this breaks kexec.
Add a AspeedXDMAClass to take into account the register
The following changes since commit 609d7596524ab204ccd71ef42c9eee4c7c338ea4:
Update version for v6.0.0 release (2021-04-29 18:05:29 +0100)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspeed-20210503
for you to fetch changes up to
The RAM memory region is now used for DMAs accesses instead of the
memory address space region. Mask off the top bits of the DMA address
to reflect this change.
Cc: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
Message-Id: <20210407171637.43-4-...@kaod.org>
Signed-off-by: Cédric Le
It improves 'info mtree' output.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210407171637.43-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/i2c/aspeed_i2c.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Instead of passing the memory address space region, simply use the RAM
memory region instead. This simplifies RAM accesses.
This patch breaks migration compatibility.
Fixes: c4e1f0b48322 ("aspeed/smc: Add support for DMAs")
Cc: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
The SWIFT machine never came out of the lab and we already have enough
AST2500 based OpenPower machines.
Cc: Adriana Kobylak
Signed-off-by: Cédric Le Goater
---
docs/system/deprecated.rst | 7 +++
hw/arm/aspeed.c| 3 +++
2 files changed, 10 insertions(+)
diff --git
On 03/05/2021 06.58, Markus Armbruster wrote:
Thomas Huth writes:
Clang unfortunately does not support generating code for the z900
architecture level and starts with the z10 instead. Thus to be able
to support compiling with Clang, we have to check for the supported
compiler flags. The
Hello,
I believe I experienced the same bug in a similar context: using QEMU
Linux user emulation for continuous integration on GitHub Actions. As a
workaround, I did run the chroot script with taskset -c 0 to limit
execution on a single CPU which has been solving the problem for more
than 10
Thomas Huth writes:
> Clang unfortunately does not support generating code for the z900
> architecture level and starts with the z10 instead. Thus to be able
> to support compiling with Clang, we have to check for the supported
> compiler flags. The disadvantage is of course that the bios image
On Fri, Apr 30, 2021 at 04:35:32PM -0300, Bruno Larsen (billionai) wrote:
> Renamed all gen_spr_* and gen_* functions specifically related to
> registering SPRs to register_*_sprs and register_*, to avoid future
> confusion with other TCG related code.
>
> Signed-off-by: Bruno Larsen (billionai)
On Fri, Apr 30, 2021 at 04:35:28PM -0300, Bruno Larsen (billionai) wrote:
> Moved all SPR read/write callback, and some related functions, to a
> new file specific for it. These callbacks are TCG only, so separating
> them is required to support the build flag disable-tcg.
>
> Making the
Philippe Mathieu-Daudé writes:
> On 5/2/21 7:48 PM, Thomas Huth wrote:
>> When compiling the s390-ccw bios with Clang, the compiler emits a warning:
>>
>> pc-bios/s390-ccw/main.c:210:5: warning: variable 'found' is used
>> uninitialized
>> whenever switch default is taken
On Fri, Apr 30, 2021 at 04:35:31PM -0300, Bruno Larsen (billionai) wrote:
> Since vscr is not an spr, its initialization was removed from the
> spr registration functions, and moved to the relevant init_procs.
>
> We may look into adding vscr to the reset path instead of the init
> path (as
On Fri, Apr 30, 2021 at 05:58:46PM -0700, Richard Henderson wrote:
> On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> > Removed functions gen_read_xer and gen_write_xer, moving their logic
> > directly into spr_read_xer and spr_write_xer, respectively.
> >
> > Signed-off-by: Bruno Larsen
On Fri, Apr 30, 2021 at 05:27:13PM -0700, Richard Henderson wrote:
> On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
> > moved RW callback parameters of _spr_register into an ifdef, to support
> > building without TCG in the future, and added definitions for
> > spr_register and
On 02/05/2021 20.57, Philippe Mathieu-Daudé wrote:
On 5/2/21 7:48 PM, Thomas Huth wrote:
When compiling the s390-ccw bios with Clang, the compiler emits a warning:
pc-bios/s390-ccw/main.c:210:5: warning: variable 'found' is used uninitialized
whenever switch default is taken
On 03/05/2021 03.41, Alistair Francis wrote:
On Thu, Apr 29, 2021 at 8:00 PM Markus Armbruster wrote:
If you're cc'ed, you added a section to docs/system/deprecated.rst that
is old enough to permit removal. This is *not* a demand to remove, it's
a polite request to consider whether the time
On Fri, Apr 30, 2021 at 03:40:47PM -0300, Lucas Mateus Castro (alqotel) wrote:
> Moved h_enter, remove_hpte, h_remove, h_bulk_remove,h_protect and
> h_read to spapr_hcall_tcg.c, added h_tcg_only to be used in a !TCG
> environment in spapr_hcall.c and changed build options to only build
>
On Fri, Apr 30, 2021 at 08:38:05PM -0300, Fabiano Rosas wrote:
> "Lucas Mateus Castro (alqotel)" writes:
>
> > Also spapr_hcall_tcg.c only has 2 duplicated functions (valid_ptex and
> > is_ram_address), what is the advised way to deal with these
> > duplications?
>
> valid_ptex is only needed
On Fri, Apr 30, 2021 at 10:02:16AM -0300, Bruno Piazera Larsen wrote:
> On 30/04/2021 01:21, David Gibson wrote:
> > On Thu, Apr 29, 2021 at 01:21:26PM -0300, Bruno Larsen (billionai) wrote:
> > > Moved all SPR read/write callback, and some related functions, to a
> > > new file specific for it.
On Sat, May 01, 2021 at 05:24:35PM +1000, Nicholas Piggin wrote:
> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
> and it removes support for the LPCR[AIL]=0b10 mode.
>
> Reviewed-by: Cédric Le Goater
> Tested-by: Cédric Le Goater
> Signed-off-by: Nicholas Piggin
On Fri, Apr 30, 2021 at 03:40:46PM -0300, Lucas Mateus Castro (alqotel) wrote:
> The functions ppc_store_lpcr, ppc_hash64_filter_pagesizes and
> ppc_hash64_unmap_hptes have been moved to mmu-misc.h since they are
> not needed in a !TCG context and mmu-hash64 should not be compiled
> in such
On Fri, Apr 30, 2021 at 07:29:23PM -0700, Richard Henderson wrote:
> We elide values when registering sprs, we might as well
> save space in the array as well.
>
> Signed-off-by: Richard Henderson
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/cpu.h | 12
> 1 file changed, 8
On Sat, May 01, 2021 at 05:24:34PM +1000, Nicholas Piggin wrote:
> The AIL logic is becoming unmanageable spread all over powerpc_excp(),
> and it is slated to get even worse with POWER10 support.
>
> Move it all to a new helper function.
>
> Reviewed-by: Cédric Le Goater
> Tested-by: Cédric Le
On Fri, Apr 30, 2021 at 07:29:22PM -0700, Richard Henderson wrote:
> Introduce 3 helper macros to elide arguments that we cannot supply.
> This reduces the repetition required to get the job done.
>
> Signed-off-by: Richard Henderson
Applied to ppc-for-6.1, thanks.
> ---
>
On Fri, Apr 30, 2021 at 5:18 PM Bin Meng wrote:
>
> From: Bin Meng
>
> The supported device bullet list has an additional space before each
> entry, which makes a wrong indentation level. Correct it.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> (no changes
On 4/24/21 3:41 PM, Philippe Mathieu-Daudé wrote:
If the Kconfig 'USB' value is not selected, it is pointless to
build the USB core components. Add a stub for the HMP commands
and usbdevice_create() which is called by usb_device_add in
softmmu/vl.c.
Signed-off-by: Philippe Mathieu-Daudé
---
On 4/24/21 3:41 PM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/host-stub.c | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson
r~
- Original Message -
> From: "Philippe Mathieu-Daudé"
> To: "Cleber Rosa" , qemu-devel@nongnu.org
> Cc: "Thomas Huth" , "Beraldo Leal" ,
> "Wainer dos Santos Moschetta"
> , "Alex Bennée" , "Willian
> Rampazzo" , "Eduardo
> Habkost"
> Sent: Sunday, May 2, 2021 11:24:44 AM
> Subject:
On Thu, Apr 29, 2021 at 8:00 PM Markus Armbruster wrote:
>
> If you're cc'ed, you added a section to docs/system/deprecated.rst that
> is old enough to permit removal. This is *not* a demand to remove, it's
> a polite request to consider whether the time for removal has come.
> Extra points for
Still present on qemu 5.2.0 and Linux 5.10
** Changed in: qemu
Status: Incomplete => New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1856399
Title:
Intel GVT-g works in X11, segfaults in
On Sun, May 02, 2021 at 10:31:20PM +0200, Philippe Mathieu-Daudé wrote:
> The OR_IRQ device is bus-less, thus isn't reset automatically.
> Add the raven_pcihost_reset() handler to manually reset the OR IRQ.
>
> Fixes: f40b83a4e31 ("40p: use OR gate to wire up raven PCI interrupts")
>
Patchew URL:
https://patchew.org/QEMU/20210502235727.1979457-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210502235727.1979457-1-richard.hender...@linaro.org
Subject: [PATCH v6
We already had mulu2_i32 for a 32-bit host; expand this to 64-bit
hosts as well. The muls2_i32 and the 64-bit opcodes are new.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c| 35
Suggested-by: Thomas Huth
Signed-off-by: Richard Henderson
---
.gitlab-ci.d/crossbuilds.yml | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 2d95784ed5..fbf7b7a881 100644
---
This removes all of the problems with unaligned accesses
to the bytecode stream.
With an 8-bit opcode at the bottom, we have 24 bits remaining,
which are generally split into 6 4-bit slots. This fits well
with the maximum length opcodes, e.g. INDEX_op_add2_i386, which
have 6 register operands.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c| 42
tcg/tci/tcg-target.c.inc | 32 ++
3 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/tcg/tci/tcg-target.h
These were already present in tcg-target.c.inc,
but not in the interpreter.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 20 ++--
tcg/tci.c| 40
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git
The longest test at the moment seems to be a (slower)
aarch64 host, for which test-mmap takes 64 seconds.
Reviewed-by: Thomas Huth
Signed-off-by: Richard Henderson
---
configure | 3 +++
tests/tcg/Makefile.target | 6 --
2 files changed, 7 insertions(+), 2 deletions(-)
We're currently only testing TCI with a 64-bit host -- also test
with a 32-bit host. Enable a selection of softmmu and user-only
targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each.
Acked-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Inline it into its one caller, tci_write_reg64.
Drop the asserts that are redundant with tcg_read_r.
Signed-off-by: Richard Henderson
---
tcg/tci.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 5677c3544a..6900c3e891 100644
---
When this opcode is not available in the backend, tcg middle-end
will expand this as a series of 5 opcodes. So implementing this
saves bytecode space.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 4 ++--
tcg/tci.c| 16 +++-
Expand the single-use macros into the new functions.
Use cpu_ldsb_mmuidx_ra and cpu_ldsw_le_mmuidx_ra so
that the trace event receives the correct sign flag.
Signed-off-by: Richard Henderson
---
tcg/tci.c | 215 +++---
1 file changed, 75
We're about to adjust the offset range on host memory ops,
and the format of branches. Both will require a temporary.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 1 +
tcg/tci/tcg-target.c.inc | 1 +
2 files changed, 2 insertions(+)
diff --git a/tcg/tci/tcg-target.h
This requires adjusting where arguments are stored.
Place them on the stack at left-aligned positions.
Adjust the stack frame to be at entirely positive offsets.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 1 +
tcg/tci/tcg-target.h | 2 +-
tcg/tcg.c|
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 12 +--
tcg/tci.c| 44
tcg/tci/tcg-target.c.inc | 9
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/tcg/tci/tcg-target.h
The current setting is much too pessimistic. Indicating only
the one or two registers that are actually assigned after a
call should avoid unnecessary movement between the register
array and the stack array.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 10 --
1 file
As the only call-clobbered regs for TCI, these should
receive the least priority.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index
The encoding planned for tci does not have enough room for
brcond2, with 4 registers and a condition as input as well
as the label. Resolve the condition into TCG_REG_TMP, and
relax brcond to one register plus a label, considering the
condition to always be reg != 0.
Signed-off-by: Richard
We already had the 32-bit versions for a 32-bit host; expand this
to 64-bit hosts as well. The 64-bit opcodes are new.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 8
tcg/tci.c| 40 ++--
tcg/tci/tcg-target.c.inc |
Add libffi as a build requirement for TCI.
Add libffi to the dockerfiles to satisfy that requirement.
Construct an ffi_cif structure for each unique typemask.
Record the result in a separate hash table for later lookup;
this allows helper_table to stay const.
Signed-off-by: Richard Henderson
This will give us both flags and typemask for use later.
We also fix a dumping bug, wherein calls generated for plugins
fail tcg_find_helper and print (null) instead of either a name
or the raw function pointer.
Signed-off-by: Richard Henderson
---
tcg/internal.h | 14 +-
tcg/tcg.c
Signed-off-by: Richard Henderson
---
tcg/internal.h | 5 +
tcg/tcg.c | 5 ++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/internal.h b/tcg/internal.h
index c2d5e9c42f..cd128e2a83 100644
--- a/tcg/internal.h
+++ b/tcg/internal.h
@@ -32,6 +32,11 @@ typedef struct
As noted by qemu-plugins.h, enum qemu_plugin_cb_flags is
currently unused -- plugins can neither read nor write
guest registers.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-helpers.h | 1 -
include/qemu/plugin.h | 1 -
accel/tcg/plugin-gen.c | 8
plugins/core.c
This operation is critical to staying within the interpretation
loop longer, which avoids the overhead of setup and teardown for
many TBs.
The check in tcg_prologue_init is disabled because TCI does
want to use NULL to indicate exit, as opposed to branching to
a real epilogue.
Signed-off-by:
As noted by qemu-plugins.h, plugins can neither read nor write
guest registers.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-helpers.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h
index
We will shortly be interested in distinguishing pointers
from integers in the helper's declaration, as well as a
true void return. We currently have two parallel 1 bit
fields; merge them and expand to a 3 bit field.
Our current maximum is 7 helper arguments, plus the return
makes 8 * 3 = 24 bits
Let the compiler decide on inlining.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index c3dc3effe7..eb99be52d0 100644
--- a/accel/tcg/plugin-gen.c
+++
We're going to change how to look up the call flags from a TCGop,
so extract it as a helper.
Signed-off-by: Richard Henderson
---
tcg/internal.h | 33 +
tcg/optimize.c | 3 ++-
tcg/tcg.c | 15 +++
3 files changed, 42 insertions(+), 9
Changes since v5:
* More patches now upstream.
* Re-work how ffi is used, to avoid breaking plugins.
Changes since v4:
* 19 more patches now upstream.
Changes since v3:
* First patch fixes g2h() breakage. This shows a hole in our CI,
in that we only build softmmu with TCI, not
Patchew URL:
https://patchew.org/QEMU/20210502231844.1977630-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210502231844.1977630-1-richard.hender...@linaro.org
Subject: [PATCH v3
Compute the value using straight division and bounds,
rather than a loop. Pass in tb_size rather than reading
from tcg_init_ctx.code_gen_buffer_size,
Signed-off-by: Richard Henderson
---
tcg/region.c | 29 -
1 file changed, 12 insertions(+), 17 deletions(-)
diff
Shortly, the full code_gen_buffer will only be visible
to region.c, so move in_code_gen_buffer out-of-line.
Move the debugging versions of tcg_splitwx_to_{rx,rw}
to region.c as well, so that the compiler gets to see
the implementation of in_code_gen_buffer.
This leaves exactly one use of
There's a change in mprotect() behaviour [1] in the latest macOS
on M1 and it's not yet clear if it's going to be fixed by Apple.
In this case, instead of changing permissions of N guard pages,
we change permissions of N rwx regions. The same number of
syscalls are required either way.
[1]
A size is easier to work with than an end point,
particularly during initial buffer allocation.
Signed-off-by: Richard Henderson
---
tcg/region.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index
Do not handle protections on a case-by-case basis in the
various alloc_code_gen_buffer instances; do it within a
single loop in tcg_region_init.
Signed-off-by: Richard Henderson
---
tcg/region.c | 45 +++--
1 file changed, 31 insertions(+), 14
Return output buffer and size via output pointer arguments,
rather than returning size via tcg_ctx->code_gen_buffer_size.
Signed-off-by: Richard Henderson
---
tcg/region.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index
Buffer management is integral to tcg. Do not leave the allocation
to code outside of tcg/. This is code movement, with further
cleanups to follow.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +-
accel/tcg/translate-all.c | 414 +
If qemu_get_host_physmem returns an odd number of pages,
then physmem / 8 will not be a multiple of the page size.
The following was observed on a gitlab runner:
ERROR qtest-arm/boot-serial-test - Bail out!
ERROR:../util/osdep.c:80:qemu_mprotect__osdep: \
assertion failed: (!(size &
Signed-off-by: Richard Henderson
---
tcg/internal.h | 37
tcg/region.c| 572
tcg/tcg.c | 547 +
tcg/meson.build | 1 +
4 files changed, 613 insertions(+), 544 deletions(-)
create mode
Move the call out of the N versions of alloc_code_gen_buffer
and into tcg_region_init.
Signed-off-by: Richard Henderson
---
tcg/region.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index 23fe113750..b3f0b9bda5 100644
---
These variables belong to the jit side, not the user side.
Since tcg_init_ctx is no longer used outside of tcg/, move
the declaration to tcg/internal.h.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 -
tcg/internal.h| 1 +
Change the interface from a boolean error indication to a
negative error vs a non-negative protection. For the moment
this is only interface change, not making use of the new data.
Signed-off-by: Richard Henderson
---
tcg/region.c | 63 +++-
1
It consists of one function call and has only one caller.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index
Finish the divorce of tcg/ from hw/, and do not take
the max cpu value from MachineState; just remember what
we were passed in tcg_init.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/internal.h | 3 ++-
tcg/region.c | 6 +++---
tcg/tcg.c | 23
For --enable-tcg-interpreter on Windows, we will need this.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/osdep.h | 1 +
util/osdep.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index
All callers immediately assert on error, so move the assert
into the function itself.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index
Do not mess around with setting values within tcg_init_ctx.
Put the values into 'region' directly, which is where they
will live for the lifetime of the program.
Signed-off-by: Richard Henderson
---
tcg/region.c | 64 ++--
1 file changed, 27
There is only one caller, and shortly we will need access
to the MachineState, which tcg_init_machine already has.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 2 ++
include/sysemu/tcg.h | 2 --
accel/tcg/tcg-all.c | 14 +-
accel/tcg/translate-all.c
Start removing the include of hw/boards.h from tcg/.
Pass down the max_cpus value from tcg_init_machine,
where we have the MachineState already.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +-
tcg/internal.h | 2 +-
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 4 +---
fpu/meson.build | 1 +
2 files changed, 2 insertions(+), 3 deletions(-)
create mode 100644 fpu/meson.build
diff --git a/meson.build b/meson.build
index f04565c5bb..bc70c9a2b3 100644
---
Give the field a name reflecting its actual meaning.
Signed-off-by: Richard Henderson
---
tcg/region.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index a17f342f38..bd81b35359 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@
Perform both tcg_context_init and tcg_region_init.
Do not leave this split to the caller.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 3 +--
tcg/internal.h| 1 +
accel/tcg/translate-all.c | 3 +--
tcg/tcg.c | 9 -
4 files changed, 11
We shortly want to use tcg_init for something else.
Since the hook is called init_machine, match that.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-all.c
This has only one user, but will make more sense after some
code motion.
Always leave the tcg_init_ctx initialized to the first region,
in preparation for tcg_prologue_init(). This also requires
that we don't re-allocate the region for the first cpu, lest
we hit the assertion for total number of
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 8 +---
tcg/meson.build | 13 +
2 files changed, 14 insertions(+), 7 deletions(-)
create mode 100644 tcg/meson.build
diff --git a/meson.build b/meson.build
index d8bb1ec5aa..f04565c5bb
This has only one user, and currently needs an ifdef,
but will make more sense after some code motion.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8b57e93ca2..df78c89673 100644
---
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