From: Richard Henderson
We have eliminated all normal uses of hflags_nmsr. We need
not even compute it except when we want to migrate. Rename
the field to emphasize this.
Remove the fixme comment for migrating access_type. This value
is only ever used with the current executing instruction,
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-15-richard.hender...@linaro.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index
The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' into
staging (2021-05-02 16:23:05 +0100)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git
From: Richard Henderson
As per hreg_compute_hflags:
We 'forget' FE0 & FE1: we'll never generate imprecise exceptions
remove the hflags marker from the respective comments.
Signed-off-by: Richard Henderson
Message-Id: <20210315184615.1985590-7-richard.hender...@linaro.org>
Reviewed-by:
From: Richard Henderson
Match cpu_post_load in using ppc_store_msr to set all of
the cpu state implied by the value of msr. Do not restore
hflags or hflags_nmsr, as we recompute them in ppc_store_msr.
Signed-off-by: Richard Henderson
Message-Id:
From: Richard Henderson
Keep all hflags computation in one place, as this will be
especially important later.
Introduce a new POWERPC_FLAG_HID0_LE bit to indicate when
LE should be taken from HID0. This appears to be set if
and only if POWERPC_FLAG_RTC_CLK is set, but we're not
short of bits
From: Philippe Mathieu-Daudé
On Mac99 and newer machines, the Uninorth PCI host bridge maps
the PCI hole region at 2GiB, so the RAM area beside 2GiB is not
accessible by the CPU. Restrict the memory to 2GiB to avoid
problems such the one reported in the buglink.
Buglink:
> > The proposal that "sync-dax=unsafe" for non-PPC architectures, is a
> > fundamental misrepresentation of how this is supposed to work. Rather
> > than make "sync-dax" a first class citizen of the device-description
> > interface I'm proposing that you make this a separate device-type.
> > This
On 03/05/2021 18.55, Peter Maydell wrote:
In rtc-test.c we know that s is non-NULL because qtest_start()
will return a non-NULL value, and we assume this when we
pass s to qtest_irq_intercept_in(). So we can drop the
initial assignment of NULL and the "if (s)" condition at
the end of the
On 5/4/21 1:11 AM, Dan Williams wrote:
On Mon, May 3, 2021 at 7:06 AM Shivaprasad G Bhat wrote:
.
The proposal that "sync-dax=unsafe" for non-PPC architectures, is a
fundamental misrepresentation of how this is supposed to work. Rather
than make "sync-dax" a first class citizen of
On Tue, May 4, 2021 at 6:34 AM Alistair Francis
wrote:
>
> QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
> and sifive_u machines. This patch moves that change from the
> deprecated.rst file to the removed-features.rst file and the
> target-riscv.rst.
>
> Signed-off-by:
On Mon, May 03, 2021 at 01:23:47PM -0500, Eric Blake wrote:
> On 4/28/21 10:48 PM, Shivaprasad G Bhat wrote:
> > The subsequent patches add definitions which tend to
> > get the compilation to cyclic dependency. So, prepare
> > with forward declarations, move the defitions and clean up.
>
>
On 4/27/21 3:00 AM, Markus Armbruster wrote:
John Snow writes:
On 4/25/21 3:59 AM, Markus Armbruster wrote:
John Snow writes:
When the token can be None, we can't use 'x in "abc"' style membership
tests to group types of tokens together, because 'None in "abc"' is a
TypeError.
Easy
On Mon, May 03, 2021, Paolo Bonzini wrote:
> On 30/04/21 08:24, Yang Zhong wrote:
> > +void pc_machine_init_sgx_epc(PCMachineState *pcms)
> > +{
> > +SGXEPCState *sgx_epc;
> > +X86MachineState *x86ms = X86_MACHINE(pcms);
> > +
> > +sgx_epc = g_malloc0(sizeof(*sgx_epc));
> > +
On Mon, May 03, 2021 at 04:18:47PM +0100, Peter Maydell wrote:
> The h_int_reset() function resets the XIVE interrupt controller via
> device_legacy_reset(). We know that the interrupt controller does
> not have a qbus of its own, so the new device_cold_reset() function
> (which resets both the
On Mon, May 03, 2021 at 05:15:38PM -0300, Bruno Piazera Larsen wrote:
>
> On 03/05/2021 01:54, David Gibson wrote:
> > On Fri, Apr 30, 2021 at 04:35:28PM -0300, Bruno Larsen (billionai) wrote:
> > > Moved all SPR read/write callback, and some related functions, to a
> > > new file specific for
On Mon, May 03, 2021 at 04:18:49PM +0100, Peter Maydell wrote:
> The pnv_psi.c code uses device_legacy_reset() for two purposes:
> * to reset itself from its qemu_register_reset() handler
> * to reset a XiveSource object it has
>
> Neither it nor the XiveSource have any qbuses, so the new
>
On Mon, May 03, 2021 at 04:18:48PM +0100, Peter Maydell wrote:
> The spapr_vio_quiesce_one() function resets the TCE table object
> (TYPE_SPAPR_TCE_TABLE) via device_legacy_reset(). We know that
> objects of that type do not have a qbus of their own, so the new
> device_cold_reset() function
On Mon, May 03, 2021 at 10:58:33PM +1000, Nicholas Piggin wrote:
> There are several new bits added to the hcall which reflect new issues
> found and new hardware mitigations.
>
> This adds the link stack flush behaviour, link stack flush accelerated
> instruction capability, and several L1D
On 4/30/21 9:45 AM, Max Reitz wrote:
>> + ``data_file_raw``
>> +If this option is set to ``on``, QEMU will always keep the external
>> +data file consistent as a standalone read-only raw image. It does
>> +this by forwarding updates through to the raw image in addition to
>> +
On 5/3/21 6:30 AM, Thomas Huth wrote:
We've started migrating the bug tickets from Launchpad to GitLab, so
it does not make too much sense anymore that users open new tickets
in the old system. Let's direct them now to the GitLab tracker instead.
Signed-off-by: Thomas Huth
Reviewed-by: John
This moved wait_for_console_pattern() to ConsoleMixIn.
By far this change required the most adaptations on tests.
Notice that:
1) Some tests from boot_linux_console.py were using the
wait_for_console_pattern()
from the avocado_qemu package rather than the overloaded method on the
This moved the last remaining _console_interaction() to ConsoleMixIn.
None tests call it directly, so only the other methods in ConsoleMixIn
needed to be adapted.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/avocado_qemu/__init__.py | 57 +++
1 file
It was the time of exec_command_and_wait_for_pattern() to find a new
home at ConsoleMixIn. This time various tests needed to be adapted.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/avocado_qemu/__init__.py | 29 +++---
tests/acceptance/boot_linux_console.py | 107
The avocado_qemu package provides the following methods to interact with the
guest via console, which are mainly used on the acceptance boot tests:
exec_command(), exec_command_and_wait_for_pattern(),
wait_for_console_pattern(),
interrupt_interactive_console_until_pattern()
Those methods are
This created the ConsoleMixIn class to wrap the methods related with console
interaction with the guest that currently are loose in the avocado_qemu
package. It should be used as a mixin on the test classes.
At this point only the interrupt_interactive_console_until_pattern() was moved
to
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/ppc/insn32.decode | 2 ++
> target/ppc/insn64.decode | 11 +++
> target/ppc/translate/fixedpoint-impl.c.inc | 5 +
> 3 files changed, 18 insertions(+)
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> scripts/decodetree.py | 50 ---
> 1 file changed, 23 insertions(+), 27 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Form a hex constant of the appropriate insnwidth.
> Begin using f-strings on changed lines.
>
> Signed-off-by: Richard Henderson
> ---
> scripts/decodetree.py | 66 +--
> 1 file changed, 38 insertions(+), 28
The ReplayKernelBase class uses the wait_for_console_pattern from its
parent LinuxKernelTest class, thus it doesn't need to import that method
from avocado_qemu.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/replay_kernel.py | 1 -
1 file changed, 1 deletion(-)
diff --git
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1
This moved exec_command() to ConsoleMixIn class.
Only the multiprocess.py file were touched by that change, so its tests
were adapted.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/avocado_qemu/__init__.py | 22 ++
tests/acceptance/multiprocess.py
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/ppc/helper.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 4/30/21 3:15 AM, Richard Henderson wrote:
> These will be used by the decodetree trans_* functions
> to early-exit when the instruction set is not enabled.
>
> Signed-off-by: Richard Henderson
> ---
> target/ppc/translate.c | 26 ++
> 1 file changed, 26 insertions(+)
On Tue, May 4, 2021 at 1:13 AM Paolo Bonzini wrote:
>
> On 03/05/21 09:12, Alistair Francis wrote:
> >> deprecated.rst is mainly thought for the things that only have been marked
> >> as deprecated, but not changed yet. Once it's done, the items normally get
> >> moved to
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/translate.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/translate.c
QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
and sifive_u machines. This patch moves that change from the
deprecated.rst file to the removed-features.rst file and the
target-riscv.rst.
Signed-off-by: Alistair Francis
---
docs/system/deprecated.rst | 19
This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
target/riscv/csr.c
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 6 --
target/riscv/cpu.c | 6 +-
2 files changed, 5 insertions(+), 7 deletions(-)
"Lucas Mateus Castro (alqotel)" writes:
> After the feedback from v1 I reworked the patch with suggested ideas and
> this version has less duplicated code and is overall simpler.
>
> This patch series is still a WIP, there are still 2 main problems I am
> trying to solve, I'll mention them in
The Sun4uMachine class inherit from LinuxKernelTest to effectively only use
the KERNEL_COMMON_COMMAND_LINE attribute. This change remove that unneeded
dependency, making Sun4uMachine self-content.
I took the occasion to delint the code: the unused os import was
removed, imports were reordered,
From: Emmanuel Blot
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id: 20210421133236.11323-1-emmanuel.b...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2
This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 10 --
target/riscv/csr.c | 12 ++--
target/riscv/translate.c | 19
From: Alexander Wagner
The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".
[1]
https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 11 ---
target/riscv/cpu_helper.c | 24 +++-
2 files
From: Emmanuel Blot
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id:
From: Frank Chang
ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-id:
From: Frank Chang
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.fran...@wdc.com
---
target/riscv/pmp.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1f5776316..78203291de
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.fran...@wdc.com
---
From: Vijai Kumar K
Add documentation for Shakti C reference platform.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210412174248.8668-1-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
docs/system/riscv/shakti-c.rst | 82
From: Hou Weiying
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 11 ---
target/riscv/cpu_helper.c | 32
target/riscv/csr.c
From: Hou Weiying
This commit adds support for ePMP v0.9.1.
The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 11 +++
target/riscv/csr.c | 37 ++---
The RISC-V spec says:
if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
pmpaddri-1 are ignored.
The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.
Update the pmp_is_locked() function to not check the supporting fields
and instead enforce
The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 1 +
1 file
From: LIU Zhiwei
The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id:
imply VIRTIO_VGA for the virt machine, this fixes the following error
when specifying `-vga virtio` as a command line argument:
qemu-system-riscv64: Virtio VGA not available
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 3 +-
target/riscv/csr.c | 80 +-
2 files
From: Hou Weiying
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.fran...@wdc.com
[ Changes by AF:
- Rebase on master
-
From: Jade Fink
Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.
Signed-off-by: Jade Fink
Reviewed-by: Alistair Francis
Message-id: 20210406113109.1031033-1-q...@jade.fyi
Signed-off-by:
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
From: Vijai Kumar K
This is the initial implementation of Shakti UART.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210401181457.73039-4-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
include/hw/char/shakti_uart.h | 74 ++
From: Hou Weiying
Use address 0x390 and 0x391 for the ePMP CSRs.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Reviewed-by: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.
Also add Bin who has been helping with reviews.
Signed-off-by: Alistair Francis
Acked-by: Bin Meng
Acked-by: Bastian Koppelmann
Reviewed-by: Philippe Mathieu-Daudé
Message-id:
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/csr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c
From: Vijai Kumar K
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id:
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 14 +-
target/riscv/csr.c | 629 +++--
2 files
From: Dylan Jhong
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong
Signed-off-by: Ruinland ChuanTzu Tsai
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210329034801.22667-1-dy...@andestech.com
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-id:
f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 44 ---
target/riscv/cpu.c| 2 +-
From: Vijai Kumar K
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210401181457.73039-5-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
include/hw/riscv/shakti_c.h | 2 ++
hw/riscv/shakti_c.c | 8
From: Atish Patra
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Message-Id: <20210319194534.2082397-2-atish.pa...@wdc.com>
[Changes by AF:
- Rebase on
From: Axel Heider
Fix style to have a proper description of the parameter 'force-raw'.
Signed-off-by: Axel Heider
Reviewed-by: Alistair Francis
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a65...@gmx.de
Signed-off-by: Alistair Francis
---
docs/system/generic-loader.rst | 9 ++---
1 file
From: Vijai Kumar K
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id:
From: Bin Meng
This was accidentally dropped before. Add it back.
Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id:
On 5/3/21 1:57 AM, Richard Henderson wrote:
> These were already present in tcg-target.c.inc,
> but not in the interpreter.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tci/tcg-target.h | 20 ++--
> tcg/tci.c| 40
> 2
The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' into
staging (2021-05-02 16:23:05 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/tci/tcg-target.h | 12 +--
> tcg/tci.c| 44
> tcg/tci/tcg-target.c.inc | 9
> 3 files changed, 59 insertions(+), 6
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/tci/tcg-target.h | 8
> tcg/tci.c| 42
> tcg/tci/tcg-target.c.inc | 32 ++
> 3 files changed, 78
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Inline it into its one caller, tci_write_reg64.
> Drop the asserts that are redundant with tcg_read_r.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tci.c | 13 ++---
> 1 file changed, 2 insertions(+), 11 deletions(-)
Reviewed-by:
Hi Richard,
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/internal.h | 5 +
> tcg/tcg.c | 5 ++---
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/internal.h b/tcg/internal.h
> index c2d5e9c42f..cd128e2a83 100644
>
On 5/3/21 4:36 PM, Eric Blake wrote:
> Back in commit d9f059aa6c (qemu-img: Deprecate use of -b without -F),
> we deprecated the ability to create a file with a backing image that
> requires qemu to perform format probing. Qemu can still probe older
> files for backwards compatibility, but it is
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Let the compiler decide on inlining.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/plugin-gen.c | 12 +---
> 1 file changed, 5 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/3/21 1:57 AM, Richard Henderson wrote:
> We're going to change how to look up the call flags from a TCGop,
> so extract it as a helper.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/internal.h | 33 +
> tcg/optimize.c | 3 ++-
> tcg/tcg.c | 15
Back in commit d9f059aa6c (qemu-img: Deprecate use of -b without -F),
we deprecated the ability to create a file with a backing image that
requires qemu to perform format probing. Qemu can still probe older
files for backwards compatibility, but it is time to finish off the
ability to create such
We've gone enough release cycles without noticeable pushback on our
intentions, so time to make it harder to create images that can form a
security hole due to a need for format probing rather than an explicit
format.
Eric Blake (2):
qcow2: Prohibit backing file changes in 'qemu-img amend'
This was deprecated back in bc5ee6da7 (qcow2: Deprecate use of
qemu-img amend to change backing file), and no one in the meantime has
given any reasons why it should be supported. Time to make change
attempts a hard error (but for convenience, specifying the _same_
backing chain is not
On Tue, Apr 27, 2021 at 12:31 AM Gerd Hoffmann wrote:
> Hi,
>
> > Questions: Is this support in QEMU and if so got any pointers to source
> for
> > existing examples?
> > If not, any guidance on how to proceed?
>
> qemu has only usb host controller emulation, not any usb device
> controller
Since commit 82bf7ae84ce ("target/arm: Remove KVM support for
32-bit Arm hosts") we can remove the comment / check added in
commit ab6b6a4 and directly run the bios-tables-test.
Reviewed-by: Eric Blake
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
On 5/3/21 4:10 PM, Philippe Mathieu-Daudé wrote:
> Now than we can probe if the TCG accelerator is available
that
> at runtime with a QMP command, do it once at the beginning
> and only register the tests we can run.
> We can then replace the #ifdef'ry by an assertion.
>
> Signed-off-by:
We might have a s390x/ppc64 QEMU binary built without the KVM
accelerator (configured with --disable-kvm).
Checking for /dev/kvm accessibility isn't enough, also check for the
accelerator in the binary.
Reviewed-by: David Gibson
Reviewed-by: Greg Kurz
Reviewed-by: Cornelia Huck
Reviewed-by:
Some tests require TCG, but don't have '_tcg' in their name,
while others do. Unify the test names by adding 'tcg' to the
TCG specific tests.
Reported-by: Igor Mammedov
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test.c | 8
1 file changed, 4 insertions(+), 4
Various tests don't require TCG, but have '_tcg' in their name.
As this is misleading, remove 'tcg' from their name.
Reported-by: Igor Mammedov
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test.c | 142 -
1 file changed, 71 insertions(+), 71
sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm()
tests are now only being run if KVM is available. Drop the TCG
fallback.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 2
The sve_tests_sve_off_kvm() test is KVM specific.
Only run it if KVM is available.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, only run these tests if TCG
is built into the QEMU binary.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
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