I mean: Please provide the QEMU command line parameters ... is this also
reproducible without libvirt? ... otherwise it might also be a problem
in libvirt instead...
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The QEMU project itself does not provide any binaries for Windows, so
I'm closing this ticket now. There are several people who provide
binaries for Windows, so if you want to get one of these changed, please
get in touch with the corresponding person who offers that binary
instead.
** Changed
How did you start QEMU? Does this still happen with the latest version
of QEMU?
** Changed in: qemu
Status: New => Incomplete
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https://bugs.launchpad.net/bugs/1863710
Title:
+-- On Wed, 5 May 2021, Li Qiang wrote --+
| P J P 于2021年5月5日周三 下午3:24写道：
| > - vg_ctrl_response(g, cmd, , sizeof(resp));
| > + vg_ctrl_response(g, cmd, , sizeof(resp.hdr));
| >
| > * While memset(3) is okay, should it also send header(hdr) size as
'resp_len'?
|
| I don't think so. This
You could try to build an image for this machine with buildroot (see
https://buildroot.org/). Anyway, I'm closing this ticket now since this
was not a bug.
** Changed in: qemu
Status: New => Invalid
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The QEMU project is currently moving its bug tracking to another system.
For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch
the state back
The QEMU project is currently moving its bug tracking to another system.
For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting older bugs to "Incomplete" now.
If you still think this bug report here is valid, then please switch
the state back
Aditya, does the problem still persist? If so, could you please provide
the QEMU command line as requested by Daniel?
** Changed in: qemu
Status: New => Incomplete
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I'm closing this now. If the problem still persists, please report it to
libslirp instead.
** Changed in: qemu
Status: New => Invalid
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https://bugs.launchpad.net/bugs/1863678
Could you please provide a test program for this issue?
** Tags added: graphics
** Changed in: qemu
Status: New => Incomplete
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https://bugs.launchpad.net/bugs/1891749
Title:
在 2021/5/6 上午5:10, Philippe Mathieu-Daudé 写道:
The compiler isn't clever enough to figure 'min_buf_size'
is a constant, so help it by using a definitions instead.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Jason Wang
---
hw/net/e1000e_core.c | 7 ---
1 file changed, 4
在 2021/5/5 下午3:46, Laurent Vivier 写道:
On 29/04/2021 09:26, Jason Wang wrote:
在 2021/4/28 下午6:14, Michael S. Tsirkin 写道:
On Tue, Apr 27, 2021 at 03:02:34PM +0100, Dr. David Alan Gilbert wrote:
* Laurent Vivier (lviv...@redhat.com) wrote:
In the failover case configuration,
Hi David,
Firstly, apologies for responding so late.
I have spinned off a v2 of this RFC patch addressing your recent review
comments at
https://lore.kernel.org/qemu-devel/20210506024924.85526-1-vaib...@linux.ibm.com
--
Cheers
~ Vaibhav
David Gibson writes:
> On Tue, Apr 20, 2021 at
On 5/5/2021 10:19 PM, Jason Wang wrote:
在 2021/5/2 下午12:10, Brad Smith 写道:
On 4/1/2021 3:24 AM, Jason Wang wrote:
在 2021/3/30 上午4:38, Brad Smith 写道:
On 3/28/2021 11:58 PM, Jason Wang wrote:
在 2021/3/29 上午11:03, Brad Smith 写道:
It very much is correct. We don't care about such releases
在 2021/5/3 下午9:53, Guenter Roeck 写道:
If a PHY does not exist, attempts to read from it should return 0x.
Otherwise the Linux kernel will believe that a PHY is there and select
the non-existing PHY. This in turn will result in network errors later
on since the real PHY is not selected or
Thank you.
On 5/5/2021 6:36 AM, Daniel P. Berrangé wrote:
The GDateTime APIs provided by GLib avoid portability pitfalls, such
as some platforms where 'struct timeval.tv_sec' field is still 'long'
instead of 'time_t'. When combined with automatic cleanup, GDateTime
often results in simpler code
On Thu, May 06, 2021 at 10:24:52AM +0800, Jason Wang wrote:
[ ... ]
> Ok, please send V2.
>
You should have it by now. Please let me know if it got lost.
Thanks,
Guenter
Add support for H_SCM_PERFORMANCE_STATS described at [1] for
spapr nvdimms. This enables guest to fetch performance stats[2] like
expected life of an nvdimm ('MemLife ') etc and display them to the
user. Linux kernel support for fetching these performance stats and
exposing them to the user-space
On 5/5/21 6:58 PM, Bin Meng wrote:
> Hi Guenter,
>
> On Tue, May 4, 2021 at 8:41 PM Guenter Roeck wrote:
>>
>> Commit dfc388797cc4 ("hw/arm: xlnx: Set all boards' GEM 'phy-addr'
>> property value to 23") configured the PHY address for xilinx-zynq-a9
>> to 23. When trying to boot xilinx-zynq-a9
在 2021/5/3 上午12:14, Guenter Roeck 写道:
On 5/2/21 9:09 AM, Bin Meng wrote:
On Mon, May 3, 2021 at 12:03 AM Guenter Roeck wrote:
If a PHY does not exist, attempts to read from it should return 0x.
Otherwise the Linux kernel will believe that a PHY is there and select
the non-existing PHY.
在 2021/5/3 上午12:03, Guenter Roeck 写道:
If a PHY does not exist, attempts to read from it should return 0x.
Otherwise the Linux kernel will believe that a PHY is there and select
the non-existing PHY. This in turn will result in network errors later
on since the real PHY is not selected or
On Wed, May 05, 2021 at 07:00:55PM +0200, Philippe Mathieu-Daudé wrote:
> The ALLOCA(3) man-page mentions its "use is discouraged".
>
> Replace it by a g_malloc() call.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
> ---
> target/ppc/kvm.c | 10 +-
> 1 file
在 2021/5/2 下午12:10, Brad Smith 写道:
On 4/1/2021 3:24 AM, Jason Wang wrote:
在 2021/3/30 上午4:38, Brad Smith 写道:
On 3/28/2021 11:58 PM, Jason Wang wrote:
在 2021/3/29 上午11:03, Brad Smith 写道:
It very much is correct. We don't care about such releases anymore.
So is there a doc/wiki to say
On Wed, May 05, 2021 at 11:10:35PM +0200, Philippe Mathieu-Daudé wrote:
> Use autofree heap allocation instead of variable-length
> array on the stack.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
> ---
> hw/intc/xics.c | 2 +-
> 1 file changed, 1 insertion(+), 1
On Wed, May 05, 2021 at 11:10:39PM +0200, Philippe Mathieu-Daudé wrote:
> Use autofree heap allocation instead of variable-length
> array on the stack.
>
> Signed-off-by: Philippe Mathieu-Daudé
fsl_etsec parts
Acked-by: David Gibson
> ---
> hw/net/fsl_etsec/rings.c | 9 -
>
On Wed, May 05, 2021 at 02:30:35PM -0300, Lucas Mateus Martins Araujo e Castro
wrote:
>
> On 03/05/2021 01:24, David Gibson wrote:
> > On Fri, Apr 30, 2021 at 03:40:46PM -0300, Lucas Mateus Castro (alqotel)
> > wrote:
> > > The functions ppc_store_lpcr, ppc_hash64_filter_pagesizes and
> > >
On Wed, May 05, 2021 at 11:10:45PM +0200, Philippe Mathieu-Daudé wrote:
> Use autofree heap allocation instead of variable-length
> array on the stack.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
> ---
> target/ppc/kvm.c | 2 +-
> 1 file changed, 1 insertion(+), 1
On Wed, May 05, 2021 at 11:10:34PM +0200, Philippe Mathieu-Daudé wrote:
> Use autofree heap allocation instead of variable-length
> array on the stack.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
> ---
> hw/ppc/pnv.c | 4 ++--
> hw/ppc/spapr.c |
在 2021/5/1 上午6:32, Si-Wei Liu 写道:
On 4/15/2021 1:04 AM, Jason Wang wrote:
This patch implements the doorbell mapping support for
vhost-vDPA. This is simply done by using mmap()/munmap() for the
vhost-vDPA fd during device start/stop. For the device without
doorbell support, we fall back to
On Fri, 2021-04-30 at 14:24 +0800, Yang Zhong wrote:
> From: Sean Christopherson
>
> KVM_CAP_SGX_ATTRIBUTE is a proposed capability for Intel SGX that can be
> used by userspace to enable privileged attributes, e.g. access to the
> PROVISIONKEY.
>
> Signed-off-by: Sean Christopherson
>
On Wed, May 05, 2021 at 06:09:10PM -0500, Eric Blake wrote:
> On 5/5/21 5:07 PM, Philippe Mathieu-Daudé wrote:
> > +Eric
> >
> > On 5/5/21 11:22 PM, Keith Busch wrote:
> >> On Wed, May 05, 2021 at 11:10:31PM +0200, Philippe Mathieu-Daudé wrote:
> >>> The compiler isn't clever enough to figure
On Wed, May 5, 2021 at 2:50 AM Lukas Jünger wrote:
>
> Signed-off-by: Lukas Jünger
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/char/sifive_uart.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
>
On Wed, Apr 21, 2021 at 7:37 AM Jose Martins wrote:
>
> The wfi exception trigger behavior should take into account user mode,
> hstatus.vtw, and the fact the an wfi might raise different types of
> exceptions depending on various factors:
>
> If supervisor mode is not present:
>
> - an illegal
On 4/27/21 5:03 AM, Markus Armbruster wrote:
John Snow writes:
On 4/25/21 9:27 AM, Markus Armbruster wrote:
John Snow writes:
Signed-off-by: John Snow
---
My hubris is infinite.
Score one of the three principal virtues of a programmer ;)
It was written before the prior review, but
On Thu, May 6, 2021 at 2:24 AM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode
Hi Guenter,
On Tue, May 4, 2021 at 8:41 PM Guenter Roeck wrote:
>
> Commit dfc388797cc4 ("hw/arm: xlnx: Set all boards' GEM 'phy-addr'
> property value to 23") configured the PHY address for xilinx-zynq-a9
> to 23. When trying to boot xilinx-zynq-a9 with zynq-zc702.dtb or
> zynq-zc706.dtb, this
From: Yuan Yao
Add new function x86_cpu_get_phys_page_attrs_encrypted_debug() to walking guset
page tables to do VA -> PA translation for encrypted guests.
Now install this to cc->get_phys_page_attrs_debug for INTEL TD guests only.
Signed-off-by: Yuan Yao
diff --git a/target/i386/cpu.h
On 4/27/21 4:43 AM, Markus Armbruster wrote:
John Snow writes:
On 4/25/21 8:34 AM, Markus Armbruster wrote:
value: object isn't wrong, but why not _ExprValue?
Updated excuse:
because all the way back outside in _parse, we know that:
1. expr is a dict (because of get_expr(False))
2.
From: Yuan Yao
Add below APIs for reading/writing the physical memory, subsequent
patch will use them in monitor commands and gdbstub to support
encrypted guest debugging.
uint32_t x86_ldl_phys_debug(CPUState *cs, hwaddr addr);
uint64_t x86_ldq_phys_debug(CPUState *cs, hwaddr addr);
void
From: Yuan Yao
Now only set the RAM's debug_ops for INTEL TD guests, SEV can also
rely on the common part introduced in previous patch or introduce
new debug_ops implementation if it's necessary.
Signed-off-by: Yuan Yao
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index d5a4345f44..772b19c524
From: Brijesh Singh
The new callbacks can be used to display the guest memory of an SEV guest
by registering callbacks to the SEV memory encryption/decryption APIs.
Typical usage:
mem_read(uint8_t *dest,
const uint8_t *hva_src, hwaddr gpa_src,
uint32_t len, MemTxAttrs attrs);
From: Yuan Yao
Please comment if some changes are incorrect or I missed something here.
Signed-off-by: Yuan Yao
diff --git a/dump/dump.c b/dump/dump.c
index 929138e91d..21eb018092 100644
--- a/dump/dump.c
+++ b/dump/dump.c
@@ -1746,7 +1746,7 @@ static void dump_init(DumpState *s, int fd, bool
From: Yuan Yao
The new functions are added into target/i386/kvm/kvm.c as common functions
to support encrypted guest for KVM on x86.
Now we enable these only for INTEL TD guests.
Signed-off-by: Yuan Yao
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 05bf4f8b8b..5050b2a82f
From: Brijesh Singh
A subsequent patch will set the debug=1 when issuing a memory access
from the gdbstub or HMP commands. This is a prerequisite to support
debugging an encrypted guest. When a request with debug=1 is seen, the
encryption APIs will be used to access the guest memory.
From: Ashish Kalra
Yuan Yao:
- Fixed fuzz_dma_read_cb() parameter issue for QEMU 5.2.91.
- Move the caller of encrypted_memory_debug_ops into phymem.c
as common callbacks for encrypted guests.
- Adapted address_space_read_debug/address_space_wirte_rom_debug
with new
From: Ashish Kalra
The MemoryDebugOps are used by cpu_memory_rw_debug() and default to
address_space_read and address_space_write_rom.
Yuan Yao: Exports the physical_memory_debug_ops variable for functions
in target/i386/helper.c
Signed-off-by: Ashish Kalra
Signed-off-by: Yuan Yao
diff
From: Yuan Yao
This interface is designed to setup the MemoryRegion::debug_ops.
Also introduced 2 wrapper functions for installing/calling the
KVMState::set_mr_debug_ops from different targets easily.
Signed-off-by: Yuan Yao
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index
From: Yuan Yao
This RFC series introduces the basic framework and a common
implementation on x86 to handle encrypted guest memory
reading/writing, to support QEMU's built-in guest debugging
features, like the monitor command xp and gdbstub.
The encrypted guest which its memory and/or register
On 4/21/21 11:07 PM, John Snow wrote:
+self.exprs: List[Expression] = []
I did indeed intend to use Expression to mean TopLevelExpr ... However,
in this case, that's not what actually gets stored here.
I tricked myself!
This stores the dict that associates 'expr', 'doc' and 'info'.
On Wed, May 5, 2021, 5:10 PM Eric Blake wrote:
> On 5/5/21 5:07 PM, Philippe Mathieu-Daudé wrote:
> > +Eric
> >
> > On 5/5/21 11:22 PM, Keith Busch wrote:
> >> On Wed, May 05, 2021 at 11:10:31PM +0200, Philippe Mathieu-Daudé wrote:
> >>> The compiler isn't clever enough to figure
FYI, to provide an update - I found a workaround! It's related to the
CPU selection. I can't seem to pass through my host CPU, even with
v6.0.0 of qemu. Rather, I have to use the qemu64 CPU.
--
You received this bug notification because you are a member of qemu-
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Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 11 ---
target/riscv/cpu_helper.c | 24 +++-
2 files
From: Emmanuel Blot
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id: 20210421133236.11323-1-emmanuel.b...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/translate.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/translate.c
From: Frank Chang
ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-id:
This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
target/riscv/csr.c
From: LIU Zhiwei
The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id:
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 6 --
target/riscv/cpu.c | 6 +-
2 files changed, 5 insertions(+), 7 deletions(-)
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a
From: Alexander Wagner
The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".
[1]
https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 11 +++
target/riscv/csr.c | 37 ++---
From: Emmanuel Blot
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id:
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 11 ---
target/riscv/cpu_helper.c | 32
target/riscv/csr.c
From: Frank Chang
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
From: Hou Weiying
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 14 +-
target/riscv/csr.c | 629 +++--
2 files
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 3 +-
target/riscv/csr.c | 80 +-
2 files
From: Hou Weiying
This commit adds support for ePMP v0.9.1.
The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 1 +
1 file
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1
From: Hou Weiying
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.fran...@wdc.com
[ Changes by AF:
- Rebase on master
-
From: Hou Weiying
Use address 0x390 and 0x391 for the ePMP CSRs.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Reviewed-by: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-id:
f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 44 ---
target/riscv/cpu.c| 2 +-
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h
From: Vijai Kumar K
Add documentation for Shakti C reference platform.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210412174248.8668-1-vi...@behindbytes.com
Signed-off-by: Bin Meng
[ Changes from Bin Meng:
- Add missing TOC
Message-id:
The RISC-V spec says:
if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
pmpaddri-1 are ignored.
The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.
Update the pmp_is_locked() function to not check the supporting fields
and instead enforce
From: Vijai Kumar K
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210401181457.73039-5-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
include/hw/riscv/shakti_c.h | 2 ++
hw/riscv/shakti_c.c | 8
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 10 --
target/riscv/csr.c | 12 ++--
target/riscv/translate.c | 19
From: Jade Fink
Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.
Signed-off-by: Jade Fink
Reviewed-by: Alistair Francis
Message-id: 20210406113109.1031033-1-q...@jade.fyi
Signed-off-by:
imply VIRTIO_VGA for the virt machine, this fixes the following error
when specifying `-vga virtio` as a command line argument:
qemu-system-riscv64: Virtio VGA not available
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
From: Vijai Kumar K
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id:
From: Vijai Kumar K
This is the initial implementation of Shakti UART.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210401181457.73039-4-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
include/hw/char/shakti_uart.h | 74 ++
Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.
Also add Bin who has been helping with reviews.
Signed-off-by: Alistair Francis
Acked-by: Bin Meng
Acked-by: Bastian Koppelmann
Reviewed-by: Philippe Mathieu-Daudé
Message-id:
From: Bin Meng
This was accidentally dropped before. Add it back.
Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id:
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.fran...@wdc.com
---
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/csr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c
From: Vijai Kumar K
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id:
From: Axel Heider
Fix style to have a proper description of the parameter 'force-raw'.
Signed-off-by: Axel Heider
Reviewed-by: Alistair Francis
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a65...@gmx.de
Signed-off-by: Alistair Francis
---
docs/system/generic-loader.rst | 9 ++---
1 file
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.fran...@wdc.com
---
target/riscv/pmp.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1f5776316..78203291de
From: Atish Patra
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Message-Id: <20210319194534.2082397-2-atish.pa...@wdc.com>
[Changes by AF:
- Rebase on
From: Dylan Jhong
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong
Signed-off-by: Ruinland ChuanTzu Tsai
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210329034801.22667-1-dy...@andestech.com
The following changes since commit d45a5270d075ea589f0b0ddcf963a5fea1f500ac:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging
(2021-05-05 13:52:00 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git
On Thu, May 6, 2021 at 5:28 AM Peter Maydell wrote:
>
> On Mon, 3 May 2021 at 23:13, Alistair Francis
> wrote:
> >
> > The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
> >
> > Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502'
> > into
On 5/5/21 5:07 PM, Philippe Mathieu-Daudé wrote:
> +Eric
>
> On 5/5/21 11:22 PM, Keith Busch wrote:
>> On Wed, May 05, 2021 at 11:10:31PM +0200, Philippe Mathieu-Daudé wrote:
>>> The compiler isn't clever enough to figure 'SEG_CHUNK_SIZE' is
>>> a constant! Help it by using a definitions instead.
On Fri, Apr 30, 2021 at 5:08 PM Bin Meng wrote:
>
> shakti_c machine documentation was missed in the riscv target doc.
>
> Signed-off-by: Bin Meng
In order to not break the doc build I squashed this commit into the
original one adding the documentation.
Alistair
> ---
>
>
On Fri, Apr 30, 2021 at 5:08 PM Bin Meng wrote:
>
> shakti_c machine documentation was missed in the riscv target doc.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> docs/system/target-riscv.rst | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
+Eric
On 5/5/21 11:22 PM, Keith Busch wrote:
> On Wed, May 05, 2021 at 11:10:31PM +0200, Philippe Mathieu-Daudé wrote:
>> The compiler isn't clever enough to figure 'SEG_CHUNK_SIZE' is
>> a constant! Help it by using a definitions instead.
>
> I don't understand.
Neither do I TBH...
> It's
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):
CID 1452921: Integer handling issues:
Potentially overflowing expression "1 << w" with type "int"
(32 bits, signed) is evaluated using 32-bit arithmetic, and
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