Still reproducible with the current qemu version from git (commit
7fe7fae8b48e3f9c647fd685)
** Tags added: net
** Changed in: qemu
Status: New => Confirmed
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On 6/9/21 4:21 AM, Alex Bennée wrote:
Richard Henderson writes:
There's a change in mprotect() behaviour [1] in the latest macOS
on M1 and it's not yet clear if it's going to be fixed by Apple.
In this case, instead of changing permissions of N guard pages,
we change permissions of N rwx
This is still reproducible with the current qemu git version (commit
7fe7fae8b48e3f9c647f)
** Tags added: block
** Changed in: qemu
Status: New => Confirmed
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* Dr. David Alan Gilbert (dgilb...@redhat.com) wrote:
> * Stefan Hajnoczi (stefa...@redhat.com) wrote:
> > Instead I was thinking about VHOST_USER_DMA_READ/WRITE messages
> > containing the address (a device IOVA, it could just be a guest physical
> > memory address in most cases) and the
On Thu, Jun 10, 2021 at 05:53:35PM +0300, Konstantin Kostiuk wrote:
> Hi All,
>
> For freeing GMatchInfo struct, a special function is required. I'm not sure is
> it possible to use g_autoptr in this case or no.
> In GLib example
>
This is still reproducible with the current git version (commit
7fe7fae8b48e3f9c647fd685e5155ebc8e6fb84d) and clang with ASAN enabled.
** Changed in: qemu
Status: New => Confirmed
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Still reproducible with the current qemu version from git (commit
7fe7fae8b48e3f9c647fd685)
** Tags added: usb
** Changed in: qemu
Status: New => Confirmed
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On 6/9/21 7:59 AM, Luis Fernando Fujita Pires wrote:
From: Richard Henderson
Return output buffer and size via output pointer arguments, rather than
returning size via tcg_ctx->code_gen_buffer_size.
Signed-off-by: Richard Henderson
---
tcg/region.c | 15 +++
1 file changed, 7
On 6/10/21 1:45 AM, Philippe Mathieu-Daudé wrote:
> Having the HMP/QMP commands defined in monitor.c makes the stubs
> rather complicated when SEV is not built in. To simplify, move the
> SEV functions to sev.c, and remove a layer of stubs.
>
> Also make it clearer when SEV is not built in, so
On 6/9/21 7:58 AM, Luis Fernando Fujita Pires wrote:
From: Richard Henderson
There is only one caller, and shortly we will need access to the MachineState,
which tcg_init_machine already has.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 2 ++
include/sysemu/tcg.h
10.06.2021 17:21, Emanuele Giuseppe Esposito wrote:
On 10/06/2021 13:12, Vladimir Sementsov-Ogievskiy wrote:
10.06.2021 13:46, Emanuele Giuseppe Esposito wrote:
On 10/06/2021 12:27, Vladimir Sementsov-Ogievskiy wrote:
10.06.2021 13:14, Emanuele Giuseppe Esposito wrote:
On 09/06/2021
Hi All,
For freeing GMatchInfo struct, a special function is required. I'm not sure is
it possible to use g_autoptr in this case or no.
In GLib example
https://developer.gnome.org/glib/stable/glib-Perl-compatible-regular-expressions.html#g-regex-match,
g_match_info_free is used directly.
Best
On 6/10/21 1:45 AM, Philippe Mathieu-Daudé wrote:
> Declarations don't require these headers, remove them.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Connor Kuehl
On 6/10/21 1:45 AM, Philippe Mathieu-Daudé wrote:
> -uint64_t
> -sev_get_me_mask(void)
> -{
> -return sev_guest ? sev_guest->me_mask : ~0;
> -}
> -
> uint32_t
> sev_get_cbit_position(void)
> {
> @@ -810,8 +803,6 @@ int sev_kvm_init(ConfidentialGuestSupport *cgs, Error
> **errp)
>
On 6/10/21 1:45 AM, Philippe Mathieu-Daudé wrote:
> The unique sev_encrypt_flash() invocation (in pc_system_flash_map)
> is protected by the "if (sev_enabled())" check, so is not
> reacheable.
> Replace the abort() call in sev_es_save_reset_vector() by
> g_assert_not_reached() which meaning is
On 6/10/21 1:45 AM, Philippe Mathieu-Daudé wrote:
> Commit 00b81053244 ("target-i386: Remove assert_no_error usage")
> forgot to add the "qapi/error.h", add it now.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Connor Kuehl
On 6/10/21 1:45 AM, Philippe Mathieu-Daudé wrote:
> If the management layer tries to inject a secret, it gets an empty
> response in case the binary built without SEV:
>
> { "execute": "sev-inject-launch-secret",
> "arguments": { "packet-header": "mypkt", "secret": "mypass", "gpa":
>
On 09/06/2021 14:25, Vladimir Sementsov-Ogievskiy wrote:
08.06.2021 10:33, Emanuele Giuseppe Esposito wrote:
Add a CoMutex to protect concurrent access of block-copy
data structures.
This mutex also protects .copy_bitmap, because its thread-safe
API does not prevent it from assigning two
From: Ruinaldn ChuanTzu Tsai
The changes from V2 :
* Making custom CSR operation table become registerable.
* Re-use the riscv_csrrw() code instead of ducplication.
* Splitting custom CPU bits into seperated files.
* Splitting the AX25 CPU from the feature patch
* Adding custom/vendor value
From: Ruinaldn ChuanTzu Tsai
Adding the skeleton of Andes Technology AX25 CPU model for the future commits,
which will utilize custom/vendor CSR handling mechaism.
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c
From: Ruinaldn ChuanTzu Tsai
For now we add a custom CSR handling mechanism to handle non-standard CSR read
or write.
The write_stub() and read_zero() are provided for quick placeholder usage if
such CSRs' behavior are expected to fail-over in its user code.
For demonstration, we modify Andes
10.06.2021 17:04, Eric Blake wrote:
Maybe the thing to do is improve the documentation and try to avoid
ambiguous terminalogy; in qemu:allocation-depth, a return of depth 0
should be called "absent", not "unallocated". And in libnbd, a
base:allocation of 0 should be "data" or "normal", not
Hi
On Thu, Jun 10, 2021 at 6:38 PM Kostiantyn Kostiuk
wrote:
> The g_regex_match function creates match_info even if it
> returns FALSE. So we should always call g_match_info_free.
>
> Signed-off-by: Kostiantyn Kostiuk
> ---
> qga/commands-win32.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
On Thu, Jun 10, 2021 at 03:35:37PM +0200, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> hw/core/machine.c | 4
> 1 file changed, 4 insertions(+)
Reviewed-by: Daniel P. Berrangé
Regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange
On Thu, Jun 10, 2021 at 03:35:38PM +0200, Paolo Bonzini wrote:
> Make -smp syntactic sugar for a compound property "-machine
> smp.{cores,threads,cpu,...}". machine_smp_parse is replaced by the
> setter for the property.
>
> numa-test will now cover the new syntax, while other tests
> still use
The g_regex_match function creates match_info even if it
returns FALSE. So we should always call g_match_info_free.
Signed-off-by: Kostiantyn Kostiuk
---
qga/commands-win32.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
index
On Thu, Jun 10, 2021 at 03:35:36PM +0200, Paolo Bonzini wrote:
> As part of converting -smp to a property with a QAPI type, define
> the struct and use it to do the actual parsing. machine_smp_parse
> takes care of doing the QemuOpts->QAPI conversion by hand, for now.
>
> Signed-off-by: Paolo
On 6/9/21 8:07 AM, Daniel P. Berrangé wrote:
I think that's overthinking things. Even a small QEMU install is
10s of MB in size once you add up the qemu binary, firmware blobs
and depedancies. If we only keep the raw help text from the json,
we'll have < 1/2 MB, which is lost in the noise of
On Thu, Jun 10, 2021 at 03:35:35PM +0200, Paolo Bonzini wrote:
> Clean up the smp_parse functions to use Error** instead of exiting.
>
> Signed-off-by: Paolo Bonzini
> ---
> hw/core/machine.c| 34 +++---
> hw/i386/pc.c | 28 ++--
>
On Thu, Jun 10, 2021 at 03:35:34PM +0200, Paolo Bonzini wrote:
> Most of smp_parse and pc_smp_parse is guarded by an "if (opts)"
> conditional, and the rest is common to both function. Move the
> conditional and the common code to the caller, machine_smp_parse.
>
> Move the replay_add_blocker
On Thu, 10 Jun 2021 at 15:16, Alex Bennée wrote:
>
>
> Peter Maydell writes:
> > I'm told that the Arm C compiler C library always assumes that
> > the "stack base" value is what it should set SP to, so reporting 0
> > for that will break binaries that were built with it.
> >
> > As the TODO
Commit 9257e514d861afa7 introduced lookup_name(), which will calls
lo_find(), to increase the refcount of the inodes used in lo_rename,
lo_rmdir, and lo_unlink.
However, as lo_find() increases both refcount and nlookup, and the
three functions do not need to increase nlookup,
On 10/06/2021 13:12, Vladimir Sementsov-Ogievskiy wrote:
10.06.2021 13:46, Emanuele Giuseppe Esposito wrote:
On 10/06/2021 12:27, Vladimir Sementsov-Ogievskiy wrote:
10.06.2021 13:14, Emanuele Giuseppe Esposito wrote:
On 09/06/2021 11:12, Vladimir Sementsov-Ogievskiy wrote:
08.06.2021
On 6/10/21 6:25 AM, Peter Maydell wrote:
Currently we provide Hn and H1_n macros for accessing the correct
data within arrays of vector elements of size 1, 2 and 4, accounting
for host endianness. We don't provide any macros for elements of
size 8 because there the host endianness doesn't
Peter Maydell writes:
> On Thu, 10 Jun 2021 at 11:26, Alex Bennée wrote:
>>
>> The previous numbers were a guess at best. While we could extract the
>> information from a loaded ELF file via -kernel we could still get
>> tripped up by self decompressing or relocating code. Besides sane
>>
On 6/7/21 9:58 AM, Peter Maydell wrote:
+if (dc_isar_feature(aa32_mve, s)) {
+TCGv_i32 eci;
+
+mve_update_eci(s);
+eci = tcg_const_i32(s->eci << 4);
+store_cpu_field(eci, condexec_bits);
+}
I think it would be handy to package this up into an
On 6/10/21 3:25 PM, Peter Maydell wrote:
> Currently we provide Hn and H1_n macros for accessing the correct
> data within arrays of vector elements of size 1, 2 and 4, accounting
> for host endianness. We don't provide any macros for elements of
> size 8 because there the host endianness doesn't
** No longer affects: qemu
** Changed in: nova
Importance: Undecided => Medium
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https://bugs.launchpad.net/bugs/1929710
Title:
virDomainGetBlockJobInfo fails during swap_volume as
10.06.2021 16:47, Eric Blake wrote:
On Thu, Jun 10, 2021 at 03:30:17PM +0300, Vladimir Sementsov-Ogievskiy wrote:
The correct fix is for ovirt to additionally use the
qemu:allocation-depth metadata context added in 5.2: after all, the
actual determination for what is needed to recreate a qcow2
Peter Maydell writes:
> On Thu, 10 Jun 2021 at 11:26, Alex Bennée wrote:
>>
>> The previous numbers were a guess at best. While we could extract the
>> information from a loaded ELF file via -kernel we could still get
>> tripped up by self decompressing or relocating code. Besides sane
>>
On Thu, Jun 10, 2021 at 09:05:18AM +0100, Steven Price wrote:
> On 09/06/2021 18:41, Catalin Marinas wrote:
> > On Wed, Jun 09, 2021 at 12:19:31PM +0100, Marc Zyngier wrote:
> >> On Wed, 09 Jun 2021 11:51:34 +0100,
> >> Steven Price wrote:
> >>> On 09/06/2021 11:30, Marc Zyngier wrote:
> On
On 6/7/21 9:58 AM, Peter Maydell wrote:
Implement the MVE VADDV insn, which performs an addition
across vector lanes.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 7 ++
target/arm/mve.decode | 2 ++
target/arm/mve_helper.c| 24 +++
Hi,
> Is the JSON file completely static, listing all modules that were built
> regardless of whether they are currently installed, or would it need to
> be refreshed when installing/uninstalling RPMs with modules ? I would
> think we can do the former and simply handle missing modules on disk
On Thu, Jun 10, 2021 at 04:16:27PM +0300, Nir Soffer wrote:
> On Thu, Jun 10, 2021 at 2:52 AM Nir Soffer wrote:
> >
> > On Wed, Jun 9, 2021 at 9:01 PM Eric Blake wrote:
>
> I posted a work in progress patch implementing support for
> qemu:joint-allocaition
> in oVirt:
>
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/404
** Changed in: qemu
Status: New => Expired
** Bug
On 6/10/21 5:40 AM, Peter Maydell wrote:
+#define DO_1OP(OP, ESIZE, TYPE, H, FN) \
+void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
+{ \
+TYPE *d = vd, *m =
On Tue, 8 Jun 2021 at 22:33, Richard Henderson
wrote:
>
> On 6/7/21 9:57 AM, Peter Maydell wrote:
> > +#define DO_VLDR(OP, ESIZE, LDTYPE, TYPE, H) \
> > +void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr)\
> > +{
On Thu, Jun 10, 2021 at 03:35:33PM +0200, Paolo Bonzini wrote:
> In order to make SMP configuration a Machine property, we need a getter as
> well as a setter. To simplify the implementation put everything that the
> getter needs in the CpuTopology struct.
>
> Signed-off-by: Paolo Bonzini
> ---
On Thu, Jun 10, 2021 at 03:35:32PM +0200, Paolo Bonzini wrote:
> -M was the sole user of qemu_opts_set and qemu_opts_set_defaults,
> remove them and the arguments that they used.
>
> Signed-off-by: Paolo Bonzini
> ---
> include/qemu/option.h | 3 ---
> tests/unit/test-qemu-opts.c | 35
On Thu, Jun 10, 2021 at 03:35:30PM +0200, Paolo Bonzini wrote:
> Allow parsing multiple keyval sequences into the same dictionary.
> This will be used to simplify the parsing of the -M command line
> option, which is currently a .merge_lists = true QemuOpts group.
>
> Signed-off-by: Paolo Bonzini
On Thu, Jun 10, 2021 at 03:35:28PM +0200, Paolo Bonzini wrote:
> Machines and accelerators are not user-creatable but they are going
> to share similar command-line parsing machinery. Export functions
> that will be used with -machine and -accel in softmmu/vl.c.
>
> Signed-off-by: Paolo Bonzini
On Thu, Jun 10, 2021 at 03:30:17PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> > > The correct fix is for ovirt to additionally use the
> > > qemu:allocation-depth metadata context added in 5.2: after all, the
> > > actual determination for what is needed to recreate a qcow2 file is
> > > not
On 10/06/21 15:17, Peng Liang wrote:
Based on the description of error_setg(), the local variable err in
qemu_init_subsystems() should be initialized to NULL.
Fix: efd7ab22fb "vl: extract qemu_init_subsystems"
Signed-off-by: Peng Liang
---
The patch is generated by the following coccinelle
On 07/06/21 15:52, Maxim Levitsky wrote:
I used to have a patch series that was about to fix the block limits of the
scsi-block,
which I think is similar to this patch series.
Sorry that I kind of forgot about it for too much time.
As part of converting -smp to a property with a QAPI type, define
the struct and use it to do the actual parsing. machine_smp_parse
takes care of doing the QemuOpts->QAPI conversion by hand, for now.
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c | 33 +++--
On 6/10/21 3:17 AM, Peter Maydell wrote:
Can't use tcg_constant_i32() because store_cpu_field() wants to
tcg_temp_free_i32() its argument.
Yes you can. I thought I documented somewhere that constant is silently
ignored by free. Oh dear, now I see that I have conflicting docs -- will fix.
> On Jun 10, 2021, at 9:14 AM, Peter Maydell wrote:
>
> On Thu, 10 Jun 2021 at 14:02, Programmingkid
> wrote:
>>
>> Hi Richard,
>>
>> There is a function called breakpoint_invalidate() in cpu.c that calls a
>> function called tb_flush(). I have determined that this call is being made
>>
In order to make SMP configuration a Machine property, we need a getter as
well as a setter. To simplify the implementation put everything that the
getter needs in the CpuTopology struct.
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c | 1 +
hw/i386/pc.c | 4 +---
Make -smp syntactic sugar for a compound property "-machine
smp.{cores,threads,cpu,...}". machine_smp_parse is replaced by the
setter for the property.
numa-test will now cover the new syntax, while other tests
still use -smp.
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c | 108
Clean up the smp_parse functions to use Error** instead of exiting.
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c| 34 +++---
hw/i386/pc.c | 28 ++--
include/hw/boards.h | 2 +-
include/hw/i386/pc.h | 2 --
4 files changed,
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 9ad8341a31..ffc076ae84 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -746,6 +746,10 @@ static void smp_parse(MachineState *ms,
** Changed in: qemu
Status: Incomplete => New
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https://bugs.launchpad.net/bugs/1883593
Title:
Windows XP takes much longer to boot in TCG mode since 5.0
Status in QEMU:
New
Switch from QemuOpts to keyval. This enables the introduction
of non-scalar machine properties, and JSON syntax in the future.
For JSON syntax to be supported right now, we would have to
consider what would happen if string-based dictionaries (produced by
-M key=val) were to be merged with
Machines and accelerators are not user-creatable but they are going
to share similar command-line parsing machinery. Export functions
that will be used with -machine and -accel in softmmu/vl.c.
Signed-off-by: Paolo Bonzini
---
include/qom/object.h| 23
Most of smp_parse and pc_smp_parse is guarded by an "if (opts)"
conditional, and the rest is common to both function. Move the
conditional and the common code to the caller, machine_smp_parse.
Move the replay_add_blocker call after all errors are checked for.
Signed-off-by: Paolo Bonzini
---
This patch introduces a function that merges two keyval-produced
(or keyval-like) QDicts. It can be used to emulate the behavior of
.merge_lists = true QemuOpts groups, merging -readconfig sections and
command-line options in a single QDict, and also to implement -set.
Signed-off-by: Paolo
Allow parsing multiple keyval sequences into the same dictionary.
This will be used to simplify the parsing of the -M command line
option, which is currently a .merge_lists = true QemuOpts group.
Signed-off-by: Paolo Bonzini
---
include/qemu/option.h | 2 ++
util/keyval.c | 43
-M was the sole user of qemu_opts_set and qemu_opts_set_defaults,
remove them and the arguments that they used.
Signed-off-by: Paolo Bonzini
---
include/qemu/option.h | 3 ---
tests/unit/test-qemu-opts.c | 35 -
util/qemu-option.c | 51
This series converts -M to keyval parsing, so that they can use
compound properties. The series also converts -smp to a
compound property.
This is also a preparatory work for SGX support, which would like to use
an array-type machine property.
Patches 1-3 introduce the infrastructure and the
On Thu, Jun 10, 2021 at 02:52:10AM +0300, Nir Soffer wrote:
> > So, as a convenience, we can provide yet another metadata context,
> > "qemu:joint-allocation", which provides the bulk of the same
> > information already available from using "base:allocation" and
> > "qemu:allocation-depth" in
On 6/10/2021 3:32 PM, Markus Armbruster wrote:
> Peng Liang writes:
>
>> On 6/9/2021 8:15 PM, Daniel P. Berrangé wrote:
>>> On Wed, Jun 09, 2021 at 02:09:47PM +0200, Markus Armbruster wrote:
Paolo Bonzini writes:
> On 10/06/21 10:47, Zhenzhong Duan wrote:
>> Based on the
On 6/9/21 6:43 PM, LIU Zhiwei wrote:
1)First a multiply instruction, if the source value big enough, it will return
a result with some bits not zero in MSW 32-bit.
Multiply is fine. Input bits outside the low 32 cannot appear in the low 32 of
the output. Multiply-high-part on the other hand
On Thu, Jun 10, 2021 at 09:17:29PM +0800, Peng Liang wrote:
> Based on the description of error_setg(), the local variable err in
> qemu_init_subsystems() should be initialized to NULL.
>
> Fix: efd7ab22fb "vl: extract qemu_init_subsystems"
> Signed-off-by: Peng Liang
> ---
> The patch is
Currently we provide Hn and H1_n macros for accessing the correct
data within arrays of vector elements of size 1, 2 and 4, accounting
for host endianness. We don't provide any macros for elements of
size 8 because there the host endianness doesn't matter. However,
this does result in
On 10/06/2021 14:14, Peter Maydell wrote:
On Thu, 10 Jun 2021 at 14:02, Programmingkid wrote:
Hi Richard,
There is a function called breakpoint_invalidate() in cpu.c that calls a
function called tb_flush(). I have determined that this call is being made over
200,000 times when Windows XP
Based on the description of error_setg(), the local variable err in
qemu_init_subsystems() should be initialized to NULL.
Fix: efd7ab22fb "vl: extract qemu_init_subsystems"
Signed-off-by: Peng Liang
---
The patch is generated by the following coccinelle script (thanks to
Markus):
@ r @
On Thu, Jun 10, 2021 at 4:06 PM Eric Blake wrote:
>
> On Thu, Jun 10, 2021 at 01:20:13AM +0300, Nir Soffer wrote:
> > > + else if (strcmp (metacontext, "qemu:joint-allocation") == 0) {
> > > +/* Combo of base:allocation and stripped-down qemu:allocation-depth
> > > */
> > > +const char
On Thu, Jun 10, 2021 at 2:52 AM Nir Soffer wrote:
>
> On Wed, Jun 9, 2021 at 9:01 PM Eric Blake wrote:
I posted a work in progress patch implementing support for
qemu:joint-allocaition
in oVirt:
https://gerrit.ovirt.org/c/ovirt-imageio/+/115197
The most important part is the nbd client:
From: hchkuo
The Data Object Exchange implementation of CXL Compliance Mode is
referring to "Compute Express Link (CXL) Specification, Rev. 2.0, Oct.
2020".
The data structure of CXL compliance request and response is added to
the header. Due to the scope limitation of QEMU, most of the
From: hchkuo
Pre-built CDAT table for testing, contains one CDAT header and six
CDAT entries: DSMAS, DSLBIS, DSMSCIS, DSIS, DSEMTS, and SSLBIS
respectively.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
tests/data/cdat/cdat.dat | Bin 0 -> 148 bytes
1 file changed, 0 insertions(+), 0
From: hchkuo
PCIe Data Object Exchange (DOE) implementation for QEMU referring to
"PCIe Data Object Exchange ECN, March 12, 2020".
The patch supports multiple DOE capabilities for a single PCIe device in
QEMU. For each capability, a static array of DOEProtocol should be
passed to
From: hchkuo
Macros for the vender ID of PCI-SIG mentioned in "PCIe Data Object
Exchange ECN, March 12, 2020" and the size of PCIe Data Object
Exchange.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
include/hw/pci/pci_ids.h | 3 +++
include/hw/pci/pcie_regs.h | 4
2 files
From: hchkuo
The Data Object Exchange implementation of CXL Coherent Device Attribute
Table (CDAT). This implementation is referring to "Coherent Device
Attribute Table Specification, Rev. 1.02, Oct. 2020" and "Compute
Express Link Specification, Rev. 2.0, Oct. 2020"
The CDAT can be specified
From: hchkuo
Linux standard header for the registers of PCI Data Object Exchange
(DOE). This header might be generated via script. The DOE feature
should be added in the future Linux release so this patch can be
removed then.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
On Thu, 10 Jun 2021 at 14:02, Programmingkid wrote:
>
> Hi Richard,
>
> There is a function called breakpoint_invalidate() in cpu.c that calls a
> function called tb_flush(). I have determined that this call is being made
> over 200,000 times when Windows XP boots. Disabling this function makes
On Thu, Jun 10, 2021 at 03:04:24PM +0200, Gerd Hoffmann wrote:
> Hi Paolo,
>
> > +if config_host.has_key('CONFIG_MODULES')
> > + qemu_modinfo = executable('qemu-modinfo', files('qemu-modinfo.c') +
> > genh,
> > + dependencies: [glib, qemuutil], install:
> >
On 6/10/21 2:23 PM, Gerd Hoffmann wrote:
> On Thu, Jun 10, 2021 at 12:34:14PM +0200, Claudio Fontana wrote:
>> On 6/10/21 12:15 PM, Gerd Hoffmann wrote:
>>> Based on the "modules: add metadata database" patch series sent
>>> earlier today. Adds support for target-specific modules to the
>>>
On 10/06/21 07:42, Markus Armbruster wrote:
Paolo Bonzini (12):
qom: export more functions for use with non-UserCreatable objects
keyval: introduce keyval_merge
keyval: introduce keyval_parse_into
vl:
Hi,
> Build qtest modular on top of that was easy, patch below.
>
> I'm not convinced though that the approach will work for other
> accelerators too given that they have dependencies to directories
> outside accel/ ...
Oh, it depends on how high you hang the tcg modularization bar.
Building
An IRQ vector used by a completion queue cannot be deasserted without
first checking if the same vector does not need to stay asserted for
some other completion queue.
Signed-off-by: Jakub Jermar
---
hw/nvme/ctrl.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
On Thu, Jun 10, 2021 at 02:57:21PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> > > for (modlist = modinfo->list; modlist != NULL; modlist =
> > > modlist->next) {
> > > +if (modlist->value->has_arch) {
> > > +if (strcmp(modlist->value->name, module_name) == 0) {
> > > +
On Thu, Jun 10, 2021 at 01:20:13AM +0300, Nir Soffer wrote:
> > + else if (strcmp (metacontext, "qemu:joint-allocation") == 0) {
> > +/* Combo of base:allocation and stripped-down qemu:allocation-depth */
> > +const char *base, *depth;
> > +switch (type & 3) {
> > +case 0: base =
Hi Paolo,
> +if config_host.has_key('CONFIG_MODULES')
> + qemu_modinfo = executable('qemu-modinfo', files('qemu-modinfo.c') + genh,
> + dependencies: [glib, qemuutil], install:
> have_tools)
> + custom_target('modinfo.json',
> + input: [
This patch implements the PCIe Data Object Exchange (DOE) for PCIe 4.0/5.0
and later and CXL 2.0 "type-3" memory devices supporting the following
protocols:
1: PCIe DOE Discovery protocol
2: CXL DOE Compliance Mode protocol
3: CXL DOE CDAT protocol
Implementation is based on QEMU version
Hi Richard,
There is a function called breakpoint_invalidate() in cpu.c that calls a
function called tb_flush(). I have determined that this call is being made over
200,000 times when Windows XP boots. Disabling this function makes Windows XP
boot way faster than before. The time went down
Hi,
> > for (modlist = modinfo->list; modlist != NULL; modlist =
> > modlist->next) {
> > +if (modlist->value->has_arch) {
> > +if (strcmp(modlist->value->name, module_name) == 0) {
> > +if (!module_arch ||
> > +
On 09/06/21 14:09, Markus Armbruster wrote:
Fixes: 03d2b412aaf2078425f8472f31c8a9c2340969eb
Actually 0546c0609c ("vl: split various early command line options to a
separate function", 2020-12-10).
Done, thanks!
Paolo
On Thu, 10 Jun 2021, luigi burdo wrote:
i dont know if you know and if in the docs is described the pegasos II can
support smp dual G4 cpu.
I think theoretically the Marvell Discovery II chip can support dual CPU
and meybe even a G5, this is described in its docs. However in practice
this
Hi!
030 is known to crash sometimes
The only thing we have (as far as I know) for now is my outdated "[PATCH RFC 0/5]
Fix accidental crash in iotest 30" (6 moths ago, time flies fast :\
https://patchew.org/QEMU/20201120161622.1537-1-vsement...@virtuozzo.com/
I hope one day I'll return to
On Tue, 8 Jun 2021 at 23:10, Richard Henderson
wrote:
>
> On 6/7/21 9:57 AM, Peter Maydell wrote:
> > Implement the MVE VCLZ insn (and the necessary machinery
> > for MVE 1-input vector ops).
> >
> > Note that for non-load instructions predication is always performed
> > at a byte level
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