On 28.08.21 00:03, Fabrice Fontaine wrote:
Include linux/fs.h to avoid the following build failure on uclibc or
musl raised since version 6.0.0:
../block/export/fuse.c: In function 'fuse_lseek':
../block/export/fuse.c:641:19: error: 'SEEK_HOLE' undeclared (first use in this
function)
641 |
Connect up the armv7m clocks on the mps2-an385/386/500/511.
Connect up the armv7m object's clocks on the MPS boards defined in
mps2.c. The documentation for these FPGA images doesn't specify what
systick reference clock is used (if any), so for the moment we
provide a 1MHz refclock, which will re
There's no particular reason why the NVIC should be owning the
SysTick device objects; move them into the ARMv7M container object
instead, as part of consolidating the "create the devices which are
built into an M-profile CPU and map them into their architected
locations in the address space" work
Create input clocks on the armv7m container object which pass through
to the systick timers, so that users of the armv7m object can specify
the clocks being used.
Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Message-id: 20210812093356.1946-7-peter.mayd...@l
It is quite common for a clock tree to involve possibly programmable
clock multipliers or dividers, where the frequency of a clock is for
instance divided by 8 to produce a slower clock to feed to a
particular device.
Currently we provide no convenient mechanism for modelling this. You
can implem
Currently we implement the RAS register block within the NVIC device.
It isn't really very tightly coupled with the NVIC proper, so instead
move it out into a sysbus device of its own and have the top level
ARMv7M container create it and map it into memory at the right
address.
Signed-off-by: Pete
The v7M systick timer can be programmed to run from either of
two clocks:
* an "external reference clock" (when SYST_CSR.CLKSOURCE == 0)
* the main CPU clock (when SYST_CSR.CLKSOURCE == 1)
Our implementation currently hardwires the external reference clock
to be 1MHz, and allows boards to set th
Implement the MVE fp vector comparisons VCMP and VPT.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 18 +++
target/arm/mve.decode | 39 +++
target/arm/mve_helper.c| 64 ++
tar
From: Shuuichirou Ishii
Add tests that the A64FX CPU model exposes the expected features.
Signed-off-by: Shuuichirou Ishii
Reviewed-by: Andrew Jones
[PMM: added commit message body]
Signed-off-by: Peter Maydell
---
tests/qtest/arm-cpu-features.c | 13 +
1 file changed, 13 inserti
From: Shuuichirou Ishii
Add a definition for the Fujitsu A64FX processor.
The A64FX processor does not implement the AArch32 Execution state,
so there are no associated AArch32 Identification registers.
For SVE, the A64FX processor supports only 128,256 and 512bit vector
lengths.
The Identific
From: Shuuichirou Ishii
Add -cpu a64fx to use A64FX processor when -machine virt option is
specified. In addition, add a64fx to the Supported guest CPU types
in the virt.rst document.
Signed-off-by: Shuuichirou Ishii
Reviewed-by: Andrew Jones
Signed-off-by: Peter Maydell
---
docs/system/arm
We now have a complete MVE emulation, so we can enable it in our
Cortex-M55 model by setting the ID registers to match those of a
Cortex-M55 with full MVE support.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu_tcg.c | 7 ++-
1 file changed, 2 insertions(+),
Implement the MVE VCVT insns which convert between floating and fixed
point. As with the Neon equivalents, these use essentially the same
constant encoding as right-shift-by-immediate.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 9 +
ta
Implement the MVE "VCVT (between floating-point and integer)" insn.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/mve.decode | 7 +++
target/arm/translate-mve.c | 32
2 files changed, 39 insertions(+)
diff --git a/target/a
Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These
calculate the maximum or minimum of floating point elements across a
vector, starting with a value in a general purpose register and
returning the result there.
The pseudocode silences a possible SNaN in the accumulating result
o
Instead of passing the MSF2 SoC an integer property specifying the
CPU clock rate, pass it a Clock instead. This lets us wire that
clock up to the armv7m object.
Signed-off-by: Peter Maydell
Reviewed-by: Alexandre Iooss
Message-id: 20210812093356.1946-20-peter.mayd...@linaro.org
---
include/hw
Implement the MVE VCVT instruction which converts between single
and half precision floating point.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 5 +++
target/arm/mve.decode | 8
target/arm/mve_helper.c| 81
Implement the MVE VRINT insns, which round floating point inputs
to integer values, leaving them in floating point format.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 6 +
target/arm/mve.decode | 7 ++
target/arm/mve_helper.c|
Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but
the destination register must be the same as one of the source
registers.
We defer the decode of the size in bit 28 to the individual insn
patterns rather than doing it in the format, because otherwise we
would have a single ins
Implement the MVE fp-with-scalar VFMA and VFMAS insns.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 6 ++
target/arm/mve.decode | 14 +++---
target/arm/mve_helper.c| 37 +
target/arm/transl
Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather
Implement the MVE VCVT which converts from floating-point to integer
using a rounding mode specified by the instruction. We implement
this similarly to the Neon equivalents, by passing the required
rounding mode as an extra integer parameter to the helper functions.
Signed-off-by: Peter Maydell
Implement the MVE VCMUL and VCMLA insns.
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 18
target/arm/mve.decode | 35
target/arm/mve_helper.c| 86 ++
target/arm/translate-mve.c
In commit a777d6033447a we added an assertion to parts_silence_nan() that
prohibits calling float*_silence_nan() when in default-NaN mode.
This ties together a property of the output ("do we generate a default
NaN when the result is a NaN?") with an operation on an input ("silence
this input NaN").
Instead of having the NVIC device provide a single sysbus memory
region covering the whole of the "System PPB" space, which implements
the default behaviour for unimplemented ranges and provides the NS
alias window to the sysregs as well as the main sysreg MR, move this
handling to the container ar
Implement the MVE VFMA and VFMS insns.
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 6 ++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c| 37 +
target/arm/translate-mve.c | 2 ++
4 files
Implement the MVE scalar floating point insns VADD, VSUB and VMUL.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 9 +
target/arm/mve.decode | 27 +--
target/arm/mve_helper.c| 35
Add the usual-style QEMU interface comment documenting what
properties, etc, this device exposes.
Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Message-id: 20210812093356.1946-5-peter.mayd...@linaro.org
---
include/hw/timer/armv7m_systick.h | 7 +++
1 f
Implement more simple 2-operand floating point MVE insns.
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 15 +++
target/arm/mve.decode | 6 ++
target/arm/mve_helper.c| 16
target/arm/translate-mve.c | 5 ++
From: Philippe Mathieu-Daudé
Quoting Peter Maydell:
These MEMTX_* aren't from the memory transaction API functions;
they're just being used by gicd_readl() and friends as a way to
indicate a success/failure so that the actual MemoryRegionOps
read/write fns like gicv3_dist_read() can log
From: Philippe Mathieu-Daudé
QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q'
suffix for 64-bit accesses. Rename the current 'll' suffix to
have the GIC dist accessors better match the rest of the codebase.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20210826180704.2131949-2
Implement the MVE VADD (floating-point) insn. Handling of this is
similar to the 2-operand integer insns, except that we must take care
to only update the floating point exception status if the least
significant bit of the predicate mask for each element is active.
Reviewed-by: Richard Henderson
Implement the MVE fp scalar comparisons VCMP and VPT.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 18 +++
target/arm/mve.decode | 61 +
target/arm/mve_helper.c| 62 +
From: Philippe Mathieu-Daudé
Commit 155e1c82ed0 deprecated the raspi2/raspi3 machine names.
Use the recommended new names: raspi2b and raspi3b.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Willian Rampazzo
Message-id: 20210827060815.2384760-2-f4...@amsat.org
Sig
Implement the MVE VCADD insn. Note that here the size bit is the
opposite sense to the other 2-operand fp insns.
We don't check for the sz == 1 && Qd == Qm UNPREDICTABLE case,
because that would mean we can't use the DO_2OP_FP macro in
translate-mve.c.
Reviewed-by: Richard Henderson
Signed-off-
From: Yanan Wang
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
Reviewed-by: Cornelia Huck
Reviewed-by: Pankaj Gupta
Signed-off-by: Peter Maydell
---
include/hw/boards.h| 3 +++
include/hw/i386/pc.h
From: Philippe Mathieu-Daudé
Remove the raspi2/raspi3 machine aliases,
deprecated since commit 155e1c82ed0.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20210827060815.2384760-3-f4...@amsat.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/about/deprecated.rst |
The following changes since commit ec397e90d21269037280633b6058d1f280e27667:
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging (2021-09-01
08:33:02 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pma
Hi,
On 9/1/21 8:53 AM, Li, Chunming wrote:
>
>> -Original Message-
>> From: Eric Auger [mailto:eric.au...@redhat.com]
>> Sent: Tuesday, August 31, 2021 10:37 PM
>> To: chunming; peter.mayd...@linaro.org
>> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
>> Renwei; Li, C
06.08.2021 12:38, Max Reitz wrote:
Callers should be able to specify whether they want job_cancel_sync() to
force-cancel the job or not.
In fact, almost all invocations do not care about consistency of the
result and just want the job to terminate as soon as possible, so they
should pass force=t
On Wed, 1 Sep 2021 11:41:47 +0200
Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
> ---
Reviewed-by: Greg Kurz
> hw/ppc/spapr_cpu_core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 4f316a6f9d31..58e7341cb784 10
On Wed, 1 Sep 2021 11:41:46 +0200
Cédric Le Goater wrote:
> This also fixes a small skiboot/skiroot typo and removes the links to
> the specific POWER8 and POWER9 images since the firmware images can be
> used to run all machines.
>
> Signed-off-by: Cédric Le Goater
> ---
> docs/system/ppc/pow
06.08.2021 12:38, Max Reitz wrote:
Finalizing the job may cause its AioContext to change. This is noted by
job_exit(), which points at job_txn_apply() to take this fact into
account.
However, job_completed() does not necessarily invoke job_txn_apply()
(through job_completed_txn_success()), but
06.08.2021 12:38, Max Reitz wrote:
When a transaction is aborted, no result matters, and so all jobs within
should be force-cancelled.
Signed-off-by: Max Reitz
---
job.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/job.c b/job.c
index 3fe23bb77e..24e7c4fcb7 10064
On Wed, 1 Sep 2021 10:45:43 +0100
Peter Maydell wrote:
> On Wed, 1 Sept 2021 at 10:02, Igor Mammedov wrote:
> >
> > On Wed, 1 Sep 2021 09:06:41 +0100
> > Peter Maydell wrote:
> >
> > > On Wed, 1 Sept 2021 at 09:03, Igor Mammedov wrote:
> > > >
> > > > not directly related to the patch but
1-08-31 14:38:15 +0100)
>
> are available in the Git repository at:
>
> g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210901-2
>
> for you to fetch changes up to 8e034ae44dba6291beb07f7f2a932c1e5ab83e98:
>
> target/riscv
On Wed, 1 Sept 2021 at 09:29, Michael Tokarev wrote:
>
> On 31.08.2021 22:47, Peter Maydell wrote:
> > On Tue, 31 Aug 2021 at 19:34, Michael Tokarev wrote:
> ..
> >> -assert(salen >= sizeof(su->sun_family) + 1 &&
> >> - salen <= sizeof(struct sockaddr_un));
> >> +/* there's a co
On Wed, 1 Sept 2021 at 10:02, Igor Mammedov wrote:
>
> On Wed, 1 Sep 2021 09:06:41 +0100
> Peter Maydell wrote:
>
> > On Wed, 1 Sept 2021 at 09:03, Igor Mammedov wrote:
> > >
> > > not directly related to the patch but while I was testing IORT testcase
> > > (https://github.com/imammedo/qemu acp
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 5 +
hw/intc/xive.c| 5 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 29b130eaea59..252c58a1d691 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/p
This also fixes a small skiboot/skiroot typo and removes the links to
the specific POWER8 and POWER9 images since the firmware images can be
used to run all machines.
Signed-off-by: Cédric Le Goater
---
docs/system/ppc/powernv.rst | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --g
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 11 +++
hw/intc/xive.c| 21 ++---
2 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index db7641165484..29b130eaea59 100644
--- a/include/hw/ppc
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a62e90b15e27..761b82be7401 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -723,6 +723,8 @@ static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv,
int chi
This to avoid possible conflicts with the "id" property of QOM objects.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv_core.h | 2 +-
hw/ppc/pnv.c | 4 ++--
hw/ppc/pnv_core.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/ppc/pnv_
Hello,
This is a small series taking into account the comments made by David
and Greg while reviewing the pnv/p10 series.
It also adds a POWER10 DD2 CPU to the pseries machine.
Thanks,
C.
Cédric Le Goater (8):
docs/system: ppc: Update the URL for OpenPOWER firmware images
ppc/spapr: Add a
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2f5358b70c95..a62e90b15e27 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -838,8 +838,7 @@ static void pnv_init(MachineState *machine)
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr_cpu_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 4f316a6f9d31..58e7341cb784 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -382,6 +382,7 @@ static const Ty
On P10, the chip id is calculated from the "Primary topology table
index". See skiboot commits for more information [1].
This information is extracted from the hdata on real systems which
QEMU needs to emulate. Add this property for all machines even if it
is only used on POWER10.
[1] https://git
On Wed, 7 Jul 2021 at 00:51, Richard Henderson
wrote:
>
> Supercedes: <20210619034329.532318-1-richard.hender...@linaro.org>
> ("[PATCH 00/12] linux-user: Load a vdso for x86_64 and hppa")
>
> Supercedes: <20210618192951.125651-1-richard.hender...@linaro.org>
> ("[PATCH v2 00/23] linux-user: Move
On 2021/9/1 16:02, Peter Maydell wrote:
On Tue, 31 Aug 2021 at 02:54, Yanan Wang wrote:
This patch adds 6.2 machine types for arm/i440fx/q35/s390x/spapr,
which is originally from [1]. Here resend it separately and hopefully
it can get into upstream first, so that some other patches currently
On 01.09.2021 12:12, Daniel P. Berrangé wrote:
Seems right to me, however there are some notes in libc bits/socket.h
/* Structure large enough to hold any socket address (with the historical
exception of AF_UNIX). */
And also this
https://idea.popcount.org/2019-12-06-addressing/#fn:sockaddr
On Tue, Aug 31, 2021 at 11:21:43PM +0400, Marc-André Lureau wrote:
> Hi
>
> On Tue, Aug 31, 2021 at 10:26 PM Michael Tokarev wrote:
>
> > We test whenever the path of unix-domain socket
> > address is non-empty and strictly-less than
> > the length of the path buffer. Both these
> > conditions a
On Tue, 31 Aug 2021, Programmingkid wrote:
I just realized, I sent a patch to the developer list that fixes the
missing qemu_vga.ndrv problem, but I do not know which maintainer to
send it to. Who maintains the configure script? A search of the
maintainers page was not clear as to who this is.
27.08.2021 21:45, Eric Blake wrote:
On Fri, Aug 27, 2021 at 07:58:10PM +0300, Vladimir Sementsov-Ogievskiy wrote:
27.08.2021 18:09, Eric Blake wrote:
According to the NBD spec, a server advertising
NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will
not see any cache inconsis
On Wed, 1 Sep 2021 09:06:41 +0100
Peter Maydell wrote:
> On Wed, 1 Sept 2021 at 09:03, Igor Mammedov wrote:
> >
> > not directly related to the patch but while I was testing IORT testcase
> > (https://github.com/imammedo/qemu acpi-tests)
> > after rebase to 6.1, I get test failure due to change
On Tue, Aug 31, 2021 at 04:29:09PM -0400, Peter Xu wrote:
> On Tue, Aug 31, 2021 at 02:16:42PM +0100, Daniel P. Berrangé wrote:
> > On Tue, Aug 31, 2021 at 08:02:39AM -0300, Leonardo Bras wrote:
> > > Call qio_channel_set_zerocopy(true) in the start of every multifd thread.
> > >
> > > Change the
On Tue, Aug 31, 2021 at 04:27:04PM -0400, Peter Xu wrote:
> On Tue, Aug 31, 2021 at 01:57:33PM +0100, Daniel P. Berrangé wrote:
> > On Tue, Aug 31, 2021 at 08:02:38AM -0300, Leonardo Bras wrote:
> > > MSG_ZEROCOPY is a feature that enables copy avoidance in TCP/UDP socket
> > > send calls. It does
On Wed, Sep 01, 2021 at 11:27:24AM +0800, Bin Meng wrote:
> Read or write to uart registers when unclocked or in reset should be
> ignored. Add the check there, and as a result of this, the check in
> uart_write_tx_fifo() is now unnecessary.
Hi Bin,
I thought I had replied to this but it must hav
27.08.2021 18:09, Eric Blake wrote:
According to the NBD spec, a server advertising
NBD_FLAG_CAN_MULTI_CONN promises that multiple client connections will
not see any cache inconsistencies: when properly separated by a single
flush, actions performed by one client will be visible to another
clien
On 31.08.2021 22:47, Peter Maydell wrote:
On Tue, 31 Aug 2021 at 19:34, Michael Tokarev wrote:
..
-assert(salen >= sizeof(su->sun_family) + 1 &&
- salen <= sizeof(struct sockaddr_un));
+/* there's a corner case when trailing \0 does not fit into
+ * sockaddr_un. Compare l
On Tue, 31 Aug 2021 at 09:29, Shuuichirou Ishii
wrote:
>
> This is the v6 patch series.
>
> v6:
> For patch 1[1/3], added the commit messages that the Identification registers
> value are defined based on FX700, and has been tested and confirmed.
Applied to target-arm.next. Thanks!
-- PMM
On 01/09/2021 08:58, Peter Maydell wrote:
On Sat, 24 Jul 2021 at 14:49, Peter Maydell wrote:
The sparc frontend is now the only user of the obsolete gen_io_end()
function (used for icount support). This patchset removes the
use from sparc as well, and then tidies up the generic icount
infrast
On Tue, 31 Aug 2021 14:15:31 +0200
Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> include/exec/exec-all.h | 1 -
> include/tcg/tcg-module.h | 1 +
> accel/stubs/tcg-stub.c| 4
> accel/tcg/tcg-module.c| 1 +
> accel/tcg/translate-all.c | 9 -
> cpu.c
On Tue, Aug 31, 2021 at 02:15:36PM +0200, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> include/exec/exec-all.h | 2 +-
> include/tcg/tcg-module.h| 1 +
> accel/tcg/cpu-exec-common.c | 2 +-
> accel/tcg/tcg-module.c | 6 ++
> accel/tc
On 31/08/2021 03.54, Yanan Wang wrote:
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
Reviewed-by: Cornelia Huck
Reviewed-by: Pankaj Gupta
---
[..]
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-vir
On Wed, 1 Sept 2021 at 09:03, Igor Mammedov wrote:
>
> not directly related to the patch but while I was testing IORT testcase
> (https://github.com/imammedo/qemu acpi-tests)
> after rebase to 6.1, I get test failure due to change in MADT table vs
> expected blobs made in 6.0 time and it does look
On 01/09/2021 08:57, Mark Cave-Ayland wrote:
I had a quick look at your via-timer branch at
https://github.com/fthain/qemu/commits/via-timer and spotted that your work is based
upon the v6.0 release. Before digging further into this, can you try using vanilla
git master or the v6.1 tag instead
not directly related to the patch but while I was testing IORT testcase
(https://github.com/imammedo/qemu acpi-tests)
after rebase to 6.1, I get test failure due to change in MADT table vs
expected blobs made in 6.0 time and it does look like ABI change
(what is bad, it also happens to virt-6.0 mac
On Tue, 31 Aug 2021 at 02:54, Yanan Wang wrote:
>
> This patch adds 6.2 machine types for arm/i440fx/q35/s390x/spapr,
> which is originally from [1]. Here resend it separately and hopefully
> it can get into upstream first, so that some other patches currently
> on the mail list which depend on 6.
On Sat, 24 Jul 2021 at 14:49, Peter Maydell wrote:
>
> The sparc frontend is now the only user of the obsolete gen_io_end()
> function (used for icount support). This patchset removes the
> use from sparc as well, and then tidies up the generic icount
> infrastructure to remove the function altoge
On 31/08/2021 23:44, Finn Thain wrote:
You mentioned that the OS may compensate for the fact that the 6522
doesn't have an overflow flag: can you explain more as to how this works
in Linux? Is the problem here that even if you read the counter value in
the interrupt handler to work out the laten
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