On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 twt = tcg_const_i32(a->wt);
tcg_constant_i32. Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
+ void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 2 ++
target/mips/tcg/msa_translate.c | 40 +++--
2 files changed, 30
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
tcg_constant_i32. Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+#define TRANS_DF_E(NAME, trans_func, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
I think this would be better as a table.
#define
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1921664
Title:
Coroutines
[Expired for qemu (Ubuntu) because there has been no activity for 60
days.]
** Changed in: qemu (Ubuntu)
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1921664
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 timm = tcg_const_i32(a->sa);
tcg_constant_i32. Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);
+timm = tcg_const_i32(a->sa);
tcg_constant_i32. Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
@u5 .. ... df:2 sa:5 ws:5 wd:5 .. _ldst
@s5 .. ... df:2 sa:s5 ws:5 wd:5 .. _ldst
@ldi.. ... df:2 sa:s10 wd:5 .. _ldst ws=0
+@bit.. ... df:7
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Extract the common code which parses data formats to an helper.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 68 +++--
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
+TCGv_i32, TCGv_i32))
{
+TCGv_i32 tdf =
Hi Eric,
On 2021/10/23 22:26, Eric Auger wrote:
Hi Kunkun,
On 10/22/21 12:01 PM, Kunkun Jiang wrote:
Hi Eric,
On 2021/10/22 0:15, Eric Auger wrote:
Hi Kunkun,
On 9/14/21 3:53 AM, Kunkun Jiang wrote:
We expand MemoryRegions of vfio-pci sub-page MMIO BARs to
vfio_pci_write_config to improve
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Similar to the TRANS() macro introduced in commit fb3164e412d,
introduce TRANS_CHECK() which takes a boolean expression as
argument.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 9 +
1 file changed, 9
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
+{
+TCGv_i32 tdf;
+TCGv_i32 twd;
+TCGv_i32 timm;
+
+if (!check_msa_access(ctx)) {
+return false;
+}
Return true. I won't mention the return after
On 10/23/21 4:14 PM, Michael S. Tsirkin wrote:
On Sat, Oct 23, 2021 at 07:52:21AM +0530, Ani Sinha wrote:
On Fri, 22 Oct 2021, Eric DeVolder wrote:
Ani, inline below.
eric
On 10/22/21 05:18, Ani Sinha wrote:
On Fri, 15 Oct 2021, Eric DeVolder wrote:
diff --git
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.
Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 20 +---
1 file changed, 13 insertions(+), 7
Signed-off-by: BALATON Zoltan
---
hw/char/sh_serial.c | 23 ++-
hw/intc/sh_intc.c| 25 -
hw/pci-host/sh_pci.c | 10 --
hw/sh4/r2d.c | 39 ---
hw/sh4/sh7750.c | 26
Signed-off-by: BALATON Zoltan
---
hw/char/sh_serial.c | 48 +++
hw/intc/sh_intc.c| 83 ++--
hw/sh4/r2d.c | 15 +---
hw/sh4/sh7750.c | 24
hw/sh4/sh7750_regnames.c | 3 +-
Signed-off-by: BALATON Zoltan
---
hw/timer/sh_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
index 68c109ecfd..02eb865908 100644
--- a/hw/timer/sh_timer.c
+++ b/hw/timer/sh_timer.c
@@ -233,7 +233,7 @@ static void
Signed-off-by: BALATON Zoltan
---
hw/char/sh_serial.c | 6 +-
hw/intc/sh_intc.c| 9 +-
hw/sh4/r2d.c | 6 +-
hw/sh4/sh7750.c | 22 +-
hw/sh4/sh7750_regs.h | 504 +--
hw/sh4/shix.c| 10 +-
hw/timer/sh_timer.c | 7 +-
7
This fixes coding style of files belonging to SH4 system emulation
which were not following current QEMU coding style requirements.
BALATON Zoltan (5):
hw/sh4: Coding style: Remove tabs
hw/sh4: Coding style: Fix multi-line comments
hw/sh4: Coding style: White space fixes
hw/sh4: Coding
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
We do not want a shell command substitution, but a parameter
substitution (with assignment). Replace $() -> ${}, otherwise
the expanded command return an empty string and the $cross_cc
variable is not set.
Fixes: 634ef789f8e ("tests/tcg: add
)
Trivial patches pull request 20211023
Greg Kurz (2):
softmmu/physmem.c: Fix typo in comment
README: Fix some documentation URLs
Laurent Vivier (2):
analyze-migration.py: fix a long standing typo
analyze-migration.py: fix
Only the MSA generic opcode was overlapping with the other
instructions. Since the previous commit removed it, we can
now remove the overlap group. The decodetree script forces
us to re-indent the opcodes.
Diff trivial to review using `git-diff --ignore-all-space`.
Signed-off-by: Philippe
Convert 3-register operations to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 53 ++
target/mips/tcg/msa_translate.c | 916 ++--
2 files changed, 106 insertions(+), 863 deletions(-)
diff --git a/target/mips/tcg/msa.decode
While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.
Signed-off-by: Philippe Mathieu-Daudé
---
Convert the MOVE.V opcode (Vector Move) to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 6 +-
target/mips/tcg/msa_translate.c | 26 +-
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git
Convert 3-register floating-point or fixed-point operations
to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 37 ++
target/mips/tcg/msa_translate.c | 213 ++--
2 files changed, 74 insertions(+), 176 deletions(-)
diff
Convert the CFCMSA (Copy From Control MSA register) and
CTCMSA (Copy To Control MSA register) opcodes to decodetree.
Since they respectively overlap with the SLDI and SPLATI
opcodes, use decodetree overlap groups.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 10
Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 2 +
target/mips/tcg/msa_translate.c | 92 -
2 files changed, 12
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 2 ++
target/mips/tcg/msa_translate.c | 40 +++--
2 files changed, 30 insertions(+), 12 deletions(-)
diff --git
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 3 +++
target/mips/tcg/msa_translate.c | 37 +++--
2 files changed, 6 insertions(+), 34
Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
decodetree.
Since the 'n' field is a constant value, use tcg_constant_i32()
instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 1 +
target/mips/tcg/msa_translate.c | 90
Convert load/store instructions to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 4 ++
target/mips/tcg/msa_translate.c | 99 +
2 files changed, 44 insertions(+), 59 deletions(-)
diff --git a/target/mips/tcg/msa.decode
Convert instructions with an immediate element index
and data format df/n to decodetree.
Since the 'data format' and 'n' fields are constant values,
use tcg_constant_i32() instead of a TCG temporaries.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 6 +
Convert 3-register floating-point or fixed-point operations
to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 8
target/mips/tcg/msa_translate.c | 70 +++--
2 files changed, 39 insertions(+), 39 deletions(-)
diff --git
Convert instructions with an 8-bit immediate value and either
implicit data format or data format df to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 8
target/mips/tcg/msa_translate.c | 72 +
2 files changed, 26
Convert 2-register operations to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 3 ++
target/mips/tcg/msa_translate.c | 91 +
2 files changed, 28 insertions(+), 66 deletions(-)
diff --git a/target/mips/tcg/msa.decode
Convert 2-register floating-point operations to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 19 ++
target/mips/tcg/msa_translate.c | 109
2 files changed, 46 insertions(+), 82 deletions(-)
diff --git
All opcodes have been converted to decodetree. The generic
MSA handler is now pointless, remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 2 --
target/mips/tcg/msa_translate.c | 7 ---
2 files changed, 9 deletions(-)
diff --git
Convert instructions with a 5-bit immediate value to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 15 +
target/mips/tcg/msa_translate.c | 99
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 3 +++
target/mips/tcg/msa_translate.c | 47
This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.
Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).
Signed-off-by: Philippe Mathieu-Daudé
---
Convert 3-register operations to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 6 ++
target/mips/tcg/msa_translate.c | 35
Similar to the TRANS() macro introduced in commit fb3164e412d,
introduce TRANS_CHECK() which takes a boolean expression as
argument.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/mips/tcg/translate.h
Convert 3-register operations to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 11 ++
target/mips/tcg/msa_translate.c | 213 +---
2 files changed, 66 insertions(+), 158 deletions(-)
diff --git a/target/mips/tcg/msa.decode
Convert instructions with an immediate bit index and
data format df/m to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 15 +
Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c
Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c
Extract the common code which parses data formats to an helper.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 68 +++--
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c
The result of the 'Vector Multiply and Add' opcode is incorrect
with Byte vectors. Probably due to a copy/paste error, commit
7a7a162adde mistakenly used the $wt (target register) instead
of $wd (destination register) as first operand. Fix that.
Cc: Aleksandar Rikalo
Fixes: 7a7a162adde
The result of the 'Vector Multiply and Subtract' opcode is
incorrect with Byte vectors. Probably due to a copy/paste error,
commit 5f148a02327 mistakenly used the $wt (target register)
instead of $wd (destination register) as first operand. Fix that.
Cc: Aleksandar Rikalo
Fixes: 5f148a02327
Convert 3-register instructions with implicit data formats
to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 8
target/mips/tcg/msa_translate.c | 82 +++--
2 files changed, 24 insertions(+), 66 deletions(-)
diff --git
Convert the LDI opcode (Immediate Load) to decodetree. Since it
overlaps with the generic MSA handler, use a decodetree overlap
group.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé
---
The following commits added various user-mode tests
for various MSA instructions:
- 0fdd986a6c8 ("Add tests for MSA integer add instructions")
- 1be82d89011 ("Add tests for MSA integer average instructions")
- 1d336c87a3c ("Add tests for MSA bit set instructions")
- 1e6bea794c8 ("Add tests
We do not want a shell command substitution, but a parameter
substitution (with assignment). Replace $() -> ${}, otherwise
the expanded command return an empty string and the $cross_cc
variable is not set.
Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh")
Signed-off-by:
Hi,
This series converts 2000+ lines of switch() code to decodetree
description, so this hard-to-review/modify switch is auto generated
by the decodetree script. This is a big win for maintenance (and
indeed the convertion revealed 2 bugs).
Massive convertions are - beside being often boring -
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
+static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
+{
+static const uint32_t valid_values = 0b00010010;
All of the specified values are non-zero, so this kinda duplicates the values table.
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 4 +++
target/ppc/insn64.decode| 19 ++
target/ppc/int_helper.c | 15
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Bruno Larsen (billionai)"
Implemented the instruction XXSPLTIDP using decodetree.
Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
target/ppc/insn64.decode| 2 ++
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Bruno Larsen (billionai)"
Implemented the XXSPLTIW instruction, using decodetree.
Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
target/ppc/insn64.decode| 6 ++
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Bruno Larsen (billionai)"
Implemented XXSPLTI32DX emulation using decodetree
Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
target/ppc/insn64.decode| 11
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Bruno Larsen (billionai)"
Changed the function that handles XXSPLTIB emulation to using
decodetree, but still use the same logic as before
Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Bruno Larsen (billionai)"
Changed the function that handles XXSPLTW emulation to using decodetree,
but still using the same logic.
Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Lucas Mateus Castro (alqotel)"
Implemented the instructions plxvp and pstxvp using decodetree
Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
target/ppc/insn64.decode| 9 +
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Lucas Mateus Castro (alqotel)"
Implemented the instructions plxv and pstxv using decodetree
Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
target/ppc/insn64.decode| 10 ++
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Lucas Mateus Castro (alqotel)"
Implemented the instructions lxvpx and stxvpx using decodetree
Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 3 +++
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
if (ctx->le_mode) {
-gen_addr_add(ctx, ea, ea, 8);
+gen_addr_add(ctx, ea, ea, paired ? 24 : 8);
Still questioning the address of the fault, but the rest of it looks ok.
r~
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
+if (ctx->le_mode) {
+gen_addr_add(ctx, ea, ea, 8);
+offset = -8;
+} else {
+offset = 8;
+}
+
+if (store) {
+get_cpu_vsrh(xt, rt);
+tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+
On 10/23/21 1:34 PM, Richard Henderson wrote:
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
+static bool do_lstxv(DisasContext *ctx, int ra, int displ,
+ int rt, bool store)
You need an int64_t displ before you add PLXV et al. What happened to passing in
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
@@ -2075,7 +1969,7 @@ static void gen_xvxsigdp(DisasContext *ctx)
tcg_temp_free_i64(xbl);
}
-static bool do_lstxv(DisasContext *ctx, int ra, int displ,
+static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
+static bool do_lstxv(DisasContext *ctx, int ra, int displ,
+ int rt, bool store)
You need an int64_t displ before you add PLXV et al. What happened to passing in arg_D as
for the other integer instructions?
+
On Fri, Oct 22, 2021 at 03:58:28PM +0100, Jean-Philippe Brucker wrote:
> On Fri, Oct 22, 2021 at 10:46:08AM -0400, Michael S. Tsirkin wrote:
> > On Wed, Oct 13, 2021 at 05:06:08PM +0100, Jean-Philippe Brucker wrote:
> > > Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine
> > >
On Sat, Oct 23, 2021 at 07:52:21AM +0530, Ani Sinha wrote:
>
>
> On Fri, 22 Oct 2021, Eric DeVolder wrote:
>
> > Ani, inline below.
> > eric
> >
> > On 10/22/21 05:18, Ani Sinha wrote:
> > >
> > >
> > > On Fri, 15 Oct 2021, Eric DeVolder wrote:
> > >
> > > > This change exposes ACPI ERST
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: "Bruno Larsen (billionai)"
Introduce the macro to centralize checking if the VSX facility is
enabled and handle it correctly.
Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Luis Pires
Signed-off-by: Matheus Ferst
---
On 10/23/21 1:02 PM, BALATON Zoltan wrote:
So may question was not if it's possible but if having target_ulong different from what we
had in qemu-system-ppc could cause any problems? I have no experience running 32-bit
guests with qemu-system-ppc64 but previously when this came up one
On Sat, 23 Oct 2021, Richard Henderson wrote:
On 10/23/21 3:12 AM, BALATON Zoltan wrote:
You mentioning target_ulong reminded me a question I had. Currently we have
qemu-system-ppc and qemu-system-ppc64 but the latter includes all machines
of the former too so you could run for example
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vextdubvlx: Vector Extract Double Unsigned Byte to VSR using
GPR-specified Left-Index
vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using
When converting a siginfo_t from waitid(), the interpretation of si_status
depends on the value of si_code: For CLD_EXITED, it is an exit code and
should be copied verbatim. For other codes, it is a signal number
(possibly with additional high bits from ptrace) that should be mapped.
This code
From: Tong Ho
Signed-off-by: Tong Ho
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211015203532.2463705-3-tong...@xilinx.com>
Signed-off-by: Laurent Vivier
---
hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +++-
1
From: Tong Ho
Signed-off-by: Tong Ho
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211015203532.2463705-4-tong...@xilinx.com>
Signed-off-by: Laurent Vivier
---
hw/nvram/xlnx-zynqmp-efuse.c | 18 --
1 file
On 10/23/21 3:12 AM, BALATON Zoltan wrote:
You mentioning target_ulong reminded me a question I had. Currently we have
qemu-system-ppc and qemu-system-ppc64 but the latter includes all machines of the former
too so you could run for example sam460ex with qemu-system-ppc64 (except mac99 which
From: Tong Ho
Signed-off-by: Tong Ho
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211015203532.2463705-2-tong...@xilinx.com>
Signed-off-by: Laurent Vivier
---
hw/nvram/xlnx-efuse.c | 9 ++---
1 file changed, 6
From: Laurent Vivier
When we try to use 'analyze-migration.py -x' with python3,
we have the following errors:
Traceback (most recent call last):
File "scripts/analyze-migration.py", line 593, in
f.write(jsonenc.encode(dump.vmsd_desc))
TypeError: a bytes-like object is required,
From: Laurent Vivier
The parameters of '-d' can be either 'state' or 'desc', not 'dump'
as it is reported in the error message.
Fixes: b17425701d66 ("Add migration stream analyzation script")
Signed-off-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Philippe Mathieu-Daudé
In order to help Eduardo and Marcel with the machine
core API, add myself as reviewer. That will also help
me to learn more about this subsystem :)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed by: Marcel Apfelbaum
Message-Id:
From: Philippe Mathieu-Daudé
We are going to modify this function, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Reviewed-by: Thomas Huth
Message-Id: <20210807110939.95853-2-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
disas/nios2.c | 55
From: Philippe Mathieu-Daudé
Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization")
the disassemble_info->bfd_endian enum is set for all targets in
target_disas(). We can directly call print_insn_nios2() and simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent
From: Greg Kurz
Fix the comment to match what the code is doing, as explained in
the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09
that introduced the change:
Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization
of vCPU and migration operations through
-for-6.2-pull-request
for you to fetch changes up to 2c92be50bcfa8b7529a39fc99078ef14dcfc71aa:
analyze-migration.py: fix extract contents ('-x') errors (2021-10-23 20:28:56
+0200)
Trivial patches pull request 20211023
From: Oğuz Ersen
Message-Id:
Signed-off-by: Oğuz Ersen
Reviewed-by: Laurent Vivier
[lv,pb: s/K_opyala/_Kopyala/;s/Se_kmeleri/_Sekmeleri/]
Signed-off-by: Laurent Vivier
---
po/tr.po | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/po/tr.po
From: Greg Kurz
All of these pages live in the wiki, not in the main web site.
Signed-off-by: Greg Kurz
Reviewed-by: Laurent Vivier
Tested-by: Laurent Vivier
Message-Id: <163456470882.196333.17366490695504718038.stgit@bahia.huguette>
Signed-off-by: Laurent Vivier
---
README.rst | 14
On 10/22/21 3:11 PM, Luis Fernando Fujita Pires wrote:
From: Richard Henderson
@@ -1392,18 +1408,18 @@ void tcg_optimize(TCGContext *s)
/* Proceed with possible constant folding. */
break;
}
-if (opc ==
On Sat, Oct 23, 2021 at 7:47 PM Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>
> > We do not want a shell command substitution, but a parameter
> > substitution (with assignment). Replace $() -> ${}, otherwise
> > the expanded command return an empty string and the $cross_cc
> > variable
Philippe Mathieu-Daudé writes:
> We do not want a shell command substitution, but a parameter
> substitution (with assignment). Replace $() -> ${}, otherwise
> the expanded command return an empty string and the $cross_cc
> variable is not set.
Queued to testing/next, thanks.
--
Alex Bennée
We do not want a shell command substitution, but a parameter
substitution (with assignment). Replace $() -> ${}, otherwise
the expanded command return an empty string and the $cross_cc
variable is not set.
Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh")
Signed-off-by:
On Sat, Oct 23, 2021 at 1:34 AM Kyle Evans wrote:
> On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote:
> >
> > Implement the system call dispatch. This implements all three kinds of
> > system call: direct and the two indirect variants. It handles all the
> > special cases for thumb as well.
>
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