On Wed, Oct 27, 2021 at 6:00 PM Laurent Vivier wrote:
>
> If the guest driver doesn't support the STANDBY feature, by default
> we keep the virtio-net device and don't hotplug the VFIO device,
> but in some cases, user can prefer to use the VFIO device rather
> than the virtio-net one. We can't
Paolo Bonzini writes:
> Acked-by: Paolo Bonzini
>
> Thanks for the quick fix!
Who's going to do the pull request?
From: Stefan Reiter
It is possible to specify more than one VNC server on the command line,
either with an explicit ID or the auto-generated ones à la "default",
"vnc2", "vnc3", ...
It is not possible to change the password on one of these extra VNC
displays though. Fix this by adding a
The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027'
into staging (2021-10-27 11:45:18 -0700)
are available in the Git repository at:
git://repo.or.cz/qemu/armbru.git tags/pull-monitor-2021-10
From: Stefan Reiter
'protocol' and 'connected' are better suited as enums than as strings,
make use of that. No functional change intended.
Suggested-by: Markus Armbruster
Reviewed-by: Markus Armbruster
Signed-off-by: Stefan Reiter
Message-Id: <20211021100135.4146766-3-s.rei...@proxmox.com>
From: Stefan Reiter
VNC only supports 'keep' here, enforce this via a seperate
SetPasswordActionVnc enum and mark the option 'deprecated' (as it is
useless with only one value possible).
Also add a deprecation note to docs.
Suggested-by: Eric Blake
Reviewed-by: Markus Armbruster
From: Stefan Reiter
Adds support for the "-xV" parameter type, where "-x" denotes a flag
name and the "V" suffix indicates that this flag is supposed to take an
arbitrary string parameter.
These parameters are always optional, the entry in the qdict will be
omitted if the flag is not given.
Stefan Reiter writes:
> Since the removal of the generic 'qmp_change' command, one can no longer
> replace
> the 'default' VNC display listen address at runtime (AFAIK). For our users who
> need to set up a secondary VNC access port, this means configuring a second
> VNC
> display (in addition
From: Jose Martins
There is no need to "force an hs exception" as the current privilege
level, the state of the global ie and of the delegation registers should
be enough to route the interrupt to the appropriate privilege level in
riscv_cpu_do_interrupt. The is true for both asynchronous and
From: Jose Martins
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always considered enabled when
it should. The spec states that "Interrupts for higher-privilege
From: Chih-Min Chao
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
The original logic:
Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan.
The alternative path:
Set invalid flag if ft1 == sNaN || ft2 == sNaN.
Return NaN only if ft1 == NaN && ft2 ==
From: Anatoly Parshintsev
Signed-off-by: Anatoly Parshintsev
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20211025173609.2724490-8-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c |
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-id: 20211025173609.2724490-5-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/machine.c | 27 +++
1 file changed, 27 insertions(+)
diff --git
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-id: 20211025173609.2724490-4-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 11 ++
target/riscv/cpu.c | 2 +
target/riscv/csr.c | 285
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-id: 20211025173609.2724490-3-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 96 +
1 file changed, 96 insertions(+)
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-id: 20211025173609.2724490-9-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 4
1 file changed, 4
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id: 20211025173609.2724490-2-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 2 ++
1 file changed, 2
From: Chih-Min Chao
The sNaN propagation behavior has been changed since
cd20cee7 in https://github.com/riscv/riscv-isa-manual.
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-id: 20211016085428.3001501-3-frank.ch...@sifive.com
Signed-off-by:
From: Alistair Francis
Fixup the PLIC context address to correctly support the threshold and
claim register.
Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Message-id: 20211022060133.3045020-5-alistair.fran...@opensource.wdc.com
---
hw/riscv/virt.c | 20 +---
1 file changed, 1 insertion(+), 19
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20211025173609.2724490-7-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/translate.c| 8
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Message-id: 20211022060133.3045020-3-alistair.fran...@opensource.wdc.com
---
include/hw/riscv/sifive_u.h | 1 -
hw/riscv/sifive_u.c | 14
From: Alistair Francis
Using a macro for the PLIC configuration doesn't make the code any
easier to read. Instead it makes it harder to figure out what is going
on, so let's remove it.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Message-id:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Message-id: 20211025173609.2724490-6-space.monkey.deliv...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Message-id: 20211022060133.3045020-4-alistair.fran...@opensource.wdc.com
---
include/hw/riscv/microchip_pfsoc.h | 1 -
hw/riscv/microchip_pfsoc.c |
From: Alistair Francis
Add a generic function that can create the PLIC strings.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Message-id: 20211022060133.3045020-2-alistair.fran...@opensource.wdc.com
---
include/hw/riscv/boot.h | 2 ++
From: Alistair Francis
The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027'
into staging (2021-10-27 11:45:18 -0700)
are available in the Git repository at:
g...@github.com:alistair23
Add a helper to loop over each root bus of the system, either the default root
bus or extended buses like pxb-pcie.
There're three places that can be rewritten with the pci_for_each_root_bus()
helper that we just introduced. De-dup the code.
Signed-off-by: Peter Xu
---
On Thu, Oct 28, 2021 at 1:30 AM Markus Armbruster wrote:
>
> Leonardo Bras Soares Passos writes:
>
> [...]
>
> >> The general argument for having QAPI schema 'if' mirror the C
> >> implementation's #if is introspection. Let me explain why that matters.
> >>
> >> Consider a management
Add this sister helper besides object_child_foreach_recursive() to loop over
child objects only if the object can be casted to a specific type.
Suggested-by: Michael S. Tsirkin
Signed-off-by: Peter Xu
---
include/qom/object.h | 20
qom/object.c | 27
Add a pre-plug hook for x86-iommu, so that we can detect vfio-pci devices
before realizing the vIOMMU device.
When the guest contains both the x86 vIOMMU and vfio-pci devices, the user
needs to specify the x86 vIOMMU before the vfio-pci devices. The reason is,
vfio_realize() calls
Note that patch 1-4 are cleanups for pci subsystem, and patch 5 is a fix to
fail early for mis-ordered qemu cmdline on vfio and vIOMMU. Logically they
should be posted separately and they're not directly related, however to make
it still correlated to v1 I kept them in the same patchset.
In this
They're actually more commonly used than the helper without _under_bus, because
most callers do have the pci bus on hand. After exporting we can switch a lot
of the call sites to use these two helpers.
Reviewed-by: David Hildenbrand
Reviewed-by: Eric Auger
Signed-off-by: Peter Xu
---
They're used in quite a few places of pci.[ch] and also in the rest of the code
base. Define them so that it doesn't need to be defined all over the places.
The pci_bus_fn is similar to pci_bus_dev_fn that only takes a PCIBus* and an
opaque. The pci_bus_ret_fn is similar to pci_bus_fn but it
Leonardo Bras Soares Passos writes:
[...]
>> The general argument for having QAPI schema 'if' mirror the C
>> implementation's #if is introspection. Let me explain why that matters.
>>
>> Consider a management application that supports a range of QEMU
>> versions, say 5.0 to 6.2. Say it wants
在 2021/10/27 14:31, Zheng Chuan 写道:
Hi.
I have no objection for the implement code itself.
But we should know or let the user know the performance penalty and conflicted
with migration compared to the hash method, especially for the performance of
vm with hugepages.
i dirty guest memory
On Mon, Oct 25, 2021 at 09:16:53AM -0400, Michael S. Tsirkin wrote:
> > +void pci_for_each_root_bus(pci_bus_fn fn, void *opaque)
> > +{
> > +pci_root_bus_args args = { .fn = fn, .opaque = opaque };
> > +
> > +object_child_foreach_recursive(object_get_root(), pci_find_root_bus,
> > );
> >
For constant shifts, we can simply shift the s_mask.
For variable shifts, we know that sar does not reduce
the s_mask, which helps for sequences like
ext32s_i64 t, in
sar_i64 t, t, v
ext32s_i64 out, t
allowing the final extend to be eliminated.
Reviewed-by: Alex Bennée
Sign repetitions are perforce all identical, whether they are 1 or 0.
Bitwise operations preserve the relative quantity of the repetitions.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 29
The result is either 0 or 1, which means that we have
a 2 bit signed result, and thus 62 bits of sign.
For clarity, use the smask_from_zmask function.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 2 ++
1 file changed, 2 insertions(+)
Move all of the known-zero optimizations into the per-opcode
functions. Use fold_masks when there is a possibility of the
result being determined, and simply set ctx->z_mask otherwise.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 545
Pull the "op r, a, i => mov r, a" optimization into a function,
and use them in the outer-most logical operations.
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 61 +-
1 file changed, 26 insertions(+), 35
Compute the type of the operation early.
There are at least 4 places that used a def->flags ladder
to determine the type of the operation being optimized.
There were two places that assumed !TCG_OPF_64BIT means
TCG_TYPE_I32, and so could potentially compute incorrect
results for vector
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 53 +-
1 file changed, 31 insertions(+), 22 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 5374c230da..8524fe1f8a
Hi Ilias,
On Tue, 26 Oct 2021 at 00:46, Ilias Apalodimas
wrote:
>
> Hi Simon,
>
> A bit late to the party, sorry!
(Did you remember the beer? I am replying to this but I don't think it
is all that helpful for me to reply to a lot of things on this thread,
since I would not be adding much to my
The results are generally 6 bit unsigned values, though
the count leading and trailing bits may produce any value
for a zero input.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On Wed, Oct 27, 2021 at 6:57 PM Andrew Melnichenko wrote:
>
> Hi,
> Let's make things clear.
> At first, I've decided to fix the issue in the linux e1000e driver.
> (https://lists.osuosl.org/pipermail/intel-wired-lan/Week-of-Mon-20200413/019497.html)
> Original driver developers suggest to fix
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 39 ++-
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 110b3d1cc2..faedbdbfb8 100644
---
Certain targets, like riscv, produce signed 32-bit results.
This can lead to lots of redundant extensions as values are
manipulated.
Begin by tracking only the obvious sign-extensions, and
converting them to simple copies when possible.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index dd65f1afcd..5374c230da 100644
---
This "garbage" setting pre-dates the addition of the type
changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64,
and INDEX_op_extr{l,h}_i64_i32.
So now we have a definitive points at which to adjust z_mask
to eliminate such bits from the 32-bit operands.
Reviewed-by: Alex Bennée
Rename to fold_addsub2.
Use Int128 to implement the wider operation.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 65 ++
1 file changed, 44
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 48 ++--
1 file changed, 30 insertions(+), 18 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index faedbdbfb8..3bd5f043c8
Rename to fold_multiply2, and handle muls2_i32, mulu2_i64,
and muls2_i64.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 44 +++-
1 file changed, 35 insertions(+), 9 deletions(-)
diff
Recognize the identity function for low-part multiply.
Suggested-by: Luis Pires
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tcg/optimize.c
Recognize the constant function for remainder.
Suggested-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index f8b0709157..7ac63c9231
Add two additional helpers, fold_add2_i32 and fold_sub2_i32
which will not be simple wrappers forever.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 70 +++---
1 file changed, 44
Recognize the identity function for division.
Suggested-by: Luis Pires
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
Even though there is only one user, place this more complex
conversion into its own helper.
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 89 ++
1 file changed, 47 insertions(+), 42 deletions(-)
diff --git
Recognize the constant function for or-complement.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index
This puts the separate mb optimization into the same framework
as the others. While fold_qemu_{ld,st} are currently identical,
that won't last as more code gets moved.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 89
Most of these are handled by creating a fold_const2_commutative
to handle all of the binary operators. The rest were already
handled on a case-by-case basis in the switch, and have their
own fold function in which to place the call.
We now have only one major switch on TCGOpcode.
Introduce
Split out the conditional conversion from a more complex logical
operation to a simple NOT. Create a couple more helpers to make
this easy for the outer-most logical operations.
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 158
Pull the "op r, 0, b => movi r, 0" optimization into a function,
and use it in fold_shift.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 28 ++--
1 file changed, 10 insertions(+), 18 deletions(-)
diff
Copy z_mask into OptContext, for writeback to the
first output within the new function.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 49 +
1 file changed, 33 insertions(+), 16
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 2c57d08760..dd65f1afcd 100644
---
Pull the "op r, a, 0 => movi r, 0" optimization into a function,
and use it in the outer opcode fold functions.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 38 --
1 file changed, 20
Return -1 instead of 2 for failure, so that we can
use comparisons against 0 for all cases.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 145 +
1 file changed, 74
This is the final entry in the main switch that was in a
different form. After this, we have the option to convert
the switch into a function dispatch table.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 27
Pull the "op r, a, a => movi r, 0" optimization into a function,
and use it in the outer opcode fold functions.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 41 -
1 file changed, 24
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 56 --
1 file changed, 31 insertions(+), 25 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 9d1d045363..110b3d1cc2
There was no real reason for calls to have separate code here.
Unify init for calls vs non-calls using the call path, which
handles TCG_CALL_DUMMY_ARG.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c |
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 24ba6d2830..f79cb44944 100644
--- a/tcg/optimize.c
Pull the "op r, a, a => mov r, a" optimization into a function,
and use it in the outer opcode fold functions.
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 39 ---
1 file changed, 24
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3bd5f043c8..2c57d08760 100644
---
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 33 +++--
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c9db14f1d0..24ba6d2830 100644
---
Prepare for tracking different masks by renaming this one.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 142 +
1 file changed, 72 insertions(+), 70
Continue splitting tcg_optimize.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/tcg/optimize.c
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 37 +
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index f79cb44944..805522f99d 100644
---
Split out a whole bunch of placeholder functions, which are
currently identical. That won't last as more code gets moved.
Use CASE_32_64_VEC for some logical operators that previously
missed the addition of vectors.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard
From: Luis Pires
These will be used to implement new decimal floating point
instructions from Power ISA 3.1.
The remainder is now returned directly by divu128/divs128,
freeing up phigh to receive the high 64 bits of the quotient.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
Reduce some code duplication by folding the NE and EQ cases.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 145 -
1 file changed, 72 insertions(+), 73 deletions(-)
diff --git
This will expose the variable to subroutines that
will be broken out of tcg_optimize.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
Reduce some code duplication by folding the NE and EQ cases.
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 159 +
1 file changed, 81 insertions(+), 78 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
Provide what will become a larger context for splitting
the very large tcg_optimize function.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 77 ++
1
Break the final cleanup clause out of the main switch
statement. When fully folding an opcode to mov/movi,
use "continue" to process the next opcode, else break
to fall into the final cleanup.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
From: Luis Pires
In preparation for changing the divu128/divs128 implementations
to allow for quotients larger than 64 bits, move the div-by-zero
and overflow checks to the callers.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
Message-Id:
Rather than try to keep these up-to-date across folding,
re-read nb_oargs at the end, after re-reading the opcode.
A couple of asserts need dropping, but that will take care
of itself as we split the function further.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 368457f4a2..699476e2f1 100644
---
From: Luis Pires
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
Message-Id: <20211025191154.350831-5-luis.pi...@eldorado.org.br>
Signed-off-by: Richard Henderson
---
tests/unit/test-div128.c | 197 +++
tests/unit/meson.build | 1 +
2 files
Calls are special in that they have a variable number
of arguments, and need to be able to clobber globals.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 63 --
1 file changed, 41
This will allow callers to tail call to these functions
and return true indicating processing complete.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 9 +
1 file changed, 5 insertions(+), 4
From: Frédéric Pétrot
Addition of not and xor on 128-bit integers.
Signed-off-by: Frédéric Pétrot
Co-authored-by: Fabien Portas
Message-Id: <20211025122818.168890-3-frederic.pet...@univ-grenoble-alpes.fr>
[rth: Split out logical operations.]
Reviewed-by: Richard Henderson
Signed-off-by:
Adjust the interface to take the OptContext parameter instead
of TCGContext or both.
Reviewed-by: Alex Bennée
Reviewed-by: Luis Pires
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 67 +-
1 file changed, 34 insertions(+), 33 deletions(-)
From: Luis Pires
Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils,
so it can be reused by divu128().
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
Message-Id: <20211025191154.350831-3-luis.pi...@eldorado.org.br>
Signed-off-by: Richard Henderson
---
The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027'
into staging (2021-10-27 11:45:18 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211027
On Wed, Oct 27, 2021 at 8:14 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:51 PM Rahul Pathak
> wrote:
> >
> > Patches add the mconfigptr csr support.
> > mconfigptr is newly incorporated in risc-v privileged architecture
> > specification 1.12 version.
> > priv spec 1.12.0 version
On Wed, Oct 27, 2021 at 8:08 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak
> wrote:
> >
> > Signed-off-by: Rahul Pathak
> > ---
> > target/riscv/cpu.c | 4 +++-
> > target/riscv/cpu.h | 1 +
> > 2 files changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git
On Wed, Oct 27, 2021 at 8:13 AM Alistair Francis
wrote:
> On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak
> wrote:
> >
> > Signed-off-by: Rahul Pathak
> > ---
> > target/riscv/cpu_bits.h | 1 +
> > target/riscv/csr.c | 19 +++
> > 2 files changed, 16 insertions(+), 4
On Wed, Oct 27, 2021 at 04:30:18PM +0800, Peter Xu wrote:
> On Tue, Oct 26, 2021 at 05:11:39PM +0200, Igor Mammedov wrote:
> > On Fri, 22 Oct 2021 10:14:29 +0800
> > Peter Xu wrote:
> >
> > > Hi, Alex,
> > >
> > > On Thu, Oct 21, 2021 at 04:30:39PM -0600, Alex Williamson wrote:
> > > > On Thu,
1 - 100 of 445 matches
Mail list logo
