Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO

On 11/2/21 6:42 AM, Peter Maydell wrote: On Tue, 2 Nov 2021 at 10:01, Richard Henderson wrote: On 11/1/21 3:35 PM, Peter Maydell wrote: On Mon, 1 Nov 2021 at 19:28, Richard Henderson wrote: On 10/26/21 3:12 AM, Alexander Graf wrote: Apple's Hypervisor.Framework forwards cache operations

[PULL 31/60] target/nios2: Implement nios2_cpu_record_sigsegv

Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/cpu.h|

[PULL 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu

This is not used by, nor required by, user-only. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/internal.h| 8 +++- target/ppc/excp_helper.c | 8 +++- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git

[PULL 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu

We have replaced tlb_fill with record_sigsegv for user mode. Move the declaration to restrict it to system emulation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 22 ++ linux-user/signal.c | 3 --- 2

[PULL 57/60] accel/tcg: Report unaligned atomics for user-only

Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Warner Losh Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 13 - 1 file changed, 12 insertions(+), 1

[PULL 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access

We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: qemu-...@nongnu.org Reviewed-by: Warner Losh Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/excp_helper.c | 14 ++ 1 file changed, 14 insertions(+) diff

[PULL 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling

We will raise SIGBUS directly from cpu_loop_exit_sigbus. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index

[PULL 54/60] target/sparc: Remove DEBUG_UNALIGNED

The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland

[PULL 37/60] target/s390x: Implement s390_cpu_record_sigsegv

Move the masking of the address from cpu_loop into s390_cpu_record_sigsegv -- this is governed by hw, not linux. This does mean we have to raise our own exception, rather than return to the fallback. Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING. Use the appropriate si_code for

[PULL 42/60] hw/core: Add TCGCPUOps.record_sigbus

Add a new user-only interface for updating cpu state before raising a signal. This will take the place of do_unaligned_access for user-only and should result in less boilerplate for each guest. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 23

[PULL 30/60] target/mips: Make mips_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for mips linux-user. This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp

By doing this while sending the exception, we will have already done the unwinding, which makes the ppc_cpu_do_unaligned_access code a bit cleaner. Update the comment about the expected instruction format. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---

[PULL 44/60] target/alpha: Implement alpha_cpu_record_sigbus

Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 8 +---

[PULL 40/60] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for xtensa linux-user. Remove the code from cpu_loop that raised SIGSEGV. Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +-

[PULL 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for hppa linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by:

[PULL 39/60] target/sparc: Make sparc_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for sparc linux-user. This makes all of the code in mmu_helper.c sysemu only, so remove the ifdefs and move the file to sparc_softmmu_ss. Remove the code from cpu_loop that handled TT_DFAULT and TT_TFAULT. Cc: Mark Cave-Ayland

[PULL 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for cris linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. This makes all of the code in helper.c sysemu only, so remove the ifdefs and move the file to cris_softmmu_ss. Reviewed-by: Philippe Mathieu-Daudé

[PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill

The fallback code in cpu_loop_exit_sigsegv is sufficient for hexagon linux-user. Remove the code from cpu_loop that raises SIGSEGV. Reviewed-by: Taylor Simpson Signed-off-by: Richard Henderson --- linux-user/hexagon/cpu_loop.c | 24 +--- target/hexagon/cpu.c | 23

[PULL 43/60] linux-user: Add cpu_loop_exit_sigbus

This is a new interface to be provided by the os emulator for raising SIGBUS on fault. Use the new record_sigbus target hook. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 14 ++ linux-user/signal.c

[PULL 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER

Now that all of the linux-user hosts have been converted to host-signal.h, drop the compatibility code. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 linux-user/signal.c | 14 -- 2

[PULL 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for openrisc linux-user. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Reviewed-by: Philippe Mathieu-Daudé

[PULL 29/60] target/microblaze: Make mb_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for microblaze linux-user. Remove the code from cpu_loop that handled the unnamed 0xaa exception. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h

[PULL 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for m68k linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 10 -- target/m68k/cpu.c | 2 +-

[PULL 16/60] target/arm: Fixup comment re handle_cpu_signal

The named function no longer exists. Refer to host_signal_handler instead. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/sve_helper.c

[PULL 20/60] linux-user: Add cpu_loop_exit_sigsegv

This is a new interface to be provided by the os emulator for raising SIGSEGV on fault. Use the new record_sigsegv target hook. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++

[PULL 23/60] target/arm: Implement arm_cpu_record_sigsegv

Because of the complexity of setting ESR, continue to use arm_deliver_fault. This means we cannot remove the code within cpu_loop that decodes EXCP_DATA_ABORT and EXCP_PREFETCH_ABORT. But using the new hook means that we don't have to do the page_get_flags check manually, and we'll be able to

[PULL 34/60] target/ppc: Implement ppc_cpu_record_sigsegv

Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Warner Losh Reviewed-by:

[PULL 21/60] target/alpha: Implement alpha_cpu_record_sigsegv

Record trap_arg{0,1,2} for the linux-user signal frame. Fill in the stores to trap_arg{1,2} that were missing from the previous user-only alpha_cpu_tlb_fill function. Use maperr to simplify computation of trap_arg1. Remove the code for EXCP_MMFAULT from cpu_loop, as that part is now handled by

[PULL 17/60] linux-user/host/riscv: Improve host_signal_write

Do not read 4 bytes before we determine the size of the insn. Simplify triple switches in favor of checking major opcodes. Include the missing cases of compact fsd and fsdsp. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 83

[PULL 09/60] linux-user/host/alpha: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/alpha/host-signal.h | 42 + accel/tcg/user-exec.c | 31 + 2 files changed, 43

[PULL 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for sh4 linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 6 +++--- linux-user/sh4/cpu_loop.c | 8

[PULL 13/60] linux-user/host/s390: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/s390/host-signal.h | 94 - linux-user/host/s390x/host-signal.h | 2 +-

[PULL 12/60] linux-user/host/aarch64: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 75 - accel/tcg/user-exec.c | 94

[PULL 11/60] linux-user/host/arm: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/arm/host-signal.h | 31 -

[PULL 36/60] target/s390x: Use probe_access_flags in s390_probe_access

Not sure why the user-only code wasn't rewritten to use probe_access_flags at the same time that the sysemu code was converted. For the purpose of user-only, this is an exact replacement. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c |

[PULL 08/60] linux-user/host/ppc: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/ppc/host-signal.h | 26 +- linux-user/host/ppc64/host-signal.h | 2 +-

[PULL 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only

The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7

[PULL 05/60] configure: Merge riscv32 and riscv64 host architectures

The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson ---

[PULL 10/60] linux-user/host/sparc: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Drop the Solaris code as completely unused. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/sparc/host-signal.h | 55

[PULL 00/60] accel/tcg patch queue

The following changes since commit dd61b91c080cdfba1360a5ea1e4693fffb3445b0: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-29' into staging (2021-10-29 19:42:36 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211102

[PULL 27/60] target/i386: Implement x86_cpu_record_sigsegv

Record cr2, error_code, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. Use the maperr parameter to properly set PG_ERROR_P_MASK. Reviewed by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by:

[PULL 07/60] linux-user/host/x86: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/i386/host-signal.h | 26 - linux-user/host/x32/host-signal.h| 2 +-

[PULL 03/60] accel/tcg: Split out handle_sigsegv_accerr_write

This is the major portion of handle_cpu_signal which is specific to tcg, handling the page protections for the translations. Most of the rest will migrate to linux-user/ shortly. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Pass guest

[PULL 06/60] linux-user: Reorg handling for SIGSEGV

Add stub host-signal.h for all linux-user hosts. Add new code replacing cpu_signal_handler. Full migration will happen one host at a time. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Richard Henderson ---

[PULL 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup

Use the new os interface for raising the exception, rather than calling arm_cpu_tlb_fill directly. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git

[PULL 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller

Remove the comment about siglongjmp. We do use sigsetjmp in the main cpu loop, but we do not save the signal mask as most exits from the cpu loop do not require them. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 14 ++ 1 file changed, 2

[PULL 11/12] target/arm: Use tcg_constant_i32() in gen_rev16()

From: Philippe Mathieu-Daudé Since the mask is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211029231834.2476117-6-f4...@amsat.org> Signed-off-by: Richard Henderson ---

[PULL 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop

Currently there are only two places that require we reset this value before exiting to the main loop, but that will change. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 ++- accel/tcg/user-exec.c | 2 -- 2 files changed, 2 insertions(+), 3

[PULL 15/60] linux-user/host/riscv: Populate host_signal.h

Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Warner Losh Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/host/riscv/host-signal.h | 86 +- accel/tcg/user-exec.c | 134 2

[PULL 12/12] hw/arm/virt: Rename default_bus_bypass_iommu

From: Jean-Philippe Brucker Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine parameter definitions cannot use underscores, because keyval_dashify() transforms them to dashes and the parser doesn't find the parameter. This affects option default_bus_bypass_iommu which was

[PULL 09/12] target/arm: Use the constant variant of store_cpu_field() when possible

From: Philippe Mathieu-Daudé When using a constant variable, we can replace the store_cpu_field() call by store_cpu_field_constant() which avoid using TCG temporaries. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211029231834.2476117-4-f4...@amsat.org>

[PULL 01/60] accel/tcg: Split out adjust_signal_pc

Split out a function to adjust the raw signal pc into a value that could be passed to cpu_restore_state. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Adjust pc in place; return MMUAccessType. --- include/exec/exec-all.h | 10 ++

[PULL 07/12] target/arm: Use tcg_constant_i32() in op_smlad()

From: Philippe Mathieu-Daudé Avoid using a TCG temporary for a read-only constant. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211029231834.2476117-2-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/arm/translate.c | 3 +-- 1 file changed,

[PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv

Add a new user-only interface for updating cpu state before raising a signal. This will replace tlb_fill for user-only and should result in less boilerplate for each guest. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 26

[PULL 08/12] target/arm: Introduce store_cpu_field_constant() helper

From: Philippe Mathieu-Daudé Similarly to the store_cpu_field() helper which takes a TCG temporary, store its value to the CPUState, introduce the store_cpu_field_constant() helper which store a constant to CPUState (without using any TCG temporary). Suggested-by: Richard Henderson

[PULL 10/12] target/arm: Use tcg_constant_i64() in do_sat_addsub_64()

From: Philippe Mathieu-Daudé The immediate value used for comparison is constant and read-only. Move it to the constant pool. This frees a TCG temporary for unsigned saturation opcodes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id:

[PULL 03/12] hw/arm: Attach MMC to quanta-gbs-bmc

From: Shengtan Mao Signed-off-by: Shengtan Mao Signed-off-by: Hao Wu Reviewed-by: Hao Wu Reviewed-by: Tyrone Ting Reviewed-by: Peter Maydell Message-Id: <20211008002628.1958285-4-wuhao...@google.com> Signed-off-by: Richard Henderson --- hw/arm/npcm7xx_boards.c | 20 1

[PULL 04/12] tests/qtest/libqos: add SDHCI commands

From: Shengtan Mao Signed-off-by: Shengtan Mao Signed-off-by: Hao Wu Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting Reviewed-by: Peter Maydell Message-Id: <20211008002628.1958285-5-wuhao...@google.com> Signed-off-by: Richard Henderson ---

[PULL 06/12] target/arm: Advertise MVE to gdb when present

From: Peter Maydell Cortex-M CPUs with MVE should advertise this fact to gdb, using the org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR register. Presence of this feature also tells gdb to create pseudo-registers Q0..Q7, so we do not need to tell gdb about them separately.

[PULL 00/12] target/arm patch queue

The following changes since commit dd61b91c080cdfba1360a5ea1e4693fffb3445b0: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-29' into staging (2021-10-29 19:42:36 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-arm-20211102

[PULL 05/12] tests/qtest: add qtests for npcm7xx sdhci

From: Shengtan Mao Signed-off-by: Shengtan Mao Signed-off-by: Hao Wu Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting Reviewed-by: Peter Maydell Message-Id: <20211008002628.1958285-6-wuhao...@google.com> Signed-off-by: Richard Henderson ---

[PULL 02/12] hw/arm: Add Nuvoton SD module to board

From: Shengtan Mao Signed-off-by: Shengtan Mao Signed-off-by: Hao Wu Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting Reviewed-by: Peter Maydell Message-Id: <20211008002628.1958285-3-wuhao...@google.com> Signed-off-by: Richard Henderson --- include/hw/arm/npcm7xx.h |

[PULL 01/12] hw/sd: add nuvoton MMC

From: Shengtan Mao Signed-off-by: Shengtan Mao Signed-off-by: Hao Wu Reviewed-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Tyrone Ting Reviewed-by: Peter Maydell Message-Id: <20211008002628.1958285-2-wuhao...@google.com> [rth: Fix typos of "nonexistent"] Signed-off-by: Richard

[PATCH v2] meson.build: Allow to disable OSS again

If sys/soundcard.h is available, it is currently not possible to disable OSS with the --disable-oss or --without-default-features configure switches. Improve the check in meson.build to fix this. Fixes: 87430d5b13 ("configure, meson: move audio driver detection to Meson") Signed-off-by: Thomas

Re: [PATCH 0/3] SEV: fixes for -kernel launch with incompatible OVMF

Hi Dov, Overall the patch looks good, only question I have is that now we are enforce qemu to hash the kernel, initrd and cmdline unconditionally for any of the SEV guest launches. This requires anyone wanting to calculating the expected measurement need to account for it. Should we make the hash

Re: [RFC PATCH 07/15] job-driver.h: add helper functions

29.10.2021 19:39, Emanuele Giuseppe Esposito wrote: These functions will be useful when job_lock is globally applied, as they will allow drivers to access the job struct fields without worrying about the job lock. Now that we are done with the job API header split, update also the comments in

Re: [PATCH v2 0/4] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts

Hello, On Mon, 25 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/25/21 13:33, BALATON Zoltan wrote: This is the same as posted before just omitting the two patches that are optimisations by caching the func0 and avoiding QOM casts which could not be measured to have an effect but these

Re: [RFC PATCH 08/15] job.c: minor adjustments in preparation to job-driver

29.10.2021 19:39, Emanuele Giuseppe Esposito wrote: job_event_* functions can be all static, as they are not used outside job.c Add also missing notifier initialization for the on_idle list in job_create(). Signed-off-by: Emanuele Giuseppe Esposito --- job.c | 13 +++-- 1 file

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Nov 2, 2021 at 6:24 PM Anup Patel wrote: > > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > > > A hypervsior can optionally take guest external interrupts using > > > > typo: hypervisor > > Okay, I will update. > > > > >

Re: [PATCH 2/2] qtest/am53c974-test: add test for cancelling in-flight requests

On 01/11/21 19:35, Mark Cave-Ayland wrote: Based upon the qtest reproducer posted to Gitlab issue #663 at https://gitlab.com/qemu-project/qemu/-/issues/663. Signed-off-by: Mark Cave-Ayland --- tests/qtest/am53c974-test.c | 36 1 file changed, 36

Re: [PATCH v2 0/5] hw/arm: Add NPCM7XX Tachometer Device

On Tue, 2 Nov 2021 at 10:03, Richard Henderson wrote: > > On 11/1/21 1:50 PM, Hao Wu wrote: > > Is this reply to a wrong thread? I thought it was applied a long time ago. > > Probably. Possibly you meant this 5-patch NPCM7xx series ?

Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO

On Tue, 2 Nov 2021 at 10:01, Richard Henderson wrote: > > On 11/1/21 3:35 PM, Peter Maydell wrote: > > On Mon, 1 Nov 2021 at 19:28, Richard Henderson > > wrote: > >> > >> On 10/26/21 3:12 AM, Alexander Graf wrote: > >>> Apple's Hypervisor.Framework forwards cache operations as MMIO traps > >>>

Re: [PATCH v2 3/3] KVM: SVM: add migration support for nested TSC scaling

On 01/11/21 14:23, Maxim Levitsky wrote: Signed-off-by: Maxim Levitsky --- target/i386/cpu.c | 5 + target/i386/cpu.h | 4 target/i386/kvm/kvm.c | 15 +++ target/i386/machine.c | 23 +++ 4 files changed, 47 insertions(+) It's easier to

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > A hypervsior can optionally take guest external interrupts using > > typo: hypervisor Okay, I will update. > > > SGEIP bit of hip and hie CSRs. > > > > Signed-off-by: Anup Patel > >

Re: [PATCH] vhost: Fix last queue index of devices with no cvq

On Tue, Nov 2, 2021 at 8:04 AM Jason Wang wrote: > > On Tue, Nov 2, 2021 at 2:59 PM Eugenio Perez Martin > wrote: > > > > On Tue, Nov 2, 2021 at 5:09 AM Jason Wang wrote: > > > > > > On Mon, Nov 1, 2021 at 4:59 PM Eugenio Perez Martin > > > wrote: > > > > > > > > On Mon, Nov 1, 2021 at 4:34

Re: [RFC PATCH v5 22/26] vhost: Shadow virtqueue buffers forwarding

On Tue, Nov 2, 2021 at 8:59 AM Jason Wang wrote: > > > 在 2021/10/30 上午2:35, Eugenio Pérez 写道: > > Initial version of shadow virtqueue that actually forward buffers. There > > are no iommu support at the moment, and that will be addressed in future > > patches of this series. Since all vhost-vdpa

Re: [RFC PATCH 03/15] job-common.h: categorize fields in struct Job

On Fri, Oct 29, 2021 at 12:39:02PM -0400, Emanuele Giuseppe Esposito wrote: > Categorize the fields in struct Job to understand which need > to be protected by the job muutex and which not. s/muutex/mutex/ (__) `\--(oo) ||(__) .o( moo-tex ) ||w--|| BTW "which ones

Re: [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN

On 11/1/21 6:01 AM, LIU Zhiwei wrote: The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c

Re: [PATCH 02/13] target/riscv: Extend pc for runtime pc write

On 11/1/21 9:48 PM, LIU Zhiwei wrote: On 2021/11/1 下午6:33, Richard Henderson wrote: On 11/1/21 6:01 AM, LIU Zhiwei wrote: In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hit zero. So extend pc register according to

Re: [RFC PATCH 02/15] job.c: make job_lock/unlock public

On Fri, Oct 29, 2021 at 12:39:01PM -0400, Emanuele Giuseppe Esposito wrote: > job mutex will be used to protect the job struct elements and list, > replacing AioContext locks. > > Right now use a shared lock for all jobs, in order to keep things > simple. Once the AioContext lock is gone, we can

Re: [RFC PATCH 01/15] jobs: add job-common.h

On Fri, Oct 29, 2021 at 12:39:00PM -0400, Emanuele Giuseppe Esposito wrote: > job-common.h contains all struct and common function that currently > are in job.h and will be shared by job-monitor and job-driver in > the next commits. > > No functional change intended. > > Signed-off-by: Emanuele

Re: [PATCH 00/16] fdt: Make OF_BOARD a boolean option

Hi, > On Thu, 28 Oct 2021 at 05:51, Simon Glass wrote: > > On Tue, 26 Oct 2021 at 00:46, Ilias Apalodimas > > wrote: .. > > Linux actually doesn't care if the U-Boot properties are in the tree, > > so long as we have proper bindings. My point here is we only need > > either: > > > > a. one

Re: [RFC PATCH 00/15] job: replace AioContext lock with job_mutex

On Fri, Oct 29, 2021 at 12:38:59PM -0400, Emanuele Giuseppe Esposito wrote: > RFC: not sure if the current patch organization is correct. > Bisecting in patches in between this serie would cause tests > to deadlock. Patch series must be bisectable. It will be necessary to fix this. Stefan

Re: [PATCH v2 0/5] hw/arm: Add NPCM7XX Tachometer Device

On 11/1/21 1:50 PM, Hao Wu wrote: Is this reply to a wrong thread? I thought it was applied a long time ago. Probably. r~ Thanks, On Mon, Nov 1, 2021 at 10:33 AM Richard Henderson > wrote: On Thu, 11 Mar 2021 at 13:11, Hao Wu

Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO

On 11/1/21 3:35 PM, Peter Maydell wrote: On Mon, 1 Nov 2021 at 19:28, Richard Henderson wrote: On 10/26/21 3:12 AM, Alexander Graf wrote: Apple's Hypervisor.Framework forwards cache operations as MMIO traps into user space. For MMIO however, these have no meaning: There is no cache attached

Re: [PULL 00/22] Python patches

On 11/1/21 1:29 PM, John Snow wrote: The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e: Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into staging (2021-10-30 11:31:41 -0700) are available in the Git repository at:

Re: [PATCH 0/5] hw/core: Remove uses of obsolete QERR_ definitions

On 10/30/21 01:01, Philippe Mathieu-Daudé wrote: QERR_ definitions are obsolete since 2015... Remove their uses in hw/core/. Philippe Mathieu-Daudé (5): hw/core: Remove use of QERR_UNSUPPORTED hw/core: Remove use of QERR_FEATURE_DISABLED hw/core: Remove uses of

Re: [PATCH 4/5] hw/core: Remove uses of QERR_PROPERTY_VALUE_BAD

On 10/30/21 01:01, Philippe Mathieu-Daudé wrote: QERR_PROPERTY_VALUE_BAD definition is obsolete since 2015 (commit 4629ed1e989, "qerror: Finally unused, clean up"). Replace the two uses and drop the definition. Signed-off-by: Philippe Mathieu-Daudé --- include/qapi/qmp/qerror.h | 3 ---

Re: [PULL 1/5] hw/pcie-root-port: Fix hotplug for PCI devices requiring IO

Hi Daniel, On Tue, Nov 2, 2021 at 11:24 AM Daniel P. Berrangé wrote: > On Mon, Sep 27, 2021 at 05:49:15AM -0400, Michael S. Tsirkin wrote: > > On Mon, Sep 27, 2021 at 10:33:42AM +0100, Daniel P. Berrangé wrote: > > > On Tue, Aug 03, 2021 at 04:52:03PM -0400, Michael S. Tsirkin wrote: > > > >

Re: [PATCH v2] hmp: Add shortcut to stop command to match cont

On Sat, Oct 30, 2021 at 11:49:37AM +0200, BALATON Zoltan wrote: > Some commands such as quit or cont have one letter alternatives but > stop is missing that. Add stop|s to match cont|c for consistency and > convenience. > > Signed-off-by: BALATON Zoltan > --- > c2: Fixed typo in commit title >

Re: [PULL 1/5] hw/pcie-root-port: Fix hotplug for PCI devices requiring IO

On Mon, Sep 27, 2021 at 05:49:15AM -0400, Michael S. Tsirkin wrote: > On Mon, Sep 27, 2021 at 10:33:42AM +0100, Daniel P. Berrangé wrote: > > On Tue, Aug 03, 2021 at 04:52:03PM -0400, Michael S. Tsirkin wrote: > > > From: Marcel Apfelbaum > > > > > > Q35 has now ACPI hotplug enabled by default

Re: [PATCH v1 1/2] migration: block-dirty-bitmap: add missing qemu_mutex_lock_iothread

Juan Quintela wrote: > Emanuele Giuseppe Esposito wrote: >> init_dirty_bitmap_migration assumes the iothread lock (BQL) >> to be held, but instead it isn't. >> >> Instead of adding the lock to qemu_savevm_state_setup(), >> follow the same pattern as the other ->save_setup callbacks >> and

Re: [PATCH 2/9] qapi: Mark unstable QMP parts with feature 'unstable'

Am 29.10.2021 um 15:07 hat Eric Blake geschrieben: > On Mon, Oct 25, 2021 at 07:25:25AM +0200, Markus Armbruster wrote: > > Add special feature 'unstable' everywhere the name starts with 'x-', > > except for InputBarrierProperties member x-origin and > > MemoryBackendProperties member

Re: [PATCH] nvmm: Fix support for stable version

Reviewed-by: Kamil Rytarowski Paolo, could you please merge it? On 13.10.2021 15:54, nia wrote: > NVMM user version 1 is the version being shipped with netbsd-9, > which is the most recent stable branch of NetBSD. This makes it > possible to use the NVMM accelerator on the most recent NetBSD >

Re: [PATCH v1 1/2] migration: block-dirty-bitmap: add missing qemu_mutex_lock_iothread

Emanuele Giuseppe Esposito wrote: > init_dirty_bitmap_migration assumes the iothread lock (BQL) > to be held, but instead it isn't. > > Instead of adding the lock to qemu_savevm_state_setup(), > follow the same pattern as the other ->save_setup callbacks > and lock+unlock inside

Re: [PATCH 2/2] failover: don't allow to migrate a paused VM that needs PCI unplug

Laurent Vivier wrote: > As the guest OS is paused, we will never receive the unplug event > from the kernel and the migration cannot continue. > > Signed-off-by: Laurent Vivier Reviewed-by: Juan Quintela queued. I can't think of a better solution.

Re: [PATCH 1/2] migration: provide an error message to migration_cancel()

Laurent Vivier wrote: > This avoids to call migrate_get_current() in the caller function > whereas migration_cancel() already needs the pointer to the current > migration state. > > Signed-off-by: Laurent Vivier Reviewed-by: Juan Quintela queued. > error_setg(, "RAM block '%s'

Re: [PATCH v2 7/7] hw/arm: Add ID for NPCM7XX SMBus

+Markus/Eduardo On 11/1/21 18:33, Peter Maydell wrote: > On Thu, 21 Oct 2021 at 19:40, Hao Wu wrote: >> >> The ID can be used to indicate SMBus modules when adding >> dynamic devices to them. >> >> Signed-off-by: Hao Wu >> --- >> hw/arm/npcm7xx.c | 1 + >> 1 file changed, 1 insertion(+) >> >>

Re: [PATCH v3 3/3] hw/i386: expose a "smbios-entry-point-type" PC machine property

On 10/26/21 17:11, Eduardo Habkost wrote: > The i440fx and Q35 machine types are both hardcoded to use the > legacy SMBIOS 2.1 (32-bit) entry point. This is a sensible > conservative choice because SeaBIOS only supports SMBIOS 2.1 > > EDK2, however, can also support SMBIOS 3.0 (64-bit) entry

Re: [PATCH v2] failover: specify an alternate MAC address

On Tue, Nov 02, 2021 at 09:14:51AM +0100, Laurent Vivier wrote: > On 01/11/2021 10:39, Michael S. Tsirkin wrote: > > On Wed, Oct 27, 2021 at 11:59:45AM +0200, Laurent Vivier wrote: > > > If the guest driver doesn't support the STANDBY feature, by default > > > we keep the virtio-net device and

<    1   2   3   4   5   6   >