RE: [RFC] vhost-vdpa-net: add vhost-vdpa-net host device support

> -Original Message- > From: Jason Wang [mailto:jasow...@redhat.com] > Sent: Wednesday, December 8, 2021 2:27 PM > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > > Cc: mst ; Parav Pandit ; Yongji Xie > ; Stefan Hajnoczi ; Stefano > Garzarella ; Yechuan ; Gonglei

[PATCH v5 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward all wired interrupts as MSIs to the

[PATCH v5 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled Interupts). This patch

[PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 1 + 2

[PATCH v5 15/23] target/riscv: Implement AIA IMSIC interface CSRs

The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel --- target/riscv/csr.c | 202

[PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anup Patel ---

[PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel --- target/riscv/csr.c | 155 + 1 file changed, 155 insertions(+) diff --git a/target/riscv/csr.c

[PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs

The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local interrupts above 12 so

[PATCH v5 22/23] docs/system: riscv: Document AIA options for virt machine

We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- docs/system/riscv/virt.rst | 16 1 file changed, 16 insertions(+) diff --git

[PATCH v5 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 7 ++ target/riscv/csr.c |

[PATCH v5 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level guest interrupt

[PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities

The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subsequent patches.

[PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example, AIA IMSIC

[PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 14 +- target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c| 560 +++---

[PATCH v5 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel --- hw/riscv/Kconfig| 1 +

[PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel --- target/riscv/cpu.h| 23 +++ target/riscv/cpu_helper.c | 14 ++ 2

[PATCH v5 04/23] target/riscv: Improve delivery of guest external interrupts

The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish response to serial

[PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 126 +

[PATCH v5 07/23] target/riscv: Add defines for AIA CSRs

The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 127 1 file changed, 127 insertions(+) diff --git

[PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 18 +++--- 3 files changed, 16

[PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 13 +++-- 1 file changed, 11

[PATCH v5 06/23] target/riscv: Add AIA cpu feature

We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 ++-

[PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs

The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 61

[PATCH v5 00/23] QEMU RISC-V AIA support

The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here:

[PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file

RE: [RFC] vhost-vdpa-net: add vhost-vdpa-net host device support

> -Original Message- > From: Stefano Garzarella [mailto:sgarz...@redhat.com] > Sent: Thursday, December 9, 2021 11:55 PM > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > > Cc: Stefan Hajnoczi ; jasow...@redhat.com; > m...@redhat.com; > pa...@nvidia.com;

RE: [RFC] vhost-vdpa-net: add vhost-vdpa-net host device support

> -Original Message- > From: Stefan Hajnoczi [mailto:stefa...@redhat.com] > Sent: Thursday, December 9, 2021 5:17 PM > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > > Cc: jasow...@redhat.com; m...@redhat.com; pa...@nvidia.com; > xieyon...@bytedance.com;

RE: [RFC] vhost-vdpa-net: add vhost-vdpa-net host device support

> -Original Message- > From: Michael S. Tsirkin [mailto:m...@redhat.com] > Sent: Thursday, December 9, 2021 3:05 AM > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > > Cc: jasow...@redhat.com; pa...@nvidia.com; xieyon...@bytedance.com; > stefa...@redhat.com;

[PATCH] iotests/testrunner.py: refactor test_field_width

A lot of Optional[] types doesn't make code beautiful. test_field_width defaults to 8, but that is never used in the code. More over, if we want some default behavior for single call of test_run(), it should just print the whole test name, not limiting or expanding its width, so 8 is bad default.

Re: [PATCH 2/3] iotests/testrunner.py: move updating last_elapsed to run_tests

10.12.2021 17:47, Vladimir Sementsov-Ogievskiy wrote: 10.12.2021 17:25, Kevin Wolf wrote: Am 06.12.2021 um 18:59 hat John Snow geschrieben: On Fri, Dec 3, 2021 at 7:22 AM Vladimir Sementsov-Ogievskiy < vsement...@virtuozzo.com> wrote: We are going to use do_run_test() in multiprocessing

[PATCH] xen-hvm: Allow disabling buffer_io_timer

commit f37f29d31488 "xen: slightly simplify bufioreq handling" hard coded setting req.count = 1 during initial field setup before the main loop. This missed a subtlety that an early exit from the loop when there are no ioreqs to process, would have req.count == 0 for the return value.

Re: [RFC PATCH v2] blog post: how to get your new feature up-streamed

On Mon, 6 Dec 2021 at 14:14, Alex Bennée wrote: > > Experience has shown that getting new functionality up-streamed can be > a somewhat painful process. Lets see if we can collect some of our > community knowledge into a blog post describing some best practices > for getting code accepted. > >

Re: [PATCH] spec: Add NBD_OPT_EXTENDED_HEADERS

04.12.2021 02:14, Eric Blake wrote: Add a new negotiation feature where the client and server agree to use larger packet headers on every packet sent during transmission phase. This has two purposes: first, it makes it possible to perform operations like trim, write zeroes, and block status on

Re: [PATCH] spec: Add NBD_OPT_EXTENDED_HEADERS

07.12.2021 12:08, Vladimir Sementsov-Ogievskiy wrote: 07.12.2021 02:00, Eric Blake wrote: On Mon, Dec 06, 2021 at 02:40:45PM +0300, Vladimir Sementsov-Ogievskiy wrote: [..] +S: 64 bits, padding (MUST be zero) Hmm. Extra 8 bytes to be power-of-2. Does 32 bytes really perform better than

Re: [RFC PATCH 09/12] qapi/qom: Convert rng-backend/random to class

Am 23.11.2021 um 14:15 hat Markus Armbruster geschrieben: > Kevin Wolf writes: > > > Signed-off-by: Kevin Wolf > > --- > > qapi/qom.json | 22 -- > > 1 file changed, 16 insertions(+), 6 deletions(-) > > > > diff --git a/qapi/qom.json b/qapi/qom.json > > index

Re: [RFC PATCH 07/12] qapi: Allow defining QOM classes

Am 23.11.2021 um 11:02 hat Markus Armbruster geschrieben: > Kevin Wolf writes: > > > Signed-off-by: Kevin Wolf > > --- > > scripts/qapi/expr.py | 28 +- > > scripts/qapi/schema.py | 66 ++ > > 2 files changed, 93 insertions(+), 1

Re: [PATCH v5 09/31] block: introduce assert_bdrv_graph_writable

On 24.11.21 07:43, Emanuele Giuseppe Esposito wrote: We want to be sure that the functions that write the child and parent list of a bs are under BQL and drain. BQL prevents from concurrent writings from the GS API, while drains protect from I/O. TODO: drains are missing in some functions

Re: [RFC PATCH 08/12] qapi: Create qom-config:... type for classes

Am 23.11.2021 um 14:00 hat Markus Armbruster geschrieben: > Kevin Wolf writes: > > > For every class that has a 'config' definition, a corresponding > > 'qom-config:$QOM_TYPE' type is automatically created that contains the > > configuration for the class and all of its parent classes. > > > >

[PATCH v7 5/8] tests/acpi: allow updates of VIOT expected data files

Create empty data files and allow updates for the upcoming VIOT tests. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ tests/data/acpi/q35/DSDT.viot | 0 tests/data/acpi/q35/VIOT.viot

[PATCH v7 4/8] hw/arm/virt: Use object_property_set instead of qdev_prop_set

To propagate errors to the caller of the pre_plug callback, use the object_poperty_set*() functions directly instead of the qdev_prop_set*() helpers. Suggested-by: Igor Mammedov Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Signed-off-by: Jean-Philippe Brucker --- hw/arm/virt.c | 5

[PATCH v7 7/8] tests/acpi: add expected blobs for VIOT test on q35 machine

Add expected blobs of the VIOT and DSDT table for the VIOT test on the q35 machine. Since the test instantiates a virtio device and two PCIe expander bridges, DSDT.viot has more blocks than the base DSDT. The VIOT table generated for the q35 test is: [000h 4]Signature

[PATCH v7 8/8] tests/acpi: add expected blob for VIOT test on virt machine

The VIOT blob contains the following: [000h 4]Signature : "VIOT"[Virtual I/O Translation Table] [004h 0004 4] Table Length : 0058 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 66 [00Ah 0010

[PATCH v7 3/8] hw/arm/virt: Reject instantiation of multiple IOMMUs

We do not support instantiating multiple IOMMUs. Before adding a virtio-iommu, check that no other IOMMU is present. This will detect both "iommu=smmuv3" machine parameter and another virtio-iommu instance. Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings") Reviewed-by:

[PATCH v7 1/8] hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu

When a virtio-iommu is instantiated, describe it using the ACPI VIOT table. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker --- hw/arm/virt-acpi-build.c | 7 +++ hw/arm/Kconfig | 1 + 2 files changed, 8 insertions(+) diff --git

[PATCH v7 0/8] virtio-iommu: Add ACPI support (Arm part + tests)

Add ACPI support for virtio-iommu on the virt machine, by instantiating a VIOT table. Also add the tests for the ACPI table. Since last posting [1], I rebased onto v6.2.0-rc4. Note that v6 of this series [2] only contained the table and x86 support, which have been merged. Everything has now been

[PATCH v7 6/8] tests/acpi: add test case for VIOT

Add two test cases for VIOT, one on the q35 machine and the other on virt. To test complex topologies the q35 test has two PCIe buses that bypass the IOMMU (and are therefore not described by VIOT), and two buses that are translated by virtio-iommu. Reviewed-by: Eric Auger Reviewed-by: Igor

[PATCH v7 2/8] hw/arm/virt: Remove device tree restriction for virtio-iommu

virtio-iommu is now supported with ACPI VIOT as well as device tree. Remove the restriction that prevents from instantiating a virtio-iommu device under ACPI. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker --- hw/arm/virt.c| 10 ++

Re: [RFC PATCH 10/12] qapi: Generate QOM config marshalling code

Am 23.11.2021 um 15:16 hat Markus Armbruster geschrieben: > Kevin Wolf writes: > > > Signed-off-by: Kevin Wolf > > --- > > backends/rng-random.c | 17 ++-- > > backends/rng.c| 17 ++-- > > scripts/qapi/main.py | 2 + > > scripts/qapi/qom.py | 91

Re: [PATCH v2] hw/net: npcm7xx_emc fix missing queue_flush

On Fri, 3 Dec 2021 at 22:10, Patrick Venture wrote: > > The rx_active boolean change to true should always trigger a try_read > call that flushes the queue. > > Signed-off-by: Patrick Venture > --- > v2: introduced helper method to encapsulate rx activation and queue flush. > --- >

Re: [PATCH 3/3] iotests: check: multiprocessing support

Am 10.12.2021 um 15:46 hat Vladimir Sementsov-Ogievskiy geschrieben: > 10.12.2021 17:36, Kevin Wolf wrote: > > Am 03.12.2021 um 13:22 hat Vladimir Sementsov-Ogievskiy geschrieben: > > > Add -j parameter, to run tests in several jobs simultaneously. > > > For realization - simply utilize

Re: [PATCH 4/4] target/ppc: move xscvqpdp to decodetree

On 10/12/2021 11:13, Victor Colombo wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 10 +++--- target/ppc/helper.h | 2 +- target/ppc/insn32.decode| 4 target/ppc/translate/vsx-impl.c.inc | 24

Re: [PATCH 0/2] block-backend: Retain permissions after migration

Am 25.11.2021 um 14:53 hat Hanna Reitz geschrieben: > Hi, > > Peng Liang has reported an issue regarding migration of raw images here: > https://lists.nongnu.org/archive/html/qemu-block/2021-11/msg00673.html > > It turns out that after migrating, all permissions are shared when they > weren’t

Re: [PATCH v4 10/11] MAINTAINERS: Add an entry for Xilinx Versal OSPI

On Wed, 1 Dec 2021 at 15:41, Francisco Iglesias wrote: > > List myself as maintainer for the Xilinx Versal OSPI controller. > > Signed-off-by: Francisco Iglesias > Reviewed-by: Edgar E. Iglesias > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v4 07/11] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model

On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias wrote: > > Connect the OSPI flash memory controller model (including the source and > destination DMA). > > Signed-off-by: Francisco Iglesias > Reviewed-by: Edgar E. Iglesias > --- > hw/arm/xlnx-versal.c | 88 >

Re: [PATCH v4 09/11] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI

On Wed, 1 Dec 2021 at 15:41, Francisco Iglesias wrote: > > Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory > controller. > > Signed-off-by: Francisco Iglesias > Reviewed-by: Edgar E. Iglesias > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v4 06/11] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller

On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias wrote: > > Add a model of Xilinx Versal's OSPI flash memory controller. > > Signed-off-by: Francisco Iglesias > +#define SZ_512MBIT (512 * 1024 * 1024) > +#define SZ_1GBIT (1024 * 1024 * 1024) > +#define SZ_2GBIT (2ULL * SZ_1GBIT) > +#define

Re: Redesign of QEMU startup & initial configuration

On Fri, Dec 10, 2021 at 04:26:20PM +0100, Markus Armbruster wrote: > > The existing binary provides bad CLI and limited QMP. > > Going from limited to good QMP involves reworking the startup code. I > believe that's easier in a new binary. > > Going from bad CLI to good CLI involves

Re: Redesign of QEMU startup & initial configuration

On 12/10/21 14:54, Markus Armbruster wrote: I want an open path to a single binary. Taking years to get there is fine. The single binary is a distraction in my opinion. Imagine instead of vl.c you have this in your second binary: /* * This copyright line means that at some point the below

Re: [PATCH v5 06/31] block/block-backend.c: assertions for block-backend

On 24.11.21 07:43, Emanuele Giuseppe Esposito wrote: All the global state (GS) API functions will check that qemu_in_main_thread() returns true. If not, it means that the safety of BQL cannot be guaranteed, and they need to be moved to I/O. Signed-off-by: Emanuele Giuseppe Esposito ---

Re: [PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)

On Fri, Dec 10, 2021 at 10:05 PM Cédric Le Goater wrote: > > On 12/10/21 09:30, Troy Lee wrote: > > AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory > > and io address. If guest machine try to access DPMCU memory, it will > > cause a fatal error. > > The Aspeed SoCs have

Re: [PATCH 1/2] target/riscv: Set the opcode in DisasContext

On 12/9/21 10:26 PM, Alistair Francis wrote: From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/translate.c | 2 ++ 1 file changed, 2 insertions(+) Reviewed-by: Richard Henderson r~

Re: Redesign of QEMU startup & initial configuration

Paolo Bonzini writes: > On 12/9/21 20:11, Daniel P. Berrangé wrote: >>> They still need to bootstrap a QMP monitor, and for that, CLI is fine >>> as long as it's simple and stable. > > I would go a step further and say that the QMP monitor socket should > be created by whoever invoked

[PATCH 0/4] target/ppc: Fix VSX instructions register access

Instructions xscvqpdp, xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using the wrong registers, which yields the wrong result when using them. This patch series fixes this issue by correcting the registers used. It also takes the opportunity to move these instructions to decodetree. Matheus

[PATCH 3/4] target/ppc: fix xscvqpdp register access

From: Matheus Ferst This instruction has VRT and VRB fields instead of T/TX and B/BX. Signed-off-by: Matheus Ferst --- target/ppc/translate/vsx-impl.c.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate/vsx-impl.c.inc

[PATCH 4/4] target/ppc: move xscvqpdp to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 10 +++--- target/ppc/helper.h | 2 +- target/ppc/insn32.decode| 4 target/ppc/translate/vsx-impl.c.inc | 24 +---

[PATCH 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree

Signed-off-by: Victor Colombo --- target/ppc/insn32.decode| 17 +--- target/ppc/translate/vsx-impl.c.inc | 30 + target/ppc/translate/vsx-ops.c.inc | 4 3 files changed, 40 insertions(+), 11 deletions(-) diff --git

[PATCH 1/4] target/ppc: Fix xs{max,min}[cj]dp to use VSX registers

PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using vector registers when they should be using VSX ones. This happens because the instructions are using GEN_VSX_HELPER_R3, which adds 32 to the register numbers, effectively making them vector registers. This patch fixes it by

[PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)

AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory and io address. If guest machine try to access DPMCU memory, it will cause a fatal error. Signed-off-by: Troy Lee --- hw/arm/aspeed_ast2600.c | 8 include/hw/arm/aspeed_soc.h | 2 ++ 2 files changed, 10

Re: [PATCH v4 04/11] hw/dma: Add the DMA control interface

On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias wrote: > > An option on real hardware when embedding a DMA engine into a peripheral > is to make the peripheral control the engine through a custom DMA control > (hardware) interface between the two. Software drivers in this scenario > configure and

Re: [PATCH v4 02/11] hw/arm/xlnx-versal: Connect Versal's PMC SLCR

On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias wrote: > > Connect Versal's PMC SLCR (system-level control registers) model. > > Signed-off-by: Francisco Iglesias > diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h > index 895ba12c61..729c093dfc 100644 > ---

Re: Redesign of QEMU startup & initial configuration

On 12/10/21 12:25, Daniel P. Berrangé wrote: I can't disagree with this. If we carry on trying to evolve vl.c incrementally we are doomed to be stuck with a horrible starstup process for enternity (or at least as long as I'll still be working as QEMU maintainer). ... and if you compare vl.c in

Re: [PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)

On 12/10/21 15:33, Troy Lee wrote: On Fri, Dec 10, 2021 at 10:05 PM Cédric Le Goater wrote: On 12/10/21 09:30, Troy Lee wrote: AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory and io address. If guest machine try to access DPMCU memory, it will cause a fatal error.

Re: [PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction

On 12/9/21 10:26 PM, Alistair Francis wrote: @@ -975,7 +975,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg = async ? env->mideleg :

Re: [PATCH v4 01/11] hw/misc: Add a model of Versal's PMC SLCR

On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias wrote: > > Add a model of Versal's PMC SLCR (system-level control registers). > > Signed-off-by: Francisco Iglesias > Signed-off-by: Edgar E. Iglesias > Acked-by: Edgar E. Iglesias > +static void xlnx_versal_pmc_iou_slcr_realize(DeviceState

Re: [PATCH 2/3] iotests/testrunner.py: move updating last_elapsed to run_tests

10.12.2021 17:25, Kevin Wolf wrote: Am 06.12.2021 um 18:59 hat John Snow geschrieben: On Fri, Dec 3, 2021 at 7:22 AM Vladimir Sementsov-Ogievskiy < vsement...@virtuozzo.com> wrote: We are going to use do_run_test() in multiprocessing environment, where we'll not be able to change original

Re: [PATCH 3/3] iotests: check: multiprocessing support

10.12.2021 17:36, Kevin Wolf wrote: Am 03.12.2021 um 13:22 hat Vladimir Sementsov-Ogievskiy geschrieben: Add -j parameter, to run tests in several jobs simultaneously. For realization - simply utilize multiprocessing.Pool class. Notes: 1. Of course, tests can't run simultaneously in same

Re: Redesign of QEMU startup & initial configuration

> On 10 Dec 2021, at 15:26, Daniel P. Berrangé wrote: > > On Fri, Dec 10, 2021 at 03:15:50PM +0100, Mark Burton wrote: >> >> >>> On 10 Dec 2021, at 12:25, Daniel P. Berrangé wrote: >>> >>> On Fri, Dec 10, 2021 at 09:34:41AM +0100, Paolo Bonzini wrote: On 12/9/21 20:11, Daniel P.

Re: [PATCH 1/3] iotests/testrunner.py: add doc string for run_test()

10.12.2021 17:12, Kevin Wolf wrote: Am 03.12.2021 um 13:22 hat Vladimir Sementsov-Ogievskiy geschrieben: We are going to modify these methods and will add more documentation in further commit. As a preparation add basic documentation. Signed-off-by: Vladimir Sementsov-Ogievskiy ---

Re: [PATCH v5 05/31] block-backend: special comments for blk_set/get_perm due to fuse

On 24.11.21 07:43, Emanuele Giuseppe Esposito wrote: Fuse logic can be classified as I/O, so there is no BQL held during its execution. And yet, it uses blk_{get/set}_perm functions, that are classified as BQL and clearly require the BQL lock. Since there is no easy solution for this, add a

Re: [PATCH 3/3] iotests: check: multiprocessing support

Am 03.12.2021 um 13:22 hat Vladimir Sementsov-Ogievskiy geschrieben: > Add -j parameter, to run tests in several jobs simultaneously. > For realization - simply utilize multiprocessing.Pool class. > > Notes: > > 1. Of course, tests can't run simultaneously in same TEST_DIR. So, >use

Re: Redesign of QEMU startup & initial configuration

On Fri, Dec 10, 2021 at 03:15:50PM +0100, Mark Burton wrote: > > > > On 10 Dec 2021, at 12:25, Daniel P. Berrangé wrote: > > > > On Fri, Dec 10, 2021 at 09:34:41AM +0100, Paolo Bonzini wrote: > >> On 12/9/21 20:11, Daniel P. Berrangé wrote: > They still need to bootstrap a QMP monitor,

Re: [PATCH 2/3] iotests/testrunner.py: move updating last_elapsed to run_tests

Am 06.12.2021 um 18:59 hat John Snow geschrieben: > On Fri, Dec 3, 2021 at 7:22 AM Vladimir Sementsov-Ogievskiy < > vsement...@virtuozzo.com> wrote: > > > We are going to use do_run_test() in multiprocessing environment, where > > we'll not be able to change original runner object. > > > >

Re: [PATCH v10 05/10] ACPI ERST: support for ACPI ERST feature

On Thu, Dec 9, 2021 at 11:28 PM Eric DeVolder wrote: > > This implements a PCI device for ACPI ERST. This implements the > non-NVRAM "mode" of operation for ERST as it is supported by > Linux and Windows. > > Signed-off-by: Eric DeVolder modulo some minor comments in V9, Reviewed-by: Ani Sinha

Re: [PATCH v5 04/31] include/sysemu/block-backend: split header into I/O and global state (GS) API

On 24.11.21 07:43, Emanuele Giuseppe Esposito wrote: Similarly to the previous patches, split block-backend.h in block-backend-io.h and block-backend-global-state.h In addition, remove "block/block.h" include as it seems it is not necessary anymore, together with "qemu/iov.h"

[PATCH 2/2] scsi/utils: pass host_status = SCSI_HOST_ERROR to guest kernel

For scsi_req_complete_failed() and when the req->bus->info->fail() is implemented, the virtio-scsi passes SCSI_HOST_ERROR to the guest kernel as VIRTIO_SCSI_S_FAILURE, while the pvscsi passes SCSI_HOST_ERROR to guest kernel as BTSTAT_HASOFTWARE. However, the

Re: Redesign of QEMU startup & initial configuration

> On 10 Dec 2021, at 12:25, Daniel P. Berrangé wrote: > > On Fri, Dec 10, 2021 at 09:34:41AM +0100, Paolo Bonzini wrote: >> On 12/9/21 20:11, Daniel P. Berrangé wrote: They still need to bootstrap a QMP monitor, and for that, CLI is fine as long as it's simple and stable. >>

[PATCH 1/2] scsi/scsi_bus: use host_status as parameter for scsi_sense_from_host_status()

The scsi_sense_from_host_status() always returns GOOD since req->host_status is 255 (-1) at this time. Change req->host_status to host_status so that scsi_sense_from_host_status() will be able to return the expected value. Fixes: f3126d65b393("scsi: move host_status handling into SCSI drivers")

[PATCH 0/2] scsi: to fix issue on passing host_status to the guest kernel

This patchset fixes the issue on passing 'host_status' to the guest kernel. The 1st patch fixes the erroneous usage of req->host_status. The 2nd patch is to pass the SCSI_HOST_ERROR to the guest kernel when the req->bus->info->fail() is not implemented. I do not add 'Fixes:' because I am not

Re: [PATCH 1/3] iotests/testrunner.py: add doc string for run_test()

Am 03.12.2021 um 13:22 hat Vladimir Sementsov-Ogievskiy geschrieben: > We are going to modify these methods and will add more documentation in > further commit. As a preparation add basic documentation. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > tests/qemu-iotests/testrunner.py |

Re: [PATCH v9 05/10] ACPI ERST: support for ACPI ERST feature

On Thu, Dec 9, 2021 at 11:24 PM Eric DeVolder wrote: > > Ani, inline responses below. eric > > On 12/9/21 00:29, Ani Sinha wrote: > > On Fri, Dec 3, 2021 at 12:39 AM Eric DeVolder > > wrote: > >> > >> This implements a PCI device for ACPI ERST. This implements the > >> non-NVRAM "mode" of

Re: [PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)

On 12/10/21 09:30, Troy Lee wrote: AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory and io address. If guest machine try to access DPMCU memory, it will cause a fatal error. The Aspeed SoCs have an "aspeed_soc.io" region for unimplemented devices but it's too small.

Re: [RFC] block-backend: prevent dangling BDS pointer in blk_drain()

Am 09.12.2021 um 15:23 hat Stefan Hajnoczi geschrieben: > The BlockBackend root child can change during bdrv_drained_begin() when > aio_poll() is invoked. In fact the BlockDriverState can reach refcnt 0 > and blk_drain() is left with a dangling BDS pointer. > > One example is

Re: Redesign of QEMU startup & initial configuration

Daniel P. Berrangé writes: > On Thu, Dec 02, 2021 at 07:57:38AM +0100, Markus Armbruster wrote: >> = Motivation = >> >> QEMU startup and initial configuration were designed many years ago for >> a much, much simpler QEMU. They have since changed beyond recognition >> to adapt to new needs.

Re: [PATCH v4 0/3] hw/block/fdc: Fix CVE-2021-20196

Am 24.11.2021 um 17:15 hat Philippe Mathieu-Daudé geschrieben: > Since v3: > - Preliminary extract blk_create_empty_drive() > - qtest checks qtest_check_clang_sanitizer() enabled > - qtest uses null-co:// driver instead of file > > Philippe Mathieu-Daudé (3): > hw/block/fdc: Extract

Re: [PATCH 5/8] standard-headers: Add virtio_video.h

Hi Peter, On Fri, 10 Dec 2021, Peter Maydell wrote: > On Thu, 9 Dec 2021 at 15:03, Peter Griffin wrote: > > > > Signed-off-by: Peter Griffin > > --- > > include/standard-headers/linux/virtio_video.h | 483 ++ > > 1 file changed, 483 insertions(+) > > create mode 100644

Re: [PATCH 2/2] iotests/149: Skip on unsupported ciphers

Am 17.11.2021 um 16:05 hat Hanna Reitz geschrieben: > On 17.11.21 16:01, Hanna Reitz wrote: > > Whenever qemu-img or qemu-io report that some cipher is unsupported, > > skip the whole test, because that is probably because qemu has been > > configured with the gnutls crypto backend. > > > > We

Re: [PATCH 5/8] standard-headers: Add virtio_video.h

Hi Michael, On Fri, 10 Dec 2021, Michael S. Tsirkin wrote: > On Thu, Dec 09, 2021 at 02:55:58PM +, Peter Griffin wrote: > > Signed-off-by: Peter Griffin > > --- > > include/standard-headers/linux/virtio_video.h | 483 ++ > > 1 file changed, 483 insertions(+) > > create

Re: [PATCH v2] Move the libssh setup from configure to meson.build

On 12/9/21 16:22, Richard W.M. Jones wrote: > On Thu, Dec 09, 2021 at 04:08:24PM +0100, Thomas Huth wrote: >> On 09/12/2021 15.55, Richard W.M. Jones wrote: >>> On Thu, Dec 09, 2021 at 03:48:01PM +0100, Thomas Huth wrote: It's easier to do this in meson.build now. Signed-off-by:

Re: [PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)

On 12/10/21 09:30, Troy Lee wrote: > AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory > and io address. If guest machine try to access DPMCU memory, it will > cause a fatal error. > > Signed-off-by: Troy Lee > --- > hw/arm/aspeed_ast2600.c | 8 >

Re: [PATCH 6/8] virtio_video: Add Fast Walsh-Hadamard Transform format

Hi Michael, On Fri, 10 Dec 2021, Michael S. Tsirkin wrote: > On Thu, Dec 09, 2021 at 02:55:59PM +, Peter Griffin wrote: > > Linux vicodec (Virtual Codec) test driver in Linux implements > > FWHT. FWHT was designed to be fast and simple and to have > > characteristics of other video codecs

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