[PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish r

[PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/csr.c | 156 + 1 file changed, 156 inser

[PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 + target/riscv

[PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c |

[PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c

[PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subseque

[PATCH v6 06/23] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alista

[PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin M

[PATCH v6 00/23] QEMU RISC-V AIA support

From: Anup Patel The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia/re

why tx_queue_size must be 256 for non-vhost-user tap nic

Hi, all: I tried to test the effort of nic queue's ring-size, but nic' tx vring-size is always 256. finally i found the code. could you tell why ? thanks - n->net_conf.tx_queue_size = MIN(virtio_net_max_tx_queue_size(n), n->net_conf.tx_queue_size);

Re: [PATCH] Add service recovery options for QGA on windows

Hi, On Mon, Nov 15, 2021 at 4:30 AM wrote: > From: shenjiatong > > Add default recovery options for QGA on windows. Previously, QGA > on windows will not try to restart service if it is down. This PS > add some default options for the first, second and other failures, > with an interval of 1min

Re: QEMU CAS

Thank you for the great response pointing out many details we have missed! The fixed constraints solved the optimization problem. I am going to see what I can do about the other issues, it will take a while. Best regards On 23/12/2021 20:24, Richard Henderson wrote: On 12/23/21 1:51 AM, Ja

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