On Wed, Jan 5, 2022 at 3:02 PM Michael S. Tsirkin wrote:
>
> On Wed, Jan 05, 2022 at 12:35:53PM +0800, Jason Wang wrote:
> > On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
> > >
> > > From: Longpeng
> > >
> > > To support generic vdpa deivce, we need add the following ioctls:
> > > -
On 1/4/22 11:22 PM, Philippe Mathieu-Daudé wrote:
On 27/12/21 15:27, zhenwei pi wrote:
A device of USB video class usually uses larger desc structure, so
use larger buffer to avoid failure.
Signed-off-by: zhenwei pi
---
hw/usb/desc.c | 15 ---
hw/usb/desc.h | 1 +
2 files
On 1/4/22 9:39 PM, Daniel P. Berrangé wrote:
On Mon, Dec 27, 2021 at 10:27:29PM +0800, zhenwei pi wrote:
1, The full picture of this patch set:
+-+ ++ +---+
|UVC(done)| |virtio(TODO)| |other HW device|
+-+
On Wed, Jan 05, 2022 at 12:35:53PM +0800, Jason Wang wrote:
> On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
> >
> > From: Longpeng
> >
> > To support generic vdpa deivce, we need add the following ioctls:
> > - GET_VECTORS_NUM: the count of vectors that supported
>
> Does this mean MSI
On 1/4/22 22:00, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signed-off-by: Matheus Ferst
---
在 2022/1/5 下午2:40, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) 写道:
-Original Message-
From: Jason Wang [mailto:jasow...@redhat.com]
Sent: Wednesday, January 5, 2022 12:36 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
Cc: Stefan Hajnoczi ; mst ;
> -Original Message-
> From: Jason Wang [mailto:jasow...@redhat.com]
> Sent: Wednesday, January 5, 2022 12:36 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: Stefan Hajnoczi ; mst ; Stefano
> Garzarella ; Cornelia Huck ; pbonzini
> ; Gonglei (Arei) ; Yechuan
On Tue, Jan 04, 2022 at 06:06:12PM +0800, Yan Zhao wrote:
> On Tue, Jan 04, 2022 at 05:10:08PM +0800, Chao Peng wrote:
> > On Tue, Jan 04, 2022 at 09:46:35AM +0800, Yan Zhao wrote:
> > > On Thu, Dec 23, 2021 at 08:30:09PM +0800, Chao Peng wrote:
> > > > When a page fault from the secondary page
On Wed, Jan 5, 2022 at 1:48 PM Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
>
>
>
> > -Original Message-
> > From: Jason Wang [mailto:jasow...@redhat.com]
> > Sent: Wednesday, January 5, 2022 12:38 PM
> > To: Longpeng (Mike, Cloud Infrastructure Service Product
On Tue, Jan 04, 2022 at 05:31:30PM +, Sean Christopherson wrote:
> On Fri, Dec 31, 2021, Chao Peng wrote:
> > On Fri, Dec 24, 2021 at 12:13:51PM +0800, Chao Peng wrote:
> > > On Thu, Dec 23, 2021 at 06:06:19PM +, Sean Christopherson wrote:
> > > > On Thu, Dec 23, 2021, Chao Peng wrote:
> >
On Tue, Jan 04, 2022 at 05:43:50PM +, Sean Christopherson wrote:
> On Fri, Dec 31, 2021, Chao Peng wrote:
> > On Tue, Dec 28, 2021 at 09:48:08PM +, Sean Christopherson wrote:
> > >KVM handles
> > > reverse engineering the memslot to get the offset and whatever else it
> > > needs.
> > >
On Tue, Jan 04, 2022 at 05:38:38PM +, Sean Christopherson wrote:
> On Fri, Dec 31, 2021, Chao Peng wrote:
> > On Fri, Dec 24, 2021 at 11:53:15AM +0800, Robert Hoo wrote:
> > > On Thu, 2021-12-23 at 20:29 +0800, Chao Peng wrote:
> > > > From: "Kirill A. Shutemov"
> > > >
> > > > +static void
> -Original Message-
> From: Jason Wang [mailto:jasow...@redhat.com]
> Sent: Wednesday, January 5, 2022 12:38 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: Stefan Hajnoczi ; mst ; Stefano
> Garzarella ; Cornelia Huck ; pbonzini
> ; Gonglei (Arei) ; Yechuan
Brown bag time: offset 0 from esp is the return address,
offset 4 is the first argument.
Fixes: d7478d4229f0 ("common-user: Fix tail calls to
safe_syscall_set_errno_tail")
Signed-off-by: Richard Henderson
---
Ho hum. I'm disappointed that our CI didn't catch this,
despite cross-i386-user.
On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> Add helpers to get the "Transitional PCI Device ID" and "class_id" of the
> deivce which is specificed by the "Virtio Device ID".
>
> These helpers will be used to build the generic vDPA device later.
>
> Signed-off-by:
On Wed, Jan 5, 2022 at 8:59 AM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> To support generic vdpa deivce, we need add the following ioctls:
> - GET_VECTORS_NUM: the count of vectors that supported
Does this mean MSI vectors? If yes, it looks like a layer violation:
vhost is transport
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the
existing support for scalable mode, we need to implement the following
missing parts:
1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation
with PASID
2) tag IOTLB with PASID
3) PASID cache and its flush
For
We introduce VTDBus structure as an intermediate step for searching
the address space. This works well with SID based matching/lookup. But
when we want to support SID plus PASID based address space lookup,
this intermediate steps turns out to be a burden. So the patch simply
drops the VTDBus
Hi All:
This series tries to introduce PASID support for Intel IOMMU. The work
is based on the previous scalabe mode support by implement the
ECAP_PASID. A new "x-pasid-mode" is introduced to enable this
mode. All internal vIOMMU codes were extended to support PASID instead
of the current
We use to warn on wrong rid2pasid entry. But this error could be
triggered by the guest and could happens during initialization. So
let's don't warn in this case.
Signed-off-by: Jason Wang
---
hw/i386/intel_iommu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
There seems to be difference in syscall and libc definition of these
methods and therefore musl does not implement them (1e21e78bf7). Call
syscall directly to ensure the behavior of the libc of user application,
not the libc that was used to build QEMU.
Signed-off-by: Tonis Tiigi
---
When scsalable mode is enabled, the passthrough more is not determined
by the context entry but PASID entry, so switch to use the logic of
vtd_dev_pt_enabled() to determine the passthrough mode in
vtd_do_iommu_translate().
Signed-off-by: Jason Wang
---
hw/i386/intel_iommu.c | 38
These syscalls are not exposed by glibc. The struct type need to be
redefined as it can't be included directly before
https://lkml.org/lkml/2020/5/28/810 .
sched_attr type can grow in future kernel versions. When client sends
values that QEMU does not understand it will return E2BIG with same
This patchset improves support for sched_* syscalls under user emulation.
The first commit adds support for sched_g/setattr that was previously not
implemented. These syscalls are not exposed by glibc. The struct type needs
to be redefined as it can't be included directly before
Anup Patel 於 2021年12月30日 週四 下午8:53寫道：
> From: Anup Patel
>
> The AIA specification defines IMSIC interface CSRs for easy access
> to the per-HART IMSIC registers without using indirect xiselect and
> xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
>
> Signed-off-by: Anup Patel
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
---
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
On Wed, Jan 5, 2022 at 5:32 AM Patrick Venture wrote:
>
>
>
> On Tue, Jan 4, 2022 at 1:18 PM Patrick Venture wrote:
>>
>> From: Peter Foley
>>
>> Match the other error handling in this function.
>
>
> Just noticed I didn't fix up the commit title here to match style. Should I
> do a PATCH
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- use 0 instead of GETPC()
target/riscv/debug.h | 4 +++
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
---
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 6 +
target/riscv/csr.c | 57
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 33 +
1 file changed,
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
---
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Bin Meng
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- use 0 instead of GETPC()
target/riscv/debug.h | 4 +++
target/riscv/cpu.c |
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
---
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 6 +
target/riscv/csr.c | 57
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 33 +
1 file changed, 33 insertions(+)
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented
On 1/4/22 4:40 PM, Richard Henderson wrote:
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into
staging (2022-01-04 07:23:27 -0800)
are available in the Git repository at:
https://gitlab.com
FreeBSD: Upgrade to 12.3 release
Note, since libtasn1 was fixed in 12.3 [*], this commit re-enables GnuTLS.
[*] https://gitlab.com/gnutls/libtasn1/-/merge_requests/71
Signed-off-by: Brad Smith
Tested-by: Thomas Huth
Reviewed-by: Warner Losh
---
.gitlab-ci.d/cirrus.yml | 5 +
From: Frank Chang
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1 file changed, 8 insertions(+), 4 deletions(-)
From: Frank Chang
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
From: Frank Chang
For vector widening and narrowing floating-point instructions, we should
use require_scale_rvf() instead of require_rvf() to check whether the
correspond RVF/RVD is enabled if either source or destination
floating-point operand is double-width of SEW. Otherwise, illegal
From: Frank Chang
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use
The GDB statck is as follows:
(gdb) bt
0 __lll_lock_wait (futex=futex@entry=0x56211df20360, private=0) at
lowlevellock.c:52
1 0x7f263caf20a3 in __GI___pthread_mutex_lock (mutex=0x56211df20360) at
../nptl/pthread_mutex_lock.c:80
2 0x56211a757364 in qemu_mutex_lock_impl
Upgrade OpenSBI from v0.9 to v1.0 and the pre-built bios images.
The v1.0 release includes the following commits:
ec5274b platform: implement K210 system reset
5487cf0 include: sbi: Simplify HSM state define names
8df1f9a lib: sbi: Use SBI_HSM_STATE_xyz defines instead of SBI_STATE_xyz defines
From: Longpeng
Implements the .get_features interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 4f97a7521b..32b3117c4b 100644
--- a/hw/virtio/vdpa-dev.c
+++
From: Longpeng
Implements the .set_status interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 100 ++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 32b3117c4b..64649bfb5a
From: Longpeng
The generic vDPA device doesn't support migration currently, so
mark it as unmigratable temporarily.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 64649bfb5a..0644aace22
From: Longpeng
Implements the .unrealize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 2d534d837a..4e4dd3d201 100644
---
From: Longpeng
Implements the .get_config and .set_config interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index 4e4dd3d201..4f97a7521b 100644
---
From: Longpeng
Add the infrastructure of vdpa-dev (the generic vDPA device), we
can add a generic vDPA device as follow:
-device vhost-vdpa-device-pci,vdpa-dev=/dev/vhost-vdpa-X
Signed-off-by: Longpeng
---
hw/virtio/Kconfig| 5
hw/virtio/meson.build| 2 ++
From: Longpeng
Implements the .realize interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev.c | 114 +++
include/hw/virtio/vdpa-dev.h | 8 +++
2 files changed, 122 insertions(+)
diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
index
From: Longpeng
Implements the .instance_init and the .class_init interface.
Signed-off-by: Longpeng
---
hw/virtio/vdpa-dev-pci.c | 80 +++-
hw/virtio/vdpa-dev.c | 68 +-
include/hw/virtio/vdpa-dev.h | 2 +
3 files
From: Longpeng
To support generic vdpa deivce, we need add the following ioctls:
- GET_VECTORS_NUM: the count of vectors that supported
- GET_CONFIG_SIZE: the size of the virtio config space
- GET_VQS_NUM: the count of virtqueues that exported
Signed-off-by: Longpeng
---
From: Longpeng
Add helpers to get the "Transitional PCI Device ID" and "class_id" of the
deivce which is specificed by the "Virtio Device ID".
These helpers will be used to build the generic vDPA device later.
Signed-off-by: Longpeng
---
hw/virtio/virtio-pci.c | 93
From: Longpeng
Hi guys,
This patchset tries to support the generic vDPA device, the previous
disscussion can be found here [1].
With the generic vDPA device, QEMU won't need to touch the device
types any more, such like vfio.
We can use the generic vDPA device as follow:
-device
Bitwise operations are easy to fold, because the operation is
identical regardless of element size. But add and sub need
extra element size info that is not currently propagated.
Fixes: 2f9f08ba43d
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/799
For the ABIs in which the syscall return register is not
also the first function argument register, move the errno
value into the correct place.
Fixes: a3310c0397e2 ("linux-user: Move syscall error detection into
safe_syscall_base")
Reported-by: Laurent Vivier
Tested-by: Laurent Vivier
From: Xiaoyao Li
Remove qemu_run_machine_init_done_notifiers() since no implementation
and user.
Fixes: f66dc8737c9 ("vl: move all generic initialization out of vl.c")
Signed-off-by: Xiaoyao Li
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220104024136.1433545-1-xiaoyao...@intel.com>
From: Philippe Mathieu-Daudé
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
In file included from ../linux-user/signal.c:33:
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into
staging (2022-01-04 07:23:27 -0800)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
On 1/4/22 11:04 AM, Richard Henderson wrote:
For the ABIs in which the syscall return register is not
also the first function argument register, move the errno
value into the correct place.
Fixes: a3310c0397e2
Reported-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
On 1/3/22 6:41 PM, Xiaoyao Li wrote:
Remove qemu_run_machine_init_done_notifiers() since no implementation
and user.
Signed-off-by: Xiaoyao Li
---
include/sysemu/sysemu.h | 1 -
1 file changed, 1 deletion(-)
Queued to tcg-next. Thanks.
r~
On Tue, Jan 4, 2022 at 4:25 PM Philippe Mathieu-Daudé
wrote:
> +Paolo for meson
>
> On 11/27/21 21:18, Warner Losh wrote:
> > Add a simple bsd-user smoke test for ensuring bsd-user is minimally
> > functional. This runs only when bsd-user has been configured. It adds a
> > simple execution of
On 1/4/22 1:50 PM, Philippe Mathieu-Daudé wrote:
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
In file included from ../linux-user/signal.c:33:
../linux-user/host/loongarch64/host-signal.h: In function
‘host_signal_write’:
On 1/4/22 19:06, Carwyn Ellis wrote:
> Debug output was always being sent to STDERR.
>
> This has been replaced with trace events.
>
> Signed-off-by: Carwyn Ellis
> ---
> hw/display/trace-events | 3 +++
> hw/display/vmware_vga.c | 22 ++
> 2 files changed, 13
+Paolo for meson
On 11/27/21 21:18, Warner Losh wrote:
> Add a simple bsd-user smoke test for ensuring bsd-user is minimally
> functional. This runs only when bsd-user has been configured. It adds a
> simple execution of 'hello world' type binaries for bsd-user. At the
> present these are tiny,
On 1/4/22 6:57 AM, Paolo Bonzini wrote:
The following changes since commit b5a3d8bc9146ba22a25116cb748c97341bf99737:
Merge tag 'pull-misc-20220103' of https://gitlab.com/rth7680/qemu into
staging (2022-01-03 09:34:41 -0800)
are available in the Git repository at:
On 1/4/22 2:48 PM, Taylor Simpson wrote:
Was Hexagon the only target that needed new ref files?
Yep. A curiosity of the guest libc, I guess.
r~
On 1/4/22 7:51 AM, Konrad Schwarz wrote:
+++ b/target/riscv/csr32-op-gdbserver.h
...
+++ b/target/riscv/csr64-op-gdbserver.h
There is a *lot* of overlap between these two files.
Why not add this data to the main csr_ops array?
That would put all the info for each csr in one place.
+
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, December 23, 2021 9:56 PM
> To: qemu-devel@nongnu.org
> Cc: alex.ben...@linaro.org; Taylor Simpson
> Subject: [PATCH 1/2] tests/tcg/multiarch: Read fp flags before printf
>
> We need to read the floating-point flags
Hi Eric,
On Tue, 04 Jan 2022 15:31:33 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 12/27/21 4:53 PM, Marc Zyngier wrote:
> > Hi Eric,
> >
> > Picking this up again after a stupidly long time...
> >
> > On Mon, 04 Oct 2021 13:00:21 +0100,
> > Eric Auger wrote:
> >> Hi Marc,
> >>
> >> On
On Wed, Jan 5, 2022 at 1:56 AM Konrad Schwarz
wrote:
>
> GDB target descriptions support typed registers;
> such that `info register X' displays not only the hex value of
> register `X', but also the individual bitfields the register
> comprises (if any), using textual labels if possible.
>
>
On 1/4/22 1:50 PM, Philippe Mathieu-Daudé wrote:
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
In file included from ../linux-user/signal.c:33:
../linux-user/host/loongarch64/host-signal.h: In function
‘host_signal_write’:
On 1/4/22 1:00 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signed-off-by: Matheus Ferst
---
On Wed, Jan 5, 2022 at 1:55 AM Konrad Schwarz
wrote:
>
> This is analog to the existing 'info mem' command and is implemented
> using the same machinery.
>
> Signed-off-by: Konrad Schwarz
Hello and thanks for the patches
> ---
> hmp-commands-info.hx | 16 +
>
On Tue, Jan 4, 2022 at 4:56 PM Jim Shu wrote:
>
> HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
> register, but QEMU emulation supports low part access now. Enhance QEMU
> emulation to support high 32-bit access.
>
> Also, permit 4/8-byte valid access in PDMA as we have verified
When building using GCC 8.3.0 on loongarch64 (Loongnix) we get:
In file included from ../linux-user/signal.c:33:
../linux-user/host/loongarch64/host-signal.h: In function ‘host_signal_write’:
../linux-user/host/loongarch64/host-signal.h:57:9: error: a label can only be
part of a statement
On Wed, Dec 29, 2021 at 12:15 PM wrote:
>
> From: Frank Chang
>
> Vector widening floating-point instructions should use
> require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
> enabled.
Missing Signed off by line
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc |
Cc'ing Daniel
On 4/1/22 22:18, Patrick Venture wrote:
From: Peter Foley
Match the other error handling in this function.
Fixes: e7b347d0bf6 ("net: detect errors from probing vnet hdr flag for
TAP devices")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Foley
---
On Tue, Jan 4, 2022 at 1:18 PM Patrick Venture wrote:
> From: Peter Foley
>
> Match the other error handling in this function.
>
Just noticed I didn't fix up the commit title here to match style. Should
I do a PATCH RESEND or a new patch, or can you add the "net/tap: " to the
title before
From: Peter Foley
Match the other error handling in this function.
Signed-off-by: Peter Foley
---
net/tap.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/tap.c b/net/tap.c
index f716be3e3f..c5cbeaa7a2 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -900,6 +900,7 @@ int net_init_tap(const
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signed-off-by: Matheus Ferst
---
linux-user/ppc/cpu_loop.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Matheus Ferst
Now that linux-user delivers the signal on tw, we can change
signal_save_restore_xer to use SIGTRAP instead of SIGILL.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
tests/tcg/ppc64le/signal_save_restore_xer.c | 8
From: Matheus Ferst
In the review of 66c6b40aba1, Richard Henderson suggested[1] using
"trap" instead of ".long 0x0" to generate the signal to test XER
save/restore behavior. However, linux-user aborts when a trap
exception is raised, so we kept the patch with SIGILL.
This patch series is a
On 1/4/22 7:51 AM, Konrad Schwarz wrote:
static const int dump_csrs[] = {
+
+# if 0
+CSR_USTATUS,
+CSR_UIE,
+CSR_UTVEC,
Adding huge sections of #if 0 code is not acceptable.
r~
Fabiano Rosas writes:
> We currently clear MSR_LE when copying bits from env->msr to
> new_msr. However, for CPUs that do not have LPCR_ILE we always set
> new_msr[LE] according to env->msr[LE]. And for CPUs that do have ILE
> support we need to check LPCR/HID0 anyway, so there's no need to
On 1/4/22 10:31 AM, Alex Bennée wrote:
+docker-image-gentoo-loongarch64-cross:
$(DOCKER_FILES_DIR)/gentoo-loongarch64-cross.docker
+ $(if $(NOCACHE),
\
+ $(call quiet-command,
Le 04/01/2022 à 20:04, Richard Henderson a écrit :
For the ABIs in which the syscall return register is not
also the first function argument register, move the errno
value into the correct place.
Fixes: a3310c0397e2
Reported-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
Richard Henderson writes:
> We didn't read the fp flags early enough, so we got whatever
> came out of the guest printf. With careful review of the
> hexagon output, we would have seen this long ago.
Queued to testing/next, thanks.
--
Alex Bennée
On 1/4/22 3:32 AM, Alex Bennée wrote:
The pgb_find_hole function goes to the trouble of taking account of
both mmap_min_addr and any offset we've applied to decide the starting
address of a potential hole. This is especially important for
emulating 32bit ARM in a 32bit build as we have applied
On 1/4/22 07:32, Alex Bennée wrote:
Daniel Henrique Barboza writes:
On 1/3/22 12:07, Alex Bennée wrote:
Daniel Henrique Barboza writes:
On 12/23/21 00:01, Richard Henderson wrote:
In contrast to Daniel's version, the code stays in power8-pmu.c,
but is better organized to not take so
WANG Xuerui writes:
> Normally this would be based on qemu/debian10 or qemu/ubuntu2004, but
> after a week-long struggle, I still cannot build stage2 gcc with the
> known-good LoongArch toolchain sources, so I chose the least-resistance
> path with Gentoo as base image. As this image is not
On 1/3/22 05:24, Cédric Le Goater wrote:
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
When creating a pnv_phb3_root_port using the command line, the first
root port is created successfully, but the second fails with the
following error:
qemu-system-ppc64: -device
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