On Jan 26 18:11, Lukasz Maniak wrote:
> From: Łukasz Gieryk
>
> An NVMe device with SR-IOV capability calculates the BAR size
> differently for PF and VF, so it makes sense to extract the common code
> to a separate function.
>
> Signed-off-by: Łukasz Gieryk
> ---
> hw/nvme/ctrl.c | 45
On Jan 26 18:11, Lukasz Maniak wrote:
> From: Łukasz Gieryk
>
> This patch updates the initialization place for the AER queue, so it’s
> initialized once, at controller initialization, and not every time
> controller is enabled.
>
> While the original version works for a non-SR-IOV device, as
On Jan 26 18:11, Lukasz Maniak wrote:
> Changes since v3:
> - Addressed comments to review on pcie: Add support for Single Root I/O
> Virtualization (SR/IOV)
> - Fixed issues reported by checkpatch.pl
>
> Knut Omang (2):
> pcie: Add support for Single Root I/O Virtualization (SR/IOV)
>
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+for (int dw = 1; dw >= 0; dw--) {
+get_avr64(vrb, a->vrb, dw);
+for (; in >= 0; in -= a->n, out--) {
+if (in > out) {
+tcg_gen_shri_i64(tmp, vrb, in - out);
+} else {
+
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+#define VSTRI(NAME, ELEM, NUM_ELEMS, LEFT) \
+void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *b,\
+ target_ulong rc) \
+{
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 8
target/ppc/translate/vmx-impl.c.inc | 32 +
2 files changed, 40 insertions(+)
Reviewed-by: Richard
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vcmpsq: Vector Compare Signed Quadword
vcmpuq: Vector Compare Unsigned Quadword
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 6
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 2 ++
target/ppc/translate/vmx-impl.c.inc | 56 +
2 files changed, 58 insertions(+)
diff --git
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+get_avr64(t0, a->vra, true);
+get_avr64(t1, a->vrb, true);
+tcg_gen_brcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t0, t1, l1);
+tcg_gen_brcond_i64(sign ? TCG_COND_LT : TCG_COND_LTU, t0, t1, l2);
+
+get_avr64(t0, a->vra,
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vcmpequq Vector Compare Equal Quadword
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 43
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+TCGv_vec t0, t1, zero;
+
+t0 = tcg_temp_new_vec_matching(t);
+t1 = tcg_temp_new_vec_matching(t);
+zero = tcg_constant_vec_matching(t, vece,
This patchset implements RISC-V Float-Point in Integer Registers
extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin
extension.
Specification:
https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf
The port is available here:
-- update extension check REQUIRE_ZDINX_OR_D
-- update double float point register read/write
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvd.c.inc | 285 +---
- update extension check REQUIRE_ZHINX_OR_ZFH and
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
- update half float point register read/write
- disable nanbox_h check
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 55371b1aa5..ddda4906ff
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 6 +-
target/riscv/csr.c| 25 -
target/riscv/translate.c | 4
3 files changed, 29 insertions(+), 6
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 12
target/riscv/cpu.h | 4
2 files changed, 16 insertions(+)
diff --git a/target/riscv/cpu.c
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 89 +++
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+static void do_vcmp_rc(int vrt)
+{
+TCGv_i64 t0, t1;
+
+t0 = tcg_temp_new_i64();
+t1 = tcg_temp_new_i64();
+
+get_avr64(t0, vrt, true);
+tcg_gen_ctpop_i64(t1, t0);
+get_avr64(t0, vrt, false);
+
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: Lucas Coutinho
Signed-off-by: Lucas Coutinho
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 18 ++
2 files changed, 19 insertions(+)
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: Lucas Coutinho
Move the following instructions to decodetree:
vextsb2w: Vector Extend Sign Byte To Word
vextsh2w: Vector Extend Sign Halfword To Word
vextsb2d: Vector Extend Sign Byte To Doubleword
vextsh2d: Vector Extend Sign
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, February 10, 2022 7:03 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: f4...@amsat.org; a...@rev.ng; Brian Cain ; Michael
> Lambert
> Subject: Re: [PATCH v2 06/12] Hexagon (tests/tcg/hexagon) test instructions
>
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Based on [1] by Lijun Pan, which was never merged
into master.
[1]:https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+/*
+ * Discard lower 64-bits, leaving the carry into bit 64.
+ * Then sum the higher 64-bit elements.
+ */
+tcg_gen_mov_i64(tmp1, tmp0);
+get_avr64(tmp0, a->rc, true);
+tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero,
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+static void do_vx_vmulhu_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+TCGv_vec a1, b1, mask, w, k;
+unsigned bits;
+bits = (vece == MO_32) ? 16 : 32;
+
+a1 = tcg_temp_new_vec_matching(t);
+b1 =
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
From: "Lucas Mateus Castro (alqotel)"
Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to
decodetree
Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h | 8
On 2/10/22 23:34, matheus.fe...@eldorado.org.br wrote:
+void helper_VMULESD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+muls64(>VsrD(1), >VsrD(0), a->VsrSD(0), b->VsrSD(0));
+}
+void helper_VMULOSD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+muls64(>VsrD(1), >VsrD(0), a->VsrSD(1),
On 2/11/22 14:30, Taylor Simpson wrote:
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson
r~
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 58a0d3870b..e3efbb2303 100644
--- a/target/hexagon/cpu.h
+++
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, February 10, 2022 7:22 PM
> To: Taylor Simpson ; Philippe Mathieu-Daudé
> ; qemu-devel@nongnu.org
> Cc: Paolo Bonzini ; Thomas Huth
>
> Subject: Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU
>
> On
在 2022/2/11 上午12:34, Christoph Muellner 写道:
The RISC-V base cache management operation ISA extension has been
ratified [1]. This patch adds support for the defined instructions.
The cmo.prefetch instructions are nops for QEMU (no emulation of the memory
hierarchy, no illegal instructions, no
A mostly generic test for unaligned access raising SIGBUS.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tests/tcg/multiarch/sigbus.c | 68
1 file changed, 68 insertions(+)
create mode 100644 tests/tcg/multiarch/sigbus.c
diff --git
Due to mapping changes, we now rarely place the code_gen_buffer
near the main executable. Which means that direct calls will
now rarely be in range.
So, always use indirect calls for tail calls, which allows us to
avoid clobbering %o7, and therefore we need not save and restore it.
Reviewed-by:
When BH is constant, it is constrained to 11 bits for use in MOVCC.
For the cases in which we must load the constant BH into a register,
we do not need the full logic of tcg_out_movi; we can use the simpler
function for emitting a 13 bit constant.
This eliminates the only case in which TCG_REG_T2
Since 7ecd02a06f8, if patch_reloc fails we restart translation
with a smaller TB. SPARC had its function signature changed,
but not the logic. Replace assert with return false.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
This will allow us to control exactly what scratch register is
used for loading the constant.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.c.inc | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git
Hi, Mark
On 02/05/2022 09:32 PM, Mark Cave-Ayland wrote:
> On 28/01/2022 03:40, Xiaojuan Yang wrote:
>
>> This series patch add softmmu support for LoongArch.
>> The latest kernel:
>>* https://github.com/loongson/linux/tree/loongarch-next
>> The latest uefi:
>>*
Support for unaligned accesses is difficult for pre-v6 hosts.
While debian still builds for armv4, we cannot use a compile
time test, so test the architecture at runtime and error out.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 5 +
1 file
Handle 32-bit constants with a separate function, so that
tcg_out_movi_int does not need to recurse. This slightly
rearranges the order of tests for small constants, but
produces the same output.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.c.inc | 36
We can use the routines just added for user-only to emit
unaligned accesses in softmmu mode too.
Tested-by: Jiaxun Yang
Reviewed-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 91 ++-
1
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 2 --
tcg/riscv/tcg-target.c.inc | 63 --
2 files changed, 61 insertions(+), 4 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index ef78b99e98..11c9b3e4f4 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 2 --
tcg/s390x/tcg-target.c.inc | 59 --
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 -
tcg/arm/tcg-target.c.inc | 83 +++-
2 files changed, 81 insertions(+), 4 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.c.inc | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 213aba4be6..e78945d153 100644
--- a/tcg/sparc/tcg-target.c.inc
+++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 -
tcg/aarch64/tcg-target.c.inc | 91 +---
2 files changed, 74 insertions(+), 19 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index
Reserve a register for the guest_base using aarch64 for reference.
By doing so, we do not have to recompute it for every memory load.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 39 ---
1 file changed, 28
This is kinda sorta the opposite of the other tcg hosts, where
we get (normal) alignment checks for free with host SIGBUS and
need to add code to support unaligned accesses.
This inline code expansion is somewhat large, but it takes quite
a few instructions to make a function call to a helper
This is now always true, since we require armv6.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 3 +--
tcg/arm/tcg-target.c.inc | 35 ++-
2 files changed, 7 insertions(+), 31 deletions(-)
diff --git
We will shortly allow the use of unaligned memory accesses,
and these require proper alignment. Use get_alignment_bits
to verify and remove USING_SOFTMMU.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 23 ---
1 file changed, 8
We had code for checking for 13 and 21-bit shifted constants,
but we can do better and allow 32-bit shifted constants.
This is still 2 insns shorter than the full 64-bit sequence.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 -
tcg/i386/tcg-target.c.inc | 103 --
2 files changed, 98 insertions(+), 7 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index
From: Idan Horowitz
Instead of taking the lock of the cpu work list in order to check if it's
empty, we can just read the head pointer atomically. This decreases
cpu_work_list_empty's share from 5% to 1.3% in a profile of icount-enabled
aarch64-softmmu.
Signed-off-by: Idan Horowitz
Message-Id:
>From armv6, the architecture supports unaligned accesses.
All we need to do is perform the correct alignment check
in tcg_out_tlb_read.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 41
1 file changed, 21
This is kinda sorta the opposite of the other tcg hosts, where
we get (normal) alignment checks for free with host SIGBUS and
need to add code to support unaligned accesses.
Fortunately, the ISA contains pairs of instructions that are
used to implement unaligned memory accesses. Use them.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 336af5945a..fe92b5d084 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -292,11 +292,11 @@ static
This is now always true, since we require armv6.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 1 -
tcg/arm/tcg-target.c.inc | 192 ++-
2 files changed, 27 insertions(+), 166 deletions(-)
diff --git
From: WANG Xuerui
Apparently we were left behind; just renaming MO_Q to MO_UQ is enough.
Fixes: fc313c64345453c7 ("exec/memop: Adding signedness to quad definitions")
Signed-off-by: WANG Xuerui
Message-Id: <20220206162106.1092364-1-i.q...@xen0n.name>
Signed-off-by: Richard Henderson
---
From: WANG Xuerui
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
Message-Id: <20220106134238.3936163-1-...@xen0n.name>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 -
tcg/loongarch64/tcg-target.c.inc | 71 +++-
2 files
Sparc64 is unique on linux in *not* passing ucontext_t as
the third argument to a SA_SIGINFO handler. It passes the
old struct sigcontext instead.
Set both pc and npc in host_signal_set_pc.
Fixes: 8b5bd461935b ("linux-user/host/sparc: Populate host_signal.h")
Reviewed-by: Peter Maydell
Do not directly access ucontext_t as the third signal parameter.
This is preparation for a sparc64 fix.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/include/host/aarch64/host-signal.h | 13 -
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 -
tcg/ppc/tcg-target.c.inc | 98
2 files changed, 90 insertions(+), 10 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index
From: Idan Horowitz
When the length of the range is large enough, clearing the whole cache is
faster than iterating over the (possibly extremely large) set of pages
contained in the range.
This mimics the pre-existing similar optimization done on the flush of the
tlb itself.
Signed-off-by:
Do not directly access the uc_sigmask member.
This is preparation for a sparc64 fix.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/include/host/aarch64/host-signal.h | 5 +
linux-user/include/host/alpha/host-signal.h|
We do not support sparc32 as a host, so there's no point in
sparc64 redirecting to sparc.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/include/host/sparc/host-signal.h | 71 ---
linux-user/include/host/sparc64/host-signal.h | 64
Use the "retl" instead of "ret" instruction alias, since we
do not allocate a register window in this function.
Fix the offset to the first stacked parameter, which lies
beyond the register window save area.
Fixes: 95c021dac835 ("linux-user/host/sparc64: Add safe-syscall.inc.S")
Signed-off-by:
The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220208'
into staging (2022-02-08 11:40:08 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git
From: Pavel Dovgalyuk
Commit aff0e204cb1f1c036a496c94c15f5dfafcd9b4b4 introduced CF_NOIRQ usage,
but one case was forgotten. Record/replay uses one special TB which is not
really executed, but used to cause a correct exception in replay mode.
This patch adds CF_NOIRQ flag for such block.
On 2/11/22 04:35, Taylor Simpson wrote:
-#define HEXAGON_CPU_CLASS(klass) \
-OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU)
-#define HEXAGON_CPU(obj) \
-OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU)
-#define HEXAGON_CPU_GET_CLASS(obj) \
-
On 2/10/22 13:15, Taylor Simpson wrote:
On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to
c4 inside a packet with reads from predicate registers, the predicate
reads should get the old values.
Test case added to tests/tcg/hexagon/preg_alias.c
Co-authored-by: Michael
On 2/10/22 13:15, Taylor Simpson wrote:
Fix typo that checked for 32 bit nan instead of 64 bit
Test case added in tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
---
target/hexagon/op_helper.c | 2 +-
tests/tcg/hexagon/usr.c| 4
2 files changed, 5 insertions(+), 1
On 2/10/22 13:15, Taylor Simpson wrote:
Add a test that sets USR multiple times in a packet
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/overflow.c | 61 +++-
1 file changed, 60 insertions(+), 1 deletion(-)
Acked-by: Richard Henderson
r~
On 2/10/22 13:15, Taylor Simpson wrote:
Tests to confirm floating point instructions are properly
setting exception bits in USR
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/usr.c | 339
1 file changed, 339 insertions(+)
Acked-by: Richard
On 2/10/22 13:15, Taylor Simpson wrote:
+#define CLEAR_USRBITS \
+"r2 = usr\n\t" \
+"r2 = clrbit(r2, #0)\n\t" \
+"r2 = clrbit(r2, #1)\n\t" \
+"r2 = clrbit(r2, #2)\n\t" \
+"r2 = clrbit(r2, #3)\n\t" \
+"r2 = clrbit(r2, #4)\n\t" \
+"r2 = clrbit(r2, #5)\n\t" \
+"usr =
> On Feb 10, 2022, at 7:26 PM, Michael S. Tsirkin wrote:
>
> On Thu, Feb 10, 2022 at 04:49:33PM -0700, Alex Williamson wrote:
>> On Thu, 10 Feb 2022 18:28:56 -0500
>> "Michael S. Tsirkin" wrote:
>>
>>> On Thu, Feb 10, 2022 at 04:17:34PM -0700, Alex Williamson wrote:
On Thu, 10 Feb 2022
On 2/10/22 13:15, Taylor Simpson wrote:
The float??_minnum implementation differs from Hexagon for SNaN,
it returns NaN, but Hexagon returns the other input. So, we add
checks for NaN before calling it.
test cases added in a subsequent patch to more extensively test USR bits
Signed-off-by:
On 2/10/22 13:15, Taylor Simpson wrote:
The arch_sf_recip_common function was calling float32_getexp which
adjusts for denorm, but the we actually need the raw exponent bits.
This function is called from 3 instructions
sfrecipa
sffixupn
sffixupd
Test cases added to
On 2/10/22 13:15, Taylor Simpson wrote:
Instead of checking for nan arguments, use float??_unordered_quiet
test cases added in a subsequent patch to more extensively test USR bits
Signed-off-by: Taylor Simpson
---
target/hexagon/op_helper.c | 6 ++
1 file changed, 2 insertions(+), 4
On 2/10/22 13:15, Taylor Simpson wrote:
Two tests added to tests/tcg/hexagon/hvx_misc.c
v21.uw = vadd(v11.uw, v10.uw):sat
v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 4 +-
tests/tcg/hexagon/hvx_misc.c | 71
On 2/10/22 13:15, Taylor Simpson wrote:
From: Michael Lambert
Versions V3 and earlier should treat the "K_const" and "length" values
as unsigned.
Modified circ_test_v3() in tests/tcg/hexagon/circ.c to reproduce the bug
Signed-off-by: Michael Lambert
Signed-off-by: Taylor Simpson
---
On Thu, Feb 10, 2022 at 04:49:33PM -0700, Alex Williamson wrote:
> On Thu, 10 Feb 2022 18:28:56 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Thu, Feb 10, 2022 at 04:17:34PM -0700, Alex Williamson wrote:
> > > On Thu, 10 Feb 2022 22:23:01 +
> > > Jag Raman wrote:
> > >
> > > > > On Feb
> On Feb 10, 2022, at 6:17 PM, Alex Williamson
> wrote:
>
> On Thu, 10 Feb 2022 22:23:01 +
> Jag Raman wrote:
>
>>> On Feb 10, 2022, at 3:02 AM, Michael S. Tsirkin wrote:
>>>
>>> On Thu, Feb 10, 2022 at 12:08:27AM +, Jag Raman wrote:
Thanks for the explanation, Alex.
On Thu, 10 Feb 2022 18:28:56 -0500
"Michael S. Tsirkin" wrote:
> On Thu, Feb 10, 2022 at 04:17:34PM -0700, Alex Williamson wrote:
> > On Thu, 10 Feb 2022 22:23:01 +
> > Jag Raman wrote:
> >
> > > > On Feb 10, 2022, at 3:02 AM, Michael S. Tsirkin wrote:
> > > >
> > > > On Thu, Feb 10,
> On Feb 10, 2022, at 5:53 PM, Michael S. Tsirkin wrote:
>
> On Thu, Feb 10, 2022 at 10:23:01PM +, Jag Raman wrote:
>>
>>
>>> On Feb 10, 2022, at 3:02 AM, Michael S. Tsirkin wrote:
>>>
>>> On Thu, Feb 10, 2022 at 12:08:27AM +, Jag Raman wrote:
> On Feb 2, 2022, at
On Thu, Feb 10, 2022 at 04:17:34PM -0700, Alex Williamson wrote:
> On Thu, 10 Feb 2022 22:23:01 +
> Jag Raman wrote:
>
> > > On Feb 10, 2022, at 3:02 AM, Michael S. Tsirkin wrote:
> > >
> > > On Thu, Feb 10, 2022 at 12:08:27AM +, Jag Raman wrote:
> > >>
> > >> Thanks for the
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops-icount.c | 1 +
accel/tcg/tcg-accel-ops-mttcg.c | 1 +
accel/tcg/tcg-accel-ops-rr.c | 1 +
accel/tcg/tcg-accel-ops.c| 1 +
4 files changed, 4 insertions(+)
What
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
preexit_cleanup() is not Linux specific, move it to common-user/.
Signed-off-by: Philippe Mathieu-Daudé
---
{linux-user => common-user}/exit.c | 0
common-user/meson.build| 1 +
linux-user/meson.build | 1 -
3 files
On Thu, 10 Feb 2022 22:23:01 +
Jag Raman wrote:
> > On Feb 10, 2022, at 3:02 AM, Michael S. Tsirkin wrote:
> >
> > On Thu, Feb 10, 2022 at 12:08:27AM +, Jag Raman wrote:
> >>
> >> Thanks for the explanation, Alex. Thanks to everyone else in the thread who
> >> helped to clarify this
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
Move user-mode specific prototypes from "exec/exec-all.h"
to "user/cpu-target.h".
Signed-off-by: Philippe Mathieu-Daudé
---
Why a new cpu-target.h, and what is it supposed to mean? What else is going in there? It
all looks cpu_loop related so
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
env_cpu() is declared in "exec/cpu-all.h".
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/cpu_loop-common.h | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
To reduce the inclusion of "hw/core/cpu.h", extract
MMUAccessType to its own "exec/cpu-tlb.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
Not keen on the name, unless you plan to put something else in there.
r~
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
qemu_plugin_user_exit() is declared in "qemu/plugin.h".
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/exit.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
Avoid spreading the headers in multiple directories,
unify exec/user/ and user/.
Signed-off-by: Philippe Mathieu-Daudé
---
bsd-user/qemu.h | 4 ++--
include/exec/cpu-all.h | 2 +-
include/{exec =>
On 2/10/22 10:00, Philippe Mathieu-Daudé wrote:
common-user/ has been added in commit bbf15aaf7c
("common-user: Move safe-syscall.* from linux-user").
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/coverity-scan/COMPONENTS.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 2/9/22 07:31, matheus.fe...@eldorado.org.br wrote:
The second patch addresses differences in the output of float_madds.c.
The __builtin_fmaf used in this test emits fmadds with GCC and xsmaddasp
with LLVM. The first insn had rounding errors fixed in
d04ca895dc7f ("target/ppc: Add helpers for
On 2/9/22 07:31, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Change VSX Scalar Multiply-Add/Subtract Type-A/M Single Precision
helpers to use float64r32_muladd. This method should correctly handle
all rounding modes, so the workaround for float_round_nearest_even can
be dropped.
On 2/9/22 04:16, Peter Maydell wrote:
In the armv7m object, handle clock inputs that aren't connected.
This is always an error for 'cpuclk'. For 'refclk' it is OK for this
to be disconnected, but we need to handle it by not trying to connect
a sourceless-clock to the systick device.
This fixes
On Thu, Feb 10, 2022 at 10:23:01PM +, Jag Raman wrote:
>
>
> > On Feb 10, 2022, at 3:02 AM, Michael S. Tsirkin wrote:
> >
> > On Thu, Feb 10, 2022 at 12:08:27AM +, Jag Raman wrote:
> >>
> >>
> >>> On Feb 2, 2022, at 12:34 AM, Alex Williamson
> >>> wrote:
> >>>
> >>> On Wed, 2 Feb
> On Feb 10, 2022, at 3:02 AM, Michael S. Tsirkin wrote:
>
> On Thu, Feb 10, 2022 at 12:08:27AM +, Jag Raman wrote:
>>
>>
>>> On Feb 2, 2022, at 12:34 AM, Alex Williamson
>>> wrote:
>>>
>>> On Wed, 2 Feb 2022 01:13:22 +
>>> Jag Raman wrote:
>>>
> On Feb 1, 2022, at 5:47 PM,
On 2/11/22 03:48, Philipp Tomsich wrote:
-lq . 010 . 000 @i
+{
+ [
+ # *** RV32 Zicbom Standard Extension ***
+ cbo_clean 000 1 . 010 0 000 @sfence_vm
+ cbo_flush 000 00010 . 010 0 000
With these interfaces missing, TFM would delegate peripherals 0, 1,
2, 3 and 8, and qemu would ignore the delegation of interface 8, as
it thought interface 4 was eth & USB.
This patch corrects this behavior and allows TFM to delegate the
eth & USB peripheral to NS mode.
Signed-off-by: Jimmy
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