Hi, any comments on this patch or patchset?
Currently, read-only instruction to access Seed CSR is checked as a
special case in helper_csrr as suggested in
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00146.html.
(The new version for that patch is in
The 04/05/2022 16:12, Cédric Le Goater wrote:
Hi Cedric,
> Hello Jamin,
>
> On 4/1/22 10:38, Jamin Lin wrote:
> > Changes from v5:
> > - remove TYPE_ASPEED_MINIBMC_MACHINE and ASPEED_MINIBMC_MACHINE
> > - remove ast1030_machine_instance_init function
> >
> > Changes from v4:
> > - drop the
The 04/01/2022 13:25, Cédric Le Goater wrote:
Hi Cedric,
> Hello Jamin,
>
> On 4/1/22 11:23, Jamin Lin wrote:
> > Hi Cedric, Joel and Andrew
> > First all, thanks for all your kindly support and review. We are so
> > glad that QEMU v7.1 will support AST1030 model.
>
> QEMU 7.1 is for after the
On 4/10/2022 5:06 AM, Peter Maydell wrote:
On Sun, 10 Apr 2022 at 05:51, Brad Smith wrote:
On 4/8/2022 12:47 PM, Thomas Huth wrote:
QEMU 7.1 won't support Ubuntu 18.04 anymore, so the last big important
distro that did not have a pre-packaged libslirp has been dismissed.
All other major
Good point; however per the SBSA specification, DEN0029F, there's the
PE architecture requirement at
each level from 1 to 7, so now I am wondering whether supporting
cortex-a57 and a72 are good enough to
set up a fully SBSA level 7 compliant "board" in QMEU. Also, the 'max'
is there, but does not
From: Corentin LABBE
The Allwinner A10 has a cryptographic offloader device which
could be easily emulated.
The emulated device is tested with Linux only as any of BSD does not
support it.
Signed-off-by: Corentin LABBE
---
MAINTAINERS| 8 +
Hi Daniel,
On 3/25/22 11:33 AM, Daniel P. Berrangé wrote:
> On Fri, Mar 18, 2022 at 02:34:29PM +0100, Claudio Fontana wrote:
>> On 3/17/22 4:03 PM, Dr. David Alan Gilbert wrote:
>>> * Claudio Fontana (cfont...@suse.de) wrote:
On 3/17/22 2:41 PM, Claudio Fontana wrote:
> On 3/17/22 11:25
Minor change to make fullscreen mode in the Cocoa UI a little more
convenient.
The menu bar is now made visible when the mouse is released (ungrabbed)
making it accessible without having to leave fullscreen mode. Grabbing
the mouse hides the menu.
Incorporates changes in response to feedback
The menu bar is only accessible when the Cocoa UI is windowed. In order
to allow the menu bar to be accessible in fullscreen mode, this change
makes the menu visible when the mouse is ungrabbed.
When the mouse is grabbed the menu is hidden again.
Incorporates changes in response to review
Thanks, taking a look now and will push up another patch once I’ve tested the
changes.
Regards
Carwyn
> On 18 Feb 2022, at 18:42, Akihiko Odaki wrote:
>
> On 2022/01/03 20:45, Carwyn Ellis wrote:
>> The menu bar is only accessible when the Cocoa UI is windowed. In order
>> to allow the menu
ping
https://patchew.org/QEMU/20220206183956.10694-1-carwynel...@gmail.com/20220206183956.10694-3-carwynel...@gmail.com/
Originally submitted as one of two patches, the first patch to use trace events
has been merged, however the patch that fixes garbled output hasn’t been
reviewed yet.
Do
On 07/04/2022 8:55, Markus Armbruster wrote:
> Cole Robinson writes:
>
>> On 2/28/22 4:39 AM, Dov Murik wrote:
>>>
>>>
>>> On 28/02/2022 11:31, Daniel P. Berrangé wrote:
On Mon, Feb 28, 2022 at 09:30:14AM +, Dov Murik wrote:
> Add a new field 'cpu0-id' to the response of
On Sun, 10 Apr 2022 at 05:51, Brad Smith wrote:
>
> On 4/8/2022 12:47 PM, Thomas Huth wrote:
> > QEMU 7.1 won't support Ubuntu 18.04 anymore, so the last big important
> > distro that did not have a pre-packaged libslirp has been dismissed.
> > All other major distros seem to have a libslirp
On Sat, 9 Apr 2022 at 21:10, Richard Henderson
wrote:
> It it really valid to write to vpendbaser with other than a 64-bit write? I
> suppose it's
> possible to order the 32-bit writes to make sure the update to valid comes
> last...
Yes, that's valid. The GICv3 spec states specifically when
On Sat, 9 Apr 2022 at 20:20, Richard Henderson
wrote:
> On 4/8/22 07:15, Peter Maydell wrote:
> > @@ -2632,6 +2735,12 @@ static void gicv3_cpuif_el_change_hook(ARMCPU *cpu,
> > void *opaque)
> > GICv3CPUState *cs = opaque;
> >
> > gicv3_cpuif_update(cs);
> > +/*
> > + *
Enable the n1 for virt and sbsa board use.
Signed-off-by: Richard Henderson
---
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 64 ++
3 files changed, 66 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
Enable the a76 for virt and sbsa board use.
Signed-off-by: Richard Henderson
---
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 64 ++
3 files changed, 66 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu64.c
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
target/arm/translate-a64.c | 1 +
On 4/9/22 20:58, jianchunfu wrote:
Handling potential memory allocation failures in dirtyrate.
Signed-off-by: jianchunfu
---
migration/dirtyrate.c | 8
1 file changed, 8 insertions(+)
diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c
index aace12a787..5dd40f32c8 100644
Update isar fields per ARM DDI0487 H.a.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index eb8cb738b5..c6c6d89a69 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@
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