Re: [PATCH v5 01/13] mm/memfd: Introduce MFD_INACCESSIBLE flag

On Thu, Mar 10, 2022 at 6:09 AM Chao Peng wrote: > > From: "Kirill A. Shutemov" > > Introduce a new memfd_create() flag indicating the content of the > created memfd is inaccessible from userspace through ordinary MMU > access (e.g., read/write/mmap). However, the file content can be > accessed

Re: [PATCH v2 2/5] 9pfs: fix qemu_mknodat(S_IFSOCK) on macOS

On 2022/04/22 23:06, Christian Schoenebeck wrote: On Freitag, 22. April 2022 04:43:40 CEST Akihiko Odaki wrote: On 2022/04/22 0:07, Christian Schoenebeck wrote: mknod() on macOS does not support creating sockets, so divert to call sequence socket(), bind() and chmod() respectively if S_IFSOCK

[PATCH v12 11/14] target/riscv: rvk: add support for zksed/zksh extension

- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 28 target/riscv/helper.h

[PATCH v12 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++

[PATCH v12 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- disas/riscv.c | 173 +- 1 file changed, 172 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c

[PATCH v12 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++

[PATCH v12 14/14] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 62a47c197b..dff4606585 100644 --- a/target/riscv/cpu.c +++

[PATCH v12 05/14] crypto: move sm4_sbox from target/arm

- share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- crypto/meson.build | 1 + crypto/sm4.c | 49

[PATCH v12 12/14] target/riscv: rvk: add CSR support for Zkr

- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye

[PATCH v12 03/14] target/riscv: rvk: add support for zbkc extension

- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvb.c.inc | 4

[PATCH v12 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/crypto_helper.c

[PATCH v12 02/14] target/riscv: rvk: add support for zbkb extension

- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c

[PATCH v12 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 105

[PATCH v12 00/14] support subsets of scalar crypto extension

This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions. Partial instructions are reused from B-extension. Specification: https://github.com/riscv/riscv-crypto The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v12 To test rvk

[PATCH v12 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ace68ed855..62a47c197b

[PATCH v12 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6

[PATCH v12 04/14] target/riscv: rvk: add support for zbkx extension

- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/bitmanip_helper.c | 27 + target/riscv/helper.h | 2 ++

RE: Backtrace stopped: previous frame identical to this frame (corrupt stack?) , even with fresh qemu and linux build

Hi, Mulyadi Thank you for replying. I found CONFIG_DEBUG_FRAME_POINTER, CONFIG_DEBUG_INFO are already set by default. And I tried adding CONFIG_DEBUG_KERNEL, CONFIG_KGDB, CONFIG_GDB_SCRIPTS, CONFIG_STACKTRACE all to no avail. Regards, Chan From: Mulyadi Santosa Sent: Friday, April 22,

Re: [EXT] Re: [PATCH v2] target/riscv: Fix incorrect PTE merge in walk_pte

On Fri, Apr 22, 2022 at 10:10 PM Ralf Ramsauer wrote: > > > > On 22/04/2022 04:54, Bin Meng wrote: > > On Fri, Apr 22, 2022 at 10:53 AM Bin Meng wrote: > >> > >> On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer > >> wrote: > >>> > >>> Two non-subsequent PTEs can be mapped to subsequent paddrs. In

Re: [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

On Fri, Apr 22, 2022 at 2:05 PM wrote: > > From: Frank Chang > > Allow user to set core's marchid, mvendorid, mipid CSRs through > -cpu command line option. > > The default values of marchid and mipid are built with QEMU's version > numbers. > > Signed-off-by: Frank Chang > Reviewed-by: Jim Shu

Re: [PATCH 2/2] hw/riscv: Don't add empty bootargs to device tree

On Thu, Apr 21, 2022 at 3:58 PM Bin Meng wrote: > > From: Bin Meng > > Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree") > tried to avoid adding *NULL* bootargs to device tree, but unfortunately > the changes were entirely useless, due to MachineState::kernel_cmdline > can't

Re: [PATCH v11 00/14] support subsets of scalar crypto extension

On Tue, Apr 19, 2022 at 11:58 AM Weiwei Li wrote: > > This patchset implements RISC-V scalar crypto extension v1.0.0 version > instructions. > Partial instructions are reused from B-extension. > > Specification: > https://github.com/riscv/riscv-crypto > > The port is available here: >

Re: [RFC 00/18] vfio: Adopt iommufd

[Cc +libvirt folks] On Thu, 14 Apr 2022 03:46:52 -0700 Yi Liu wrote: > With the introduction of iommufd[1], the linux kernel provides a generic > interface for userspace drivers to propagate their DMA mappings to kernel > for assigned devices. This series does the porting of the VFIO devices >

Re: [PATCH] iotests/108: Fix when missing user_allow_other

On Thu, Apr 21, 2022 at 04:24:35PM +0200, Hanna Reitz wrote: > FUSE exports' allow-other option defaults to "auto", which means that it > will try passing allow_other as a mount option, and fall back to not > using it when an error occurs. We make no effort to hide fusermount's > error message

Re: [RFC 15/18] vfio/iommufd: Implement iommufd backend

On Fri, 22 Apr 2022 11:58:15 -0300 Jason Gunthorpe wrote: > > I don't see IOMMU_IOAS_IOVA_RANGES called at all, that seems like a > problem.. Not as much as you might think. Note that you also won't find QEMU testing VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE in the QEMU vfio-pci driver either. The

Re: [PATCH v2 for-7.1 0/9] nbd: actually make s->state thread-safe

On Sat, Apr 16, 2022 at 07:03:57PM +, Lukas Straub wrote: > On Thu, 14 Apr 2022 19:57:47 +0200 > Paolo Bonzini wrote: > > > The main point of this series is patch 7, which removes the dubious and > > probably wrong use of atomics in block/nbd.c. This in turn is enabled > > mostly by the

Re: [PATCH v2 1/3] hw/audio/ac97: Coding style fixes to avoid checkpatch errors

On 22/04/2022 12:14, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/audio/ac97.c | 727 1 file changed, 357 insertions(+), 370 deletions(-) diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c index 3cb8131060..0b1d8ce9c6 100644 ---

Re: [PATCH v2] Only advertise aio=io_uring if support is actually available

On Thu, Apr 21, 2022 at 02:27:55PM -0500, Eric Blake wrote: > On Thu, Apr 21, 2022 at 06:50:48PM +0200, Dirk Müller wrote: > > Change --help output for aio option to only list the aio backend options > > that > > are actually available. io_uring is an optional, linux only backend > > option so

Re: [PATCH v3 0/3] nbd: MULTI_CONN for shared writable exports

Ping. Now that 7.1 is open, I'd like to include this series in my next NBD pull request. On Mon, Mar 14, 2022 at 03:38:15PM -0500, Eric Blake wrote: > v2 was here: > https://lists.gnu.org/archive/html/qemu-devel/2022-02/msg03314.html > > Since then: > - expose the knob through 'qemu-nbd -m

Re: [PATCH v2 for-7.1 0/3] qapi: nbd-export: select bitmap by node/name pair

On Tue, Mar 15, 2022 at 12:45:04AM +0300, Vladimir Sementsov-Ogievskiy wrote: > 15.03.2022 00:32, Vladimir Sementsov-Ogievskiy wrote: > > From: Vladimir Sementsov-Ogievskiy > > > > Hi all! > > > > Here is small improvement for bitmap exporting interface. > > > > v2: Sorry for the noise, me

Re: [PATCH v2 2/3] qapi: nbd-export: allow select bitmaps by node/name pair

On Fri, Apr 08, 2022 at 11:27:42PM +0300, Vladimir Sementsov-Ogievskiy wrote: > 17.03.2022 00:28, Eric Blake wrote: > > > +++ b/qapi/block-export.json > > > @@ -6,6 +6,7 @@ > > > ## > > > { 'include': 'sockets.json' } > > > +{ 'include': 'block-core.json' } > > Hmm. Does this extra inclusion

Re: [RFC PATCH] 9p: case-insensitive host filesystems

Christian Schoenebeck wrote on Fri, Apr 22, 2022 at 08:02:46PM +0200: > So maybe it's better to handle case-insensitivity entirely on client side? > I've read that some generic "case fold" code has landed in the Linux kernel > recently that might do the trick? I haven't tried, but settings

[PATCH] target/xtensa: add clock input to xtensa CPU

Create clock input for the xtensa CPU device and initialize its frequency to the default core frequency specified in the config. Signed-off-by: Max Filippov --- target/xtensa/cpu.c | 15 +++ target/xtensa/cpu.h | 5 + target/xtensa/op_helper.c | 7 --- 3 files

[PATCH 20/20] target/ppc: Add unused M_MSR_* macros

Add M_MSR_* macros for msr bits that had an unused msr_* before. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 24 1 file changed, 24 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3cbecc96d8..dda289a121 100644 --- a/target/ppc/cpu.h +++

[PATCH 19/20] target/ppc: Substitute msr_hv macro with new M_MSR_HV macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 11 +-- target/ppc/cpu_init.c| 4 ++-- target/ppc/excp_helper.c | 9 + target/ppc/mem_helper.c | 5 +++-- target/ppc/misc_helper.c | 2 +- target/ppc/mmu-radix64.c | 6 +++---

[PATCH 18/20] target/ppc: Substitute msr_ts macro with new M_MSR_TS macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 4 +++- target/ppc/kvm.c | 4 ++-- target/ppc/machine.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b957fc95e0..ee00b27818 100644 ---

[PATCH 15/20] target/ppc: Substitute msr_dr macro with new M_MSR_DR macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/helper_regs.c | 2 +- target/ppc/mmu_common.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

[PATCH 08/20] target/ppc: Substitute msr_ce macro with new M_MSR_CE macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/excp_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bfde66ed66..3f10c1f5b2 100644 --- a/target/ppc/cpu.h +++

[PATCH 17/20] target/ppc: Substitute msr_fe macro with new M_MSR_FE macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 5 +++-- target/ppc/excp_helper.c | 12 ++-- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1767a3a430..b957fc95e0 100644 ---

[PATCH 14/20] target/ppc: Substitute msr_ir macro with new M_MSR_IR macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/helper_regs.c | 2 +- target/ppc/mmu_common.c | 11 ++- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

[PATCH 07/20] target/ppc: Substitute msr_ee macro with new M_MSR_EE macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/cpu_init.c| 15 ++- target/ppc/excp_helper.c | 2 +- target/ppc/kvm.c | 3 ++- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git

[PATCH 04/20] target/ppc: Substitute msr_le macro with new M_MSR_LE macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h| 2 +- target/ppc/cpu_init.c | 2 +- target/ppc/gdbstub.c| 2 +- target/ppc/mem_helper.c | 16 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/ppc/cpu.h

[PATCH 16/20] target/ppc: Substitute msr_ep macro with new M_MSR_EP macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/helper_regs.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3a5218a2cd..1767a3a430 100644 --- a/target/ppc/cpu.h +++

[PATCH 13/20] target/ppc: Substitute msr_cm macro with new M_MSR_CM macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h| 2 +- target/ppc/mmu_common.c | 2 +- target/ppc/mmu_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 634c05a9d2..e26530fa09

[PATCH 06/20] target/ppc: Substitute msr_ile macro with new M_MSR_ILE macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e81f1f2d68..95c28c3c1b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -353,6 +353,7 @@

[PATCH 01/20] target/ppc: Remove fpscr_* macros from cpu.h

fpscr_* defined macros are hiding the usage of *env behind them. Substitute the usage of these macros with `env->fpscr & FP_*` to make the code cleaner. Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.c| 2 +- target/ppc/cpu.h| 29

[PATCH 12/20] target/ppc: Substitute msr_fp macro with new M_MSR_FP macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/excp_helper.c | 12 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 15f5d059a3..634c05a9d2 100644 ---

[PATCH 02/20] target/ppc: Remove unused msr_* macros

Some msr_* macros are not used anywhere. Remove them as part of the work to remove all hidden usage of *env. Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 21 - 1 file changed, 21 deletions(-) diff --git a/target/ppc/cpu.h

[PATCH 11/20] target/ppc: Substitute msr_gs macro with new M_MSR_GS macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/helper_regs.c | 2 +- target/ppc/mmu_helper.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index aa20a604ab..15f5d059a3

[PATCH 00/20] target/ppc: Remove hidden usages of *env

By running the grep command `git grep -nr 'define \(fpscr\|msr\)_[a-z0-9]\+\>'` we can find multiple macros that use `env->fpscr` and `env->msr` but doesn't take *env as a parameter. Richard Henderson said [1] that these macros hiding the usage of *env "are evil". This patch series remove them

[PATCH 10/20] target/ppc: Substitute msr_me macro with new M_MSR_ME macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/excp_helper.c | 12 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b79c00dd65..aa20a604ab 100644 ---

[PATCH 09/20] target/ppc: Substitute msr_pow macro with new M_MSR_POW macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/excp_helper.c | 12 ++-- target/ppc/helper_regs.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

[qemu.qmp PATCH 05/12] add a couple new trove classifiers

Signed-off-by: John Snow Reviewed-by: Beraldo Leal --- setup.cfg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/setup.cfg b/setup.cfg index 0a1c215..000f00a 100644 --- a/setup.cfg +++ b/setup.cfg @@ -12,6 +12,7 @@ long_description = file:PACKAGE.rst long_description_content_type =

[qemu.qmp PATCH 09/12] add LGPLv2+ and GPLv2 LICENSE files

This clarifies that the majority of this package is LGPLv2+. Copyright blurbs that pointed to QEMU's "COPYING" file are amended to point to this repository's "LICENSE" file instead. The only file that is not already licensed as LGPLv2+ is legacy.py, which is GPLv2 only. Amend the copyright blurb

[PATCH 05/20] target/ppc: Substitute msr_ds macro with new M_MSR_DS macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- target/ppc/cpu.h| 2 +- target/ppc/mmu_common.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d25a778b7c..e81f1f2d68 100644 --- a/target/ppc/cpu.h +++

[PATCH 03/20] target/ppc: Substitute msr_pr macro with new M_MSR_PR macro

Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo --- hw/ppc/pegasos2.c| 2 +- hw/ppc/spapr.c | 2 +- target/ppc/cpu.h | 3 ++- target/ppc/cpu_init.c| 4 ++-- target/ppc/excp_helper.c | 6 +++--- target/ppc/mem_helper.c | 4 ++--

[qemu.qmp PATCH 11/12] remove sub-dependency pins from Pipfile

Now that we've got a Pipfile.lock generated that works, we can remove the static pins from the Pipfile to allow various dependencies to be added or removed as necessary when updating our direct dependencies in the future. So long as --keep-outdated is always passed to Pipenv, items that aren't

[qemu.qmp PATCH 12/12] update VERSION to 0.0.0a1

qemu.qmp will be independently versioned, without regard to QEMU version. While the repo is being established here, set the version to something impossibly low. Later, I intend to introduce automatic versioning based on git tags. While the repo is being established it's going to be easier to have

[qemu.qmp PATCH 02/12] update maintainer metadata

Modify "QEMU Developer Team" to "QEMU Project", as this matches the spelling we use for the collective on gitlab.com/qemu-project. Add myself as the principal maintainer contact. Signed-off-by: John Snow --- setup.cfg | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

[qemu.qmp PATCH 08/12] docs: add versioning policy to README

The package is in an alpha state, but there's a method to the madness. Signed-off-by: John Snow Reviewed-by: Damien Hedde --- README.rst | 22 ++ 1 file changed, 22 insertions(+) diff --git a/README.rst b/README.rst index 20f513e..cea1400 100644 --- a/README.rst +++

[qemu.qmp PATCH 10/12] update Pipfile

The name of the package has changed and the dependencies are different, so the Pipfile needs to be updated. This is a little annoying, but Python doesn't offer any tool (to my knowledge) that behaves in a manner that gives you the *oldest*, but still adequate, versions of dependencies. So testing

[qemu.qmp PATCH 06/12] move README.rst to FILES.rst and update

The intent is to use README.rst as the new package-level readme that will be bundled with the source and be displayed on the GitLab landing page; so move the old "git level readme" over to FILES.rst instead, and update it accordingly. This is primarily here to just document and explain what all

[qemu.qmp PATCH 01/12] fork qemu.qmp from qemu.git

Split python/ from qemu.git, using these commands: > git subtree split -P python/ -b python-split-v3 > mkdir ~/src/tmp > cd ~/src/tmp > git clone --no-local --branch python-split-v3 --single-branch ~/src/qemu > cd qemu > git filter-repo --path qemu/machine/ \ --path

[qemu.qmp PATCH 03/12] update project description

Signed-off-by: John Snow Reviewed-by: Beraldo Leal --- setup.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.cfg b/setup.cfg index f06f944..c21f2ce 100644 --- a/setup.cfg +++ b/setup.cfg @@ -7,7 +7,7 @@ maintainer = John Snow maintainer_email = js...@redhat.com

[qemu.qmp PATCH 00/12] python: fork qemu.qmp python lib into independent repo

GitLab: https://gitlab.com/jsnow/qemu.qmp/-/commits/initial-checkin Hi, this series is part of an effort to publish the qemu.qmp package on PyPI. It is part of the second of three phases to complete this work: (1) Switch the new Async QMP library in to python/qemu/qmp [merged!] (2) Fork

[qemu.qmp PATCH 04/12] update project URLs

Point to this library's URLs instead of the entire project's. Signed-off-by: John Snow --- setup.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/setup.cfg b/setup.cfg index c21f2ce..0a1c215 100644 --- a/setup.cfg +++ b/setup.cfg @@ -5,8 +5,8 @@ author = QEMU Project

[qemu.qmp PATCH 07/12] move PACKAGE.rst to README.rst and update

The README here will reflect both what is shown on GitLab and on the PyPI landing page. Update it accordingly, and freshen it up. The documentation URL still points to my mirror, as the patches to establish sphinx as part of the build process aren't checked in yet, this will be updated later.

Re: [PULL v2 00/61] target-arm queue

/pmaydell/qemu-arm.git tags/pull-target-arm-20220422-1 for you to fetch changes up to c3ca7d56c4790c2223122f7e84b71161cd36dbce: hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() (2022-04-22 14:44:55 +0100

Re: [PATCH] qapi: Fix malformed "Since:" section tags

On Fri, Apr 22, 2022 at 03:28:07PM +0200, Markus Armbruster wrote: > "Since X.Y" is not recognized as a tagged section, and therefore not > formatted as such in generated documentation. Fix by adding the > required colon. > > Signed-off-by: Markus Armbruster > --- > qapi/crypto.json | 3 +--

[RFC PATCH] 9p: case-insensitive host filesystems

Now that 9p support for macOS hosts just landed in QEMU 7.0 and with support for Windows hosts on the horizon [1], the question is how to deal with case- insensitive host filesystems, which are very common on those two systems? I made some tests, e.g. trying to setup a 9p root fs Linux

[PATCH v9 09/12] target/hexagon: import lexer for idef-parser

From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/idef-parser.h | 253 +++ target/hexagon/idef-parser/idef-parser.lex | 471 +

[PATCH v9 07/12] target/hexagon: prepare input for the idef-parser

From: Alessandro Di Federico Introduce infrastructure necessary to produce a file suitable for being parsed by the idef-parser. Signed-off-by: Alessandro Di Federico Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/gen_idef_parser_funcs.py | 128

target/i386/kvm/kvm.c:2996: kvm_buf_set_msrs: Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed

Hi! Apparently there's an assertion failure like in $subj in qemu-7.0.0 (it didn't happen with qemu-6.2), even after the commit: commit e910a53fb4f20aa012e46371ffb4c32c8da259b4 Author: Maxim Levitsky Date: Wed Feb 23 13:56:49 2022 +0200 KVM: x86: nSVM: disallow userspace setting of

[PATCH v9 10/12] target/hexagon: import parser for idef-parser

Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/idef-parser.y| 961 target/hexagon/idef-parser/parser-helpers.c | 2346 +++

[PATCH v9 04/12] target/hexagon: make helper functions non-static

From: Paolo Montesel Make certain helper functions non-static, making them available outside genptr.c. These functions are required by code generated by the idef-parser. This commit also makes some op_helper.c non-static in order to avoid having them marked as unused when using the idef-parser

[PATCH v9 08/12] target/hexagon: import flex/bison to docker files

This patch points `tests/lcitool/libvirt-ci` to an upstreamed commit of `libvirt-ci` which includes flex and bison. The `lcitool/refresh` script was then ran to update the the generated docker/cirrus files. Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Signed-off-by: Anton

[PATCH v9 12/12] target/hexagon: import additional tests

From: Niccolò Izzo Signed-off-by: Alessandro Di Federico Signed-off-by: Niccolò Izzo Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- tests/tcg/hexagon/Makefile.target | 28 - tests/tcg/hexagon/crt.S| 14 +++ tests/tcg/hexagon/test_abs.S | 17

[PATCH v9 06/12] target/hexagon: expose next PC in DisasContext

From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Reviewed-by: Richard Henderson Reviewed-by: Taylor Simpson --- target/hexagon/translate.c | 3 ++- target/hexagon/translate.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH v9 03/12] target/hexagon: make slot number an unsigned

From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Acked-by: Richard Henderson Reviewed-by: Taylor Simpson --- target/hexagon/genptr.c | 24 +--- target/hexagon/macros.h | 2 +- 2 files changed, 14 insertions(+), 12 deletions(-)

[PATCH v9 00/12] target/hexagon: introduce idef-parser

This patchset introduces the idef-parser for target/hexagon. It's the ninth iteration of the patchset and includes fixes suggested in previous iterations. `idef-parser` is a build-time tool built using flex and bison. Its aim is to generate a large part of the tiny code generator frontend for

[PATCH v9 01/12] target/hexagon: update MAINTAINERS for idef-parser

From: Alessandro Di Federico Signed-off-by: Alessandro Di Federico Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Taylor Simpson --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 294c88ace9..d6b62ff319

[PATCH v9 05/12] target/hexagon: introduce new helper functions

From: Niccolò Izzo These helpers will be employed by the idef-parser generated code, to correctly implement instruction semantics. "Helper" functions, in the context of this patch, refers to functions which provide a manual TCG implementation of certain features. Signed-off-by: Alessandro Di

[PATCH v8 63/68] hw/intc: Vectored Interrupt Controller (VIC)

From: Amir Gonnen Implement nios2 Vectored Interrupt Controller (VIC). VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi fields on Nios2CPU before raising an IRQ. For that purpose, VIC has a "cpu" property which should refer to the nios2 cpu and set by the board that connects

[PATCH v9 02/12] target/hexagon: import README for idef-parser

From: Alessandro Di Federico Signed-off-by: Alessandro Di Federico Signed-off-by: Anton Johansson Reviewed-by: Taylor Simpson --- target/hexagon/README | 5 + target/hexagon/idef-parser/README.rst | 722 ++ 2 files changed, 727 insertions(+) create

Re: [PATCH] qga/vss-win32: enable qga-vss.tlb generation with widl

Hello, a few moments ago I sent a PR to Msys2 to make widl work as expected. I've prepared a rather simple patch to activate the generation of qga-vss.tlb by widl in targets all and qemu-ga, which I will post later on. Thank you for your patience and your help! Regards, Helge. Am 20.04.22

[PATCH v8 58/68] target/nios2: Implement rdprs, wrprs

Implement these out of line, so that tcg global temps (aka the architectural registers) are synced back to tcg storage as required. This makes sure that we get the proper results when status.PRS == status.CRS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id:

[PATCH v8 52/68] target/nios2: Create gen_jumpr

Split out a function to perform an indirect branch. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-49-richard.hender...@linaro.org> --- target/nios2/translate.c | 27 +-- 1 file changed, 13 insertions(+), 14 deletions(-)

[PATCH v8 66/68] hw/nios2: Machine with a Vectored Interrupt Controller

From: Amir Gonnen Demonstrate how to use nios2 VIC on a machine. Introduce a new machine property to attach a VIC. When VIC is present, let the CPU know that it should use the External Interrupt Interface instead of the Internal Interrupt Interface. The devices on the machine are attached to

[PATCH v9 11/12] target/hexagon: call idef-parser functions

From: Alessandro Di Federico Extend gen_tcg_funcs.py in order to emit calls to the functions emitted by the idef-parser, if available. An option is also added to fully disable the output of the idef-parser, which is useful for debugging purposes. Signed-off-by: Alessandro Di Federico

[PATCH v8 51/68] target/nios2: Enable unaligned traps for system mode

Unaligned traps are optional, but required with an mmu. Turn them on always, because the fallback behaviour undefined. Enable alignment checks in the config file. Unwind the guest pc properly from do_unaligned_access. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id:

[PATCH v8 68/68] tests/tcg/nios2: Add test-shadow-1

Add a regression test for tcg indirect global lowering. This appeared with nios2, with cps != 0, so that we use indirection into the shadow register set. An indirect call verifies alignment of rA. The use of rA was live across the brcond leading to a tcg_debug_assert failure. Cc: Alex Bennée

[PATCH v8 64/68] hw/nios2: Introduce Nios2MachineState

We want to move data from the heap into Nios2MachineState, which is not possible with DEFINE_MACHINE. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-61-richard.hender...@linaro.org> --- hw/nios2/10m50_devboard.c | 24 ++-- 1

[PATCH v8 65/68] hw/nios2: Move memory regions into Nios2Machine

Convert to contiguous allocation, as much as possible so far. The two timer objects are not exposed for subobject allocation. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-62-richard.hender...@linaro.org> --- hw/nios2/10m50_devboard.c | 30

[PATCH v8 50/68] target/nios2: Drop CR_STATUS_EH from tb->flags

There's nothing about EH that affects translation, so there's no need to include it in tb->flags. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-47-richard.hender...@linaro.org> --- target/nios2/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH v8 60/68] target/nios2: Implement EIC interrupt processing

This is the cpu side of the operation. Register one irq line, called EIC. Split out the rather different processing to a separate function. Delay initialization of gpio irqs until realize. We need to provide a window after init in which the board can set eic_present. Signed-off-by: Richard

[PATCH v8 67/68] tests/tcg/nios2: Add semihosting multiarch tests

Add runtime supporting the nios2-semi.c interface. Execute the hello and memory multiarch tests. Cc: Alex Bennée Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-64-richard.hender...@linaro.org> --- tests/tcg/nios2/semicall.h | 28 +++

[PATCH v8 61/68] target/nios2: Advance pc when raising exceptions

The exception return address for nios2 is the instruction after the one that was executing at the time of the exception. We have so far implemented this by advancing the pc during the process of raising the exception. It is perhaps a little less confusing to do this advance in the translator

[PATCH v8 49/68] target/nios2: Introduce dest_gpr

Constrain all references to cpu_R[] to load_gpr and dest_gpr. This will be required for supporting shadow register sets. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-46-richard.hender...@linaro.org> --- target/nios2/translate.c | 144

[PATCH v8 62/68] linux-user/nios2: Handle various SIGILL exceptions

We missed out on a couple of exception types that may legitimately be raised by a userland program. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-59-richard.hender...@linaro.org> --- linux-user/nios2/cpu_loop.c | 12 1 file changed,

[PATCH v8 57/68] target/nios2: Introduce shadow register sets

Do not actually enable them so far, in terms of being able to change the current register set, but add all of the plumbing to address them. Do not enable them for user-only. Add an env->regs pointer that handles the indirection to the current register set. The naming of the pointer hides the

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