On 5/19/2022 9:07 PM, Chao Peng wrote:
> A page fault can carry the information of whether the access if private
> or not for KVM_MEM_PRIVATE memslot, this can be filled by architecture
> code(like TDX code). To handle page faut for such access, KVM maps the
> page only when this private property m
On Mon, 20 Jun 2022 at 19:51, Richard Henderson
wrote:
>
> Note that SME remains effectively disabled for user-only,
> because we do not yet set CPACR_EL1.SMEN. This needs to
> wait until the kernel ABI is implemented.
>
> Signed-off-by: Richard Henderson
> ---
> docs/system/arm/emulation.rst |
On Fri, Jun 24, 2022 at 04:54:26PM +0800, Chao Peng wrote:
> On Thu, Jun 23, 2022 at 05:59:49PM -0500, Michael Roth wrote:
> > On Fri, May 20, 2022 at 06:31:02PM +, Sean Christopherson wrote:
> > > On Fri, May 20, 2022, Andy Lutomirski wrote:
> > > > The alternative would be to have some kind o
On Mon, 20 Jun 2022 at 19:55, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Same commit message remark.
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 20 Jun 2022 at 19:14, Richard Henderson
wrote:
>
> We can handle both exception entry and exception return by
> hooking into aarch64_sve_change_el.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
On 6/22/22 02:08, Alexey Kardashevskiy wrote:
It keeps repeating, move it to the header. This uses __builtin_ffsl() to
allow using the macros in #define.
This is not using the QEMU's FIELD macros as this would require changing
all such macros found in skiboot (the PPC PowerNV firmware).
Sign
On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
wrote:
>
> On Fri, 24 Jun 2022 11:48:47 +0100
> Peter Maydell wrote:
> >
> > This seems to be missing code to advertise the new devices in the
> > device tree.
>
> Intentionally. I am not aware of any current interest
> in defining DT support CXL or
On Mon, 20 Jun 2022 at 19:57, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Again, commit message could note that this is an SVE insn that's
only present with SME implemented.
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 20 Jun 2022 at 19:14, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Would be helpful to note in the commit message that this is an
SVE instruction that operates using the SVE vector length but that
it is present only if SME is implemented.
> +static bool trans_PSEL(Disas
On 6/23/22 04:31, Alexey Kardashevskiy wrote:
PAPR 2.8 (2018) defines an extension to return 64bit value for
the largest TCE block in "ibm,query-pe-dma-window". Recent Linux kernels
support this already.
This adds the extension and supports the older format.
This advertises a bigger window f
On 6/22/22 02:10, Alexey Kardashevskiy wrote:
The new PAPR 2.12 defines a watchdog facility managed via the new
H_WATCHDOG hypercall.
This adds H_WATCHDOG support which a proposed driver for pseries uses:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=303120
This was tested b
On 6/22/22 02:29, Alexey Kardashevskiy wrote:
PAPR+/LoPAPR says:
===
The platform must restore the default DMA window for the PE on a call
to the ibm,remove-pe-dma-window RTAS call when all of the following
are true:
a. The call removes the last DMA window remaining for the PE.
b. The DMA
On Mon, 20 Jun 2022 at 19:29, Richard Henderson
wrote:
>
> This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sme.h| 16
> target/arm/sme.decode | 10 +
> target/arm/sme_helper.c| 82 ++
On Fri, 24 Jun 2022 11:48:47 +0100
Peter Maydell wrote:
> On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
> wrote:
> >
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extended memmap.
> > The CFMWs are p
On Mon, 20 Jun 2022 at 19:07, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
> + void *vpm, void *vst, uint32_t desc)
> +{
> +intptr_t row, col, oprsz = simd_maxsz(desc);
> +uin
On 6/23/22 18:34, Richard Henderson wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 6/23/22 07:26, Leandro Lupori wrote:
On 6/21/22
On Thu, Jun 23, 2022 at 07:13:24PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> From: Konstantin Khlebnikov
>
> Kernel and user vhost may report virtqueue errors via eventfd.
> This is only reliable way to get notification about protocol error.
^^^
the
>
> Signed-off-by: Konstan
Thanks! I will be offline for the next week.
Feel free to progress this series without my review.
Stefan
On Fri, Jun 24, 2022, 11:53 Andrey Ryabinin wrote:
>
>
> On 6/15/22 16:10, Stefan Hajnoczi wrote:
> > On Tue, Jun 14, 2022 at 02:18:41PM +0300, Andrey Ryabinin wrote:
> >> Hi
> >>
> >> Thes
On Fri, Jun 24, 2022 at 02:00:15PM +0300, Andrey Ryabinin wrote:
>
>
> On 6/15/22 16:12, Stefan Hajnoczi wrote:
> > On Tue, Jun 14, 2022 at 02:18:42PM +0300, Andrey Ryabinin wrote:
> >> This reverts commit 9b938c7262e4 ("chardev: clear O_NONBLOCK on SCM_RIGHTS
> >> file descriptors").
> >> File
On 6/15/22 16:12, Stefan Hajnoczi wrote:
> On Tue, Jun 14, 2022 at 02:18:42PM +0300, Andrey Ryabinin wrote:
>> This reverts commit 9b938c7262e4 ("chardev: clear O_NONBLOCK on SCM_RIGHTS
>> file descriptors").
>> File descriptor passed to QEMU via 'getfd' QMP command always
>> changed to blockin
On 6/15/22 16:10, Stefan Hajnoczi wrote:
> On Tue, Jun 14, 2022 at 02:18:41PM +0300, Andrey Ryabinin wrote:
>> Hi
>>
>> These couple patches aims to make possible local migration (within one host)
>> on the same TAP device used by source and destination QEMU
>>
>> The scenario looks like this
>
On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
wrote:
>
> Code based on i386/pc enablement.
> The memory layout places space for 16 host bridge register regions after
> the GIC_REDIST2 in the extended memmap.
> The CFMWs are placed above the extended memmap.
>
> Only create the CEDT table if cxl=o
On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
wrote:
>
> Add a single complex case for aarch64 virt machine.
>
> Signed-off-by: Jonathan Cameron
> ---
> tests/qtest/cxl-test.c | 48 +
> tests/qtest/meson.build | 1 +
> 2 files changed, 40 insertions(+),
On Sat, 28 May 2022 at 21:11, Ben Cohen wrote:
>
> I was testing some multi-threaded code in qemu's usermode and ran into
> issues with the gdbstub because the user mode qemu emulation spawns new
> threads when the process tries to make a new thread but the gdbstub does
> not handle the threads we
On Thu, 23 Jun 2022 at 21:36, Richard Henderson
wrote:
> On 6/23/22 04:41, Peter Maydell wrote:
> > We now have several rather long functions that are
> > pretty complicated and pretty similar handling the various
> > SVE and SME loads and stores. Is there really no hope for
> > sharing code ?
>
>
On 24/06/2022 11.20, Christian Borntraeger wrote:
Am 24.06.22 um 10:50 schrieb Thomas Huth:
The s390-ccw bios fails to boot if the boot disk is a virtio-blk
disk with a sector size of 4096. For example:
dasdfmt -b 4096 -d cdl -y -p -M quick /dev/dasdX
fdasd -a /dev/dasdX
install a guest
From: Ilya Leoshkevich
Currently QEMU ignores madvise(MADV_DONTNEED), which break apps that
rely on this for zeroing out memory [1]. Improve the situation by doing
a passthrough when the range in question is a host-page-aligned
anonymous mapping.
This is based on the patches from Simon Hausmann
From: Helge Deller
Keep track of the new child tidptr given by a set_tid_address() syscall.
Do not call the host set_tid_address() syscall because we are emulating
the behaviour of writing to child_tidptr in the exit() path.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
Reviewed-b
Laurent Vivier writes:
> Copied from socket netdev file and modified to use SocketAddress
> to be able to introduce new features like unix socket.
>
> "udp" and "mcast" are squashed into dgram netdev, multicast is detected
> according to the IP address type.
> "listen" and "connect" modes are man
From: Richard Henderson
We had been using the i686 platform string for x86_64.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1041
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Vivier
Message-Id: <20220603213801.64738-1-richard.hender...@linaro.org>
Signed-off-by: Laurent Vivi
-user pull request 20220624
Helge Deller (1):
linux-user: Adjust child_tidptr on set_tid_address() syscall
Ilya Leoshkevich (1):
linux-user: Add partial support for MADV_DONTNEED
Richard Henderson (1):
linux-user/x86_64: Fix EL
We also need to switch to the right address space on dest side
after loading the device status. DMA to wrong address space is
destructive.
Fixes: 3facd774962fd ("virtio-iommu: Add bypass mode support to assigned
device")
Suggested-by: Eric Auger
Signed-off-by: Zhenzhong Duan
---
hw/virtio/virt
Laurent Vivier writes:
> Copied from socket netdev file and modified to use SocketAddress
> to be able to introduce new features like unix socket.
>
> "udp" and "mcast" are squashed into dgram netdev, multicast is detected
> according to the IP address type.
> "listen" and "connect" modes are man
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Rename qemu_semihosting_connect_chardevs to
> qemu_semihosting_chardev_init; pass the result
> directly to qemu_semihosting_console_init.
>
> Store the chardev in SemihostingConsole instead
> of SemihostingConfig, which lets us drop
> semihostin
On Fri, Jun 24, 2022 at 09:28:23AM +0530, Nikunj A. Dadhania wrote:
> On 5/19/2022 9:07 PM, Chao Peng wrote:
> > A page fault can carry the information of whether the access if private
> > or not for KVM_MEM_PRIVATE memslot, this can be filled by architecture
> > code(like TDX code). To handle page
On Thu, Jun 23, 2022 at 05:59:49PM -0500, Michael Roth wrote:
> On Fri, May 20, 2022 at 06:31:02PM +, Sean Christopherson wrote:
> > On Fri, May 20, 2022, Andy Lutomirski wrote:
> > > The alternative would be to have some kind of separate table or bitmap
> > > (part
> > > of the memslot?) that
Queued, thanks.
Paolo
Am 24.06.22 um 10:50 schrieb Thomas Huth:
The s390-ccw bios fails to boot if the boot disk is a virtio-blk
disk with a sector size of 4096. For example:
dasdfmt -b 4096 -d cdl -y -p -M quick /dev/dasdX
fdasd -a /dev/dasdX
install a guest onto /dev/dasdX1 using virtio-blk
qemu-system-s
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Allow more than one character to be read at one time.
> Will be used by m68k and nios2 semihosting for stdio.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/console.h | 12 +++-
> linux-user
The s390-ccw bios fails to boot from non-DASD disks that have a
sector size of 4096. Fix it by relaxing the check for the disk
geometries.
Thomas Huth (2):
pc-bios/s390-ccw/virtio-blkdev: Simplify/fix
virtio_ipl_disk_is_valid()
pc-bios/s390-ccw/virtio-blkdev: Remove virtio_assume_scsi()
The s390-ccw bios fails to boot if the boot disk is a virtio-blk
disk with a sector size of 4096. For example:
dasdfmt -b 4096 -d cdl -y -p -M quick /dev/dasdX
fdasd -a /dev/dasdX
install a guest onto /dev/dasdX1 using virtio-blk
qemu-system-s390x -nographic -hda /dev/dasdX1
The bios then bai
The virtio_assume_scsi() function is very questionable: First, it
is only called for virtio-blk, and not for virtio-scsi, so the naming
is already quite confusing. Second, it is called if we detected a
"invalid" IPL disk, trying to fix it by blindly setting a sector
size of 512. This of course won'
The attribute is unused.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4_pec.c | 2 --
include/hw/pci-host/pnv_phb4.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 0ef66b9a9b..8dc363d69c 100644
--- a/hw/pci-
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' pointer that will be initialized
with the PHB implementatio
The helper is only used in this file.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 24
hw/ppc/pnv.c | 25 -
include/hw/ppc/pnv.h | 1 -
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/hw/pci-host/p
On Thu, 16 Jun 2022 15:19:48 +0100
Jonathan Cameron via wrote:
> Previously patches 40 and 41 of
> [PATCH v10 00/45] CXl 2.0 emulation Support
> https://lore.kernel.org/qemu-devel/20220429144110.25167-45-jonathan.came...@huawei.com/#r
>
> Now the base CXL support including for x86/pc is upstream
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb3.c |
The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
regions, registering it via pci_register_root_bus() and then setup the
iommu.
We'll want to init the bus from outside pnv_phb3.c when the bus is
removed from the PnvPHB3 device and put into a new parent PnvPHB device.
The new pn
Similar to what we already did for the PnvPHB3 device, let's add a
helper to init the bus when using a PnvPHB4. This helper will be used by
PnvPHb when PnvPHB4 turns into a backend.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 2 ++
hw/pci-host/pnv_phb4.c
It's unused.
Signed-off-by: Daniel Henrique Barboza
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 61a0cb9989..20aa4819d3 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pc
We support only a single root port, PNV_PHB_ROOT_PORT.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 7 +--
hw/ppc/pnv.c | 9 +
include/hw/ppc/pnv.h | 3 +--
3 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-
Laurent Vivier writes:
> As qemu_opts_parse_noisily() flattens the QAPI structures ("type" field
> of Netdev structure can collides with "type" field of SocketAddress),
> we introduce a way to bypass qemu_opts_parse_noisily() and use directly
> visit_type_Netdev() to parse the backend parameters.
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Change 'ret' to uint64_t. This resolves a FIXME in the
> m68k and nios2 semihosting that we've lost data.
> Change 'err' to int. There is nothing target-specific
> about the width of the errno value.
>
> Signed-off-by: Richard Henderson
> ---
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is that
pnv-phb4-root-port has the pnv_phb4_root_port_
The unified pnv-phb-root-port can be used instead. The phb4-root-port
device isn't exposed to the user in any official QEMU release so there's
no ABI breakage in removing it.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 4 +-
hw/pci-host/pnv_phb4.c | 85 --
From: Alexander Bulekov
The sancov filter check still fails when unused arguments are treated as
errors. To work around that, add a SanitizerCoverage flag to the
build-check.
Fixes: aa4f3a3b88 ("build: fix check for -fsanitize-coverage-allowlist")
Signed-off-by: Alexander Bulekov
Message-Id: <2
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a
couple of instances in pnv_phb3.c that needs to
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> We don't need CPUArchState, and we do want the CPUState of the
> thread performing the operation -- use this instead of current_cpu.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.
pnv_phb4_pec now creates a PnvPHB object.
The powernv9 machine class
From: Miaoqian Lin
This function doesn't release descriptors in one error path,
result in memory leak. Call g_free() to release it.
Fixes: cc01a3f4cadd ("kvm: Support for querying fd-based stats")
Signed-off-by: Miaoqian Lin
Message-Id: <20220624063159.57411-1-linmq...@gmail.com>
Signed-off-by:
Hi,
This is the version 3 of the pnv-phb proxy device which has the
following main differences from v2:
- it's rebased on top of "[PATCH v3 0/8] pnv-phb related cleanups"
- it doesn't have any patches related to user-created devices
There is no user visible change made here yet. We're making dev
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> The implementation of qemu_semihosting_console_inc does not
> defer to gdbstub, but only reads from the fifo in console.c.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/console.h | 9 -
> 1
System emulation tests do not run in a hosted environment, since they
do not link with libc. They should only use freestanding headers
(float.h, limits.h, stdarg.h, stddef.h, stdbool.h, stdint.h,
stdalign.h, stdnoreturn.h) and should be compiled with -ffreestanding
in order to use the compiler imp
When running from the build tree, the executable is able to find
the BIOS on its own; when running from the source tree, a firmware
blob should already be installed and there is no guarantee that
the one in the source tree works with the QEMU that is being used for
the installation.
Just remove th
On Thu, Jun 23, 2022 at 05:07:51PM -0500, Michael Roth wrote:
...
> > diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
> > index db9d39a2d3a6..f93ac7cdfb53 100644
> > --- a/virt/kvm/kvm_main.c
> > +++ b/virt/kvm/kvm_main.c
> > @@ -843,6 +843,73 @@ static int kvm_init_mmu_notifier(struct kvm *
>-Original Message-
>From: Eric Auger
>Sent: Friday, June 24, 2022 12:52 AM
>To: Duan, Zhenzhong
>Cc: qemu-devel@nongnu.org; m...@redhat.com; jean-phili...@linaro.org;
>pbonz...@redhat.com; Zhang, Yu C ; Dong,
>Chuanxiao ; Zhang, Tina
>
>Subject: Re: [PATCH 1/3] virtio-iommu: Add bypass m
The following changes since commit 2b049d2c8dc01de750410f8f1a4eac498c04c723:
Merge tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu into
staging (2022-06-22 07:27:06 -0700)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you t
From: Marc-André Lureau
Commit c9c847481 broken dbus audio module compilation with bad
'CONFIG_GIO' usage. Furthermore, it implied extra dependency on audio
module which aren't necessary.
The problem was that 'dbus_display' is not correctly automatically set
on MacOS, because opengl dependency w
From: Thomas Huth
According to https://gitlab.com/qemu-project/qemu/-/issues/1080#note_998088246
QEMU does not compile with older versions of libpng, so we should check
for a good version in meson.build. According to repology.org, our supported
host target operating systems ship these versions:
The following changes since commit 2b049d2c8dc01de750410f8f1a4eac498c04c723:
Merge tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu into
staging (2022-06-22 07:27:06 -0700)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you t
From: Alexander Bulekov
The non-generic-fuzz targets often time-out, or run out of memory.
Additionally, they create unreproducible bug-reports. It is possible
that this is resulting in failing coverage-reports on OSS-Fuzz. In the
future, these test-cases should be fixed, or removed.
Reviewed-by
Signed-off-by: Paolo Bonzini
---
configure | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/configure b/configure
index c9feb1a924..0fd2838e82 100755
--- a/configure
+++ b/configure
@@ -2090,6 +2090,7 @@ probe_target_compiler() {
}
write_target_makefile() {
+ echo "E
Add more pairs of bi-arch compilers, so that it is not necessary to have
e.g. both little-endian and big-endian ARM compilers.
Signed-off-by: Paolo Bonzini
---
configure | 4
1 file changed, 4 insertions(+)
diff --git a/configure b/configure
index 8f3401a23e..c9feb1a924 100755
--- a/config
Use the flags passed to the configure script for the ppc cross compiler,
which in fact default to those that are needed to get the 32-bit ISA.
Add the endianness flag so that it remains possible to use a ppc64le
compiler to compile VOF.
Signed-off-by: Paolo Bonzini
---
configure| 13
QEMU_CFLAGS is not available in pc-bios/s390-ccw/netboot.mak, but the Makefile
needs to access the flags passed to the configure script for the s390x
cross compiler. Fix everything and rename QEMU_CFLAGS to EXTRA_CFLAGS for
consistency with tests/tcg.
Reviewed-by: Thomas Huth
Signed-off-by: Paol
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> These syscalls will be used by m68k and nios2 semihosting.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/syscalls.h | 7 ++
> semihosting/syscalls.c | 137
The optionrom build is disregarding the flags passed to the configure
script via --cross-cflags-i386. Pass it down and add it to the Makefile.
This will make it possible to get the -m32 flag from $target_cflags to
force a 32-bit build on 64-bit hosts, instead of supplying manually the
arcane -Wa,
Configure is trying to fall back on cross compilers for targets that
can have bi-arch or bi-endian toolchains, but there are many corner
cases where just checking the name can go wrong. For example, the RHEL
ppc64le compiler is bi-arch and bi-endian, but multilibs are disabled.
Therefore it cannot
The Programmable Attribute Registers (PAM) of QEMU's emulated i440FX
chipset now fully support the exclusive Read Enable (RE) and Write
Enable (WE) modes by forwarding reads of the applicable PAM region to
RAM and writes to the bus or vice versa, respectively. This chipset
functionality is often u
Remove support for .code16gcc, all supported platforms have -m16.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
pc-bios/optionrom/Makefile| 15 +--
pc-bios/optionrom/code16gcc.h | 3 ---
2 files changed, 1 insertion(+), 17 deletions(-)
delete mode 100644 pc-b
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> This syscall will be used by m68k and nios2 semihosting.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/syscalls.h | 3 +++
> semihosting/syscalls.c | 42 ++
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> These syscalls will be used by m68k and nios2 semihosting.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/syscalls.h | 7 ++
> semihosting/syscalls.c | 137
Queued, thanks.
Paolo
Queued, thanks.
Paolo
With the prior patch in this series adding support for RE^WE PAM
semantics, the '#ifndef BROKEN' segments of test_i440fx_pam can now be
enabled.
Additionally:
- Verify that changing attributes does not affect the initial contents
of the PAM region;
- Verify that that the first new mask is writte
Queued, thanks.
Paolo
Queued, thanks.
Paolo
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Split out the non-ARM specific portions of SYS_SYSTEM to a
> reusable function.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/syscalls.h | 3 +++
> semihosting/arm-compat-semi.c | 12 +-
>
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Split out the non-ARM specific portions of SYS_REMOVE to a
> reusable function.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/syscalls.h | 3 +++
> semihosting/arm-compat-semi.c | 13 +--
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Split out the non-ARM specific portions of SYS_RENAME to a
> reusable function.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/syscalls.h | 4 +++
> semihosting/arm-compat-semi.c | 21 +---
Hi Eric,
>-Original Message-
>From: Eric Auger
>Sent: Friday, June 24, 2022 12:52 AM
>To: Duan, Zhenzhong
>Cc: qemu-devel@nongnu.org; m...@redhat.com; jean-phili...@linaro.org;
>pbonz...@redhat.com; Zhang, Yu C ; Dong,
>Chuanxiao ; Zhang, Tina
>
>Subject: Re: [PATCH 0/3] Add bypass mode
On 6/23/22 16:11, Jae Hyun Yoo wrote:
On 6/22/2022 11:43 PM, Cédric Le Goater wrote:
On 6/22/22 19:28, Jae Hyun Yoo wrote:
From: Graeme Gregory
Add base for Qualcomm Firework machine and add its FRU device which is
defined by DC-SCM to be fixed address 0x50.
Signed-off-by: Graeme Gregory
--
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> The ARM-specific SYS_FLEN isn't really something that can be
> reused by other semihosting apis, but there are parts that can
> reused for the implementation of semihost_sys_fstat.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
On 6/24/22 02:36, Peter Delevoryas wrote:
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
MAINTAINERS| 1 +
hw/arm/fby35.c | 54 ++
hw/arm/meson.build | 3 ++-
3 files changed, 57 insertions(+),
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