Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU

Patch title is wrong. It should be Embed CPU object in SoC as it's not QOMifies the CPU just moves it from dinamically allocated to embedded. On Mon, 8 Aug 2022, Cédric Le Goater wrote: Drop the use of ppc4xx_init() and duplicate a bit of code related to clocks in the SoC realize routine. We

Re: [PATCH v3 1/2] Update AVX512 support for xbzrle_encode_buffer function

ling xu wrote: > This commit update runtime check of AVX512, and implements avx512 of > xbzrle_encode_buffer function to accelerate xbzrle encoding speed. > Compared with C version of xbzrle_encode_buffer function, avx512 version > can achieve almost 60%-70% performance improvement on unit test

Re: [PATCH] error handling: Use TFR() macro where applicable

On Montag, 8. August 2022 14:52:28 CEST Christian Schoenebeck wrote: > On Montag, 8. August 2022 10:05:56 CEST Markus Armbruster wrote: > > Nikita Ivanov writes: > > > Summing up the discussion above, I suggest the following patch for TFR() > > > macro refactoring. (The patch is sequential to the

Re: [PATCH v3 00/22] ppc: QOM'ify 405 board

On 8/8/22 14:16, BALATON Zoltan wrote: On Mon, 8 Aug 2022, Cédric Le Goater wrote: Hello, Here is large series QOM'ifying the PPC405 board. It introduces a new generic machine and SoC models, converts the current device models to QOM and populates the SoC. The process is quite mechanical

Re: Migration tests are very slow in the CI

On Mon, Aug 08, 2022 at 02:43:49PM +0200, Thomas Huth wrote: > On 08/08/2022 14.14, Daniel P. Berrangé wrote: > > On Mon, Aug 08, 2022 at 01:57:17PM +0200, Thomas Huth wrote: > > > > > > Hi! > > > > > > Seems like we're getting more timeouts in the CI pipelines since commit > > > 2649a72555e

Re: [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC

On Mon, 8 Aug 2022, Cédric Le Goater wrote: This moves all the code previously done in the ppc405ep_init() routine under ppc405_soc_realize(). We can also adjust the number of banks now that we have control on ppc4xx_sdram_init(). Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h|

[PULL 5/5] tests/qtest: add scenario for -readconfig handling

From: Daniel P. Berrangé This test of -readconfig validates the last three regressions we have fixed with -readconfig: * Interpretation of memory size units as MiB not bytes * Allow use of [spice] * Allow use of [object] Signed-off-by: Daniel P. Berrangé Message-Id:

[PULL 0/5] Misc QEMU 7.1 fixes for 2002-08-08

The following changes since commit 3916603e0c1d909e14e09d5ebcbdaa9c9e21adf3: Merge tag 'pull-la-20220729' of https://gitlab.com/rth7680/qemu into staging (2022-07-29 17:39:17 -0700) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to

[PULL 4/5] vl: remove dead code in parse_memory_options()

mem_str will never be an empty string, because qemu_opt_get_size() fails if it encounters one: $ ./qemu-system-x86_64 -m size= qemu-system-x86_64: -m size=: Parameter size expects a non-negative number below 2^64 Optional suffix k, M, G, T, P or E means kilo-, mega-, giga-, tera-, peta-

[PULL 2/5] scsi-disk: ensure block size is non-zero and changes limited to bits 8-15

From: Mark Cave-Ayland The existing code assumes that the block size can be generated from p[1] << 8 in multiple places which ignores the top and bottom 8 bits. If the block size is allowed to be set to an arbitrary value then this causes a mismatch between the value written by the guest in the

[PULL 3/5] vl: fix [memory] section with -readconfig

The -M memory.* options do not have magic applied to them like the -m option, namely no "M" (for mebibytes) is tacked at the end of a suffixless value for "-M memory.size". This magic is performed by parse_memory_options, and we have to do it for both "-m" and the [memory] section of a config

[PULL 1/5] scsi-disk: fix overflow when block size is not a multiple of BDRV_SECTOR_SIZE

From: Mark Cave-Ayland In scsi_disk_emulate_write_same() the number of host sectors to transfer is calculated as (s->qdev.blocksize / BDRV_SECTOR_SIZE) which is then used to copy data in block size chunks to the iov buffer. Since the loop copying the data to the iov buffer uses a fixed

Re: [PATCH 7/9] parallels: Out of image offset in BAT leads to image inflation

On 08.08.2022 14:07, Alexander Ivanov wrote: When an image is opened, data_end field in BDRVParallelsState is setted as the biggest offset in the BAT plus cluster size. If there is a corrupted offset pointing outside the image, the image size increase accordingly. It potentially leads to

Re: [PATCH] error handling: Use TFR() macro where applicable

On Montag, 8. August 2022 10:05:56 CEST Markus Armbruster wrote: > Nikita Ivanov writes: > > Summing up the discussion above, I suggest the following patch for TFR() > > macro refactoring. (The patch is sequential to the first one I introduced > > in the start of the discussion). > > > >>From

Re: [BUG] cxl can not create region

On Fri, 5 Aug 2022 10:20:23 +0800 Bobo WL wrote: > Hi list > > I want to test cxl functions in arm64, and found some problems I can't > figure out. Hi Bob, Glad to see people testing this code. > > My test environment: > > 1. build latest bios from https://github.com/tianocore/edk2.git

Re: Migration tests are very slow in the CI

On 08/08/2022 14.14, Daniel P. Berrangé wrote: On Mon, Aug 08, 2022 at 01:57:17PM +0200, Thomas Huth wrote: Hi! Seems like we're getting more timeouts in the CI pipelines since commit 2649a72555e ("Allow test to run without uffd") enabled the migration tests in more scenarios. For example:

Re: [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC

On Mon, 8 Aug 2022, Cédric Le Goater wrote: It is an initial model to start QOMification of the PPC405 board. QOM'ified devices will be reintroduced one by one. Start with the memory regions, which name prefix is changed to "ppc405". Also, initialize only one RAM bank. The second bank is a

Re: [PATCH v3 04/22] ppc/ppc405: Move SRAM under the ref405ep machine

On Mon, 8 Aug 2022, Cédric Le Goater wrote: It doesn't belong to the generic machine nor the SoC. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index

Re: [PATCH 1/9] parallels: Move check of unclean image to a separate function

On 08.08.2022 14:07, Alexander Ivanov wrote: Signed-off-by: Alexander Ivanov --- block/parallels.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index a229c06f25..108aa907b8 100644 ---

[PATCH 1/2] hw/cxl: Fix memory leak in error paths

Use g_autofree to free the CXLFixedWindow structure if an error occurs in configuration before we have added to the list (via g_steal_pointer()) Fix Coverity CID: 1488872 Reported-by: Peter Maydell Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-host.c | 5 +++-- 1 file changed, 3

Re: [PATCH 8/9] parallels: Replace bdrv_co_pwrite_sync by bdrv_co_flush for BAT flushing

On 08.08.2022 14:07, Alexander Ivanov wrote: It's too costly to write all the BAT to the disk. Let the flush function write only dirty blocks. Signed-off-by: Alexander Ivanov --- block/parallels.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/parallels.c

Re: [PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine

On Mon, 8 Aug 2022, Cédric Le Goater wrote: Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Reviewed-by: BALATON Zoltan --- hw/ppc/ppc405_boards.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git

Re: [PATCH 2/9] parallels: Move check of cluster outside image to a separate function

On 08.08.2022 14:19, Denis V. Lunev wrote: On 08.08.2022 14:07, Alexander Ivanov wrote: Signed-off-by: Alexander Ivanov ---   block/parallels.c | 76 +--   1 file changed, 53 insertions(+), 23 deletions(-) diff --git a/block/parallels.c

[PATCH 2/2] hw/cxl: Fix wrong query of target ports

Two issues were present in this code: 1) Check on which register to look in was inverted. 2) Both branches use the _LO register. Whilst here moved to extract32() rather than hand rolling the field extraction as simpler and hopefully less error prone. Fixes Coverity CID: 1488873 Reported-by:

Re: [PATCH 5/9] parallels: Move statistic collection to a separate function

On 08.08.2022 14:07, Alexander Ivanov wrote: Signed-off-by: Alexander Ivanov --- block/parallels.c | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index 0edbb812dd..b0982d60d0 100644 --- a/block/parallels.c

Re: [PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine

On Mon, 8 Aug 2022, Cédric Le Goater wrote: We will use this machine as a base to define the ref405ep and possibly the PPC405 hotfoot board as found in the Linux kernel. Signed-off-by: Cédric Le Goater Reviewed-by: BALATON Zoltan --- hw/ppc/ppc405_boards.c | 31

Re: [PATCH v3 00/22] ppc: QOM'ify 405 board

On Mon, 8 Aug 2022, Cédric Le Goater wrote: Hello, Here is large series QOM'ifying the PPC405 board. It introduces a new generic machine and SoC models, converts the current device models to QOM and populates the SoC. The process is quite mechanical without too much issues to handle. The noisy

[PATCH 6/9] parallels: Replace qemu_co_mutex_lock by WITH_QEMU_LOCK_GUARD

Replace the way that we use mutex in parallels_co_check() for more clean code. Signed-off-by: Alexander Ivanov --- block/parallels.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index b0982d60d0..3cb5452613 100644 ---

Re: [PATCH 9/9] parallels: Merge parallels_check_fragmentation to parallels_collect_statistics

On 08.08.2022 14:07, Alexander Ivanov wrote: Frgamentation is a part of statistics so it is better to count the statistics in one function. Signed-off-by: Alexander Ivanov --- block/parallels.c | 31 --- 1 file changed, 8 insertions(+), 23 deletions(-) diff

[PATCH 0/2] hw/cxl: Two CXL emulation fixes.

Peter Maydell reported both these issues, having looked into Coverity identified issues. The memory leak was straight forward, but testing the second patch identified a bug in the Linux kernel. This bug has been fixed in the series

Re: Migration tests are very slow in the CI

On Mon, Aug 08, 2022 at 01:57:17PM +0200, Thomas Huth wrote: > > Hi! > > Seems like we're getting more timeouts in the CI pipelines since commit > 2649a72555e ("Allow test to run without uffd") enabled the migration tests > in more scenarios. > > For example: > >

[PATCH 5/9] parallels: Move statistic collection to a separate function

Signed-off-by: Alexander Ivanov --- block/parallels.c | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index 0edbb812dd..b0982d60d0 100644 --- a/block/parallels.c +++ b/block/parallels.c @@ -553,13 +553,29 @@

Re: [PATCH 2/9] parallels: Move check of cluster outside image to a separate function

On 08.08.2022 14:07, Alexander Ivanov wrote: Signed-off-by: Alexander Ivanov --- block/parallels.c | 76 +-- 1 file changed, 53 insertions(+), 23 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index 108aa907b8..7b400ecdcc 100644

[PATCH 4/9] parallels: Move check of fragmentation to a separate function

Signed-off-by: Alexander Ivanov --- block/parallels.c | 38 +- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index 6d4cfb738b..0edbb812dd 100644 --- a/block/parallels.c +++ b/block/parallels.c @@ -530,12

Re: [PATCH for-7.1] hw/mips/malta: turn off x86 specific features of PIIX4_PM

On Wed, 3 Aug 2022 19:26:30 +0200 Bernhard Beschow wrote: > On Tue, Aug 2, 2022 at 8:37 AM Philippe Mathieu-Daudé via < > qemu-devel@nongnu.org> wrote: > > > On 28/7/22 15:16, Igor Mammedov wrote: > > > On Thu, 28 Jul 2022 13:29:07 +0100 > > > Peter Maydell wrote: > > > > > >> On Thu, 28

[PATCH 9/9] parallels: Merge parallels_check_fragmentation to parallels_collect_statistics

Frgamentation is a part of statistics so it is better to count the statistics in one function. Signed-off-by: Alexander Ivanov --- block/parallels.c | 31 --- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index

[PATCH 8/9] parallels: Replace bdrv_co_pwrite_sync by bdrv_co_flush for BAT flushing

It's too costly to write all the BAT to the disk. Let the flush function write only dirty blocks. Signed-off-by: Alexander Ivanov --- block/parallels.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/block/parallels.c b/block/parallels.c index 72cf7499c1..38b1482e81 100644

[PATCH 3/9] parallels: Move check of leaks to a separate function

Signed-off-by: Alexander Ivanov --- block/parallels.c | 96 --- 1 file changed, 58 insertions(+), 38 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index 7b400ecdcc..6d4cfb738b 100644 --- a/block/parallels.c +++ b/block/parallels.c @@

[PATCH 2/9] parallels: Move check of cluster outside image to a separate function

Signed-off-by: Alexander Ivanov --- block/parallels.c | 76 +-- 1 file changed, 53 insertions(+), 23 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index 108aa907b8..7b400ecdcc 100644 --- a/block/parallels.c +++ b/block/parallels.c @@

[PATCH 7/9] parallels: Out of image offset in BAT leads to image inflation

When an image is opened, data_end field in BDRVParallelsState is setted as the biggest offset in the BAT plus cluster size. If there is a corrupted offset pointing outside the image, the image size increase accordingly. It potentially leads to attempts to create a file size of petabytes. Set the

[PATCH 0/9] parallels: Refactor the code of images checks and fix a bug

We will add more and more checks of images so we need to reorganize the code. Put each check to a separate helper function with a separate loop. Replace qemu_co_mutex_lock by WITH_QEMU_LOCK_GUARD for more clean code. Fix a bug when out of image offset in BAT leads to image inflation. Replace

[PATCH 1/9] parallels: Move check of unclean image to a separate function

Signed-off-by: Alexander Ivanov --- block/parallels.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/block/parallels.c b/block/parallels.c index a229c06f25..108aa907b8 100644 --- a/block/parallels.c +++ b/block/parallels.c @@ -413,6 +413,23 @@

Re: VGA hardware cursor query

On Sun, 7 Aug 2022, BALATON Zoltan wrote: On Sun, 7 Aug 2022, Mark Cave-Ayland wrote: On 07/08/2022 12:47, Elliot Nunn wrote: I want to give Mac OS 9 clients access to hardware cursor support, to improve responsiveness in absolute-cursor mode. Would it be acceptable to add a hardware cursor

Migration tests are very slow in the CI

Hi! Seems like we're getting more timeouts in the CI pipelines since commit 2649a72555e ("Allow test to run without uffd") enabled the migration tests in more scenarios. For example: https://gitlab.com/qemu-project/qemu/-/jobs/2821578332#L49 You can see that the migration-test ran for

Re: [PATCH v3 0/2] This patch updates runtime check of AVX512

ling xu wrote: > This patch updates runtime check of AVX512 and update avx512 support for > xbzrle_encode_buffer function to accelerate xbzrle encoding speed. > > The runtime check is updated in meson.build and meson_options.txt. > > The updated AVX512 algorithm is provided in ram.c, xbzrle.c and

Re: [PATCH for-7.2 04/10] ppc/pnv: add helpers for pnv-phb user devices

On 8/5/22 07:41, Frederic Barrat wrote: On 03/08/2022 15:44, Daniel Henrique Barboza wrote: pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices". They are needed to amend the

[PATCH v3 22/22] ppc/ppc4xx: Fix sdram trace events

Signed-off-by: Cédric Le Goater --- hw/ppc/ppc4xx_devs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 3cb6d0e66eff..5d5626c0506d 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -175,7 +175,7 @@ static void

[PATCH v3 16/22] ppc/ppc405: QOM'ify POB

POB is currently modeled as a simple DCR device. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 12 +++ hw/ppc/ppc405_uc.c | 50 ++ 2 files changed, 40 insertions(+), 22 deletions(-) diff --git

[PATCH v3 20/22] ppc/ppc405: Use an explicit PPCUIC object

Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 3 ++- hw/ppc/ppc405_uc.c | 26 +- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 31c94e474209..8e67ad0b72c3 100644

Re: [PATCH] xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command

On Mon, Aug 8, 2022 at 6:09 PM Qiang Liu wrote: > > In xlnx_dp_aux_set_command, when the command leads to the default > branch, xlxn-dp will abort and then crash. > > This patch removes this abort and drops this operation. > > Fixes: 58ac482 ("introduce xlnx-dp") > Resolves:

[PATCH v3 13/22] ppc/ppc405: QOM'ify DMA

The GPIO controller is currently modeled as a DCR device with a couple of IRQs. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 19 ++ hw/ppc/ppc405_uc.c | 141 - 2 files changed, 81 insertions(+),

[PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA

Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 55 +- 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 5ba12d60bc00..195aa58c35ad

[PATCH v3 18/22] ppc/ppc405: QOM'ify MAL

The Memory Access Layer (MAL) controller is currently modeled as a DCR device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 1 + include/hw/ppc/ppc4xx.h |

[PATCH v3 10/22] ppc/ppc405: QOM'ify GPT

The GPT controller is currently modeled as a SysBus device with a unique memory region, a couple of IRQs and a timer. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 22 hw/ppc/ppc405_uc.c | 90

[PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO

The GPIO controller is currently modeled as a simple SysBus device with a unique memory region. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 21 +++ hw/ppc/ppc405_uc.c | 50 +- 2 files

[PATCH v3 21/22] ppc/ppc405: Use an explicit I2C object

Having an explicit I2C model object will help if one day we want to add I2C devices on the bus from the machine init routine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 2 ++ hw/ppc/ppc405_uc.c | 10 -- 2 files changed, 10

[PATCH v3 17/22] ppc/ppc405: QOM'ify PLB

PLB is currently modeled as a simple DCR device. Also drop the ppc4xx_plb_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 14 +-- hw/ppc/ppc405_uc.c | 58

[PATCH v3 09/22] ppc/ppc405: QOM'ify CPC

The OCM controller is currently modeled as a DCR device. Now that all clock settings are handled at the CPC level, change the SoC "sys-clk" property to be an alias on the same property in the CPC model. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h

[PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model

The Device Control Registers (DCR) of on-SoC devices are accessed by software through the use of the mtdcr and mfdcr instructions. These are converted in transactions on a side band bus, the DCR bus, which connects the on-SoC devices to the CPU. Ideally, we should model these accesses with a DCR

[PATCH v3 07/22] ppc/ppc405: QOM'ify CPU

Drop the use of ppc4xx_init() and duplicate a bit of code related to clocks in the SoC realize routine. We will clean that up in the following patches. ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe this could be done in model initializer of the CPU families needing it.

[PATCH v3 14/22] ppc/ppc405: QOM'ify EBC

EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 17 +- hw/ppc/ppc405_uc.c | 56

[PATCH v3 15/22] ppc/ppc405: QOM'ify OPBA

The OPB arbitrer is currently modeled as a simple SysBus device with a unique memory region. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 12 hw/ppc/ppc405_uc.c | 47 +++--- 2 files changed,

[PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC

This moves all the code previously done in the ppc405ep_init() routine under ppc405_soc_realize(). We can also adjust the number of banks now that we have control on ppc4xx_sdram_init(). Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 12 ++-- hw/ppc/ppc405_boards.c | 12 ++--

[PATCH v3 04/22] ppc/ppc405: Move SRAM under the ref405ep machine

It doesn't belong to the generic machine nor the SoC. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index f4794ba40ce6..c6fa559b03d9 100644 ---

[PATCH v3 11/22] ppc/ppc405: QOM'ify OCM

The OCM controller is currently modeled as a simple DCR device with a couple of memory regions. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 16 +++ hw/ppc/ppc405_uc.c | 72 +++--- 2 files changed,

[PATCH v3 00/22] ppc: QOM'ify 405 board

Hello, Here is large series QOM'ifying the PPC405 board. It introduces a new generic machine and SoC models, converts the current device models to QOM and populates the SoC. The process is quite mechanical without too much issues to handle. The noisy part is the initial patch introducing the

[PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC

It is an initial model to start QOMification of the PPC405 board. QOM'ified devices will be reintroduced one by one. Start with the memory regions, which name prefix is changed to "ppc405". Also, initialize only one RAM bank. The second bank is a dummy one (zero size) which is here to match the

[PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine

Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 96700be74d08..f4794ba40ce6 100644 ---

[PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine

We will use this machine as a base to define the ref405ep and possibly the PPC405 hotfoot board as found in the Linux kernel. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 31 --- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git

[PATCH v3 01/22] ppc/ppc405: Remove taihu machine

It has been deprecated since 7.0. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- docs/about/deprecated.rst | 9 -- docs/about/removed-features.rst | 6 + docs/system/ppc/embedded.rst| 1 - hw/ppc/ppc405_boards.c | 232

Re: [PATCH v5 5/8] blockdev: Add a new IF type IF_OTHER

Adding Paolo and Eduardo since we're wandering into QOM-land. Kevin Wolf writes: > Am 08.08.2022 um 08:26 hat Markus Armbruster geschrieben: >> Daniel P. Berrangé writes: >> >> > On Thu, Aug 04, 2022 at 05:30:40PM +0200, Markus Armbruster wrote: >> >> Daniel P. Berrangé writes: >> >> >> >>

[PATCH 2/2] virtio-blk: replace dataplane_start/stopping/started with enum

Virtio-blk uses VirtIOBlockDataPlane and VirtIOBlock to keep track of the dataplane flags. This is completely unnecessary, as both structures are always accessed together and we can simplify the sages with an enum. Read/write the enum atomically, as it can be read also by iothread callbacks.

[PATCH 0/2] virtio-blk and scsi: replace dataplane_{start/stopping/started}

The way the dataplane stages at startup and stop are monitored is unnecessary complicated. In virtio-scsi we have dataplane_started, dataplane_starting and dataplane_stopping in VirtIOSCSI. In virtio-blk we have dataplene_started in VirtIOBlock, and starting and stopping in VirtIOBlockDataPlane.

[PATCH 1/2] virtio-scsi: replace VirtIOBlock dataplane_{start/starting/stopped} with enum

Simplify the various dataplane stages in dataplane_start/stop by using a single enum instead of having multiple flags. Read/write the enum atomically, as it can be read also by iothread callbacks. Signed-off-by: Emanuele Giuseppe Esposito --- hw/scsi/virtio-scsi-dataplane.c | 21

Re: [PATCH] xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command

Le 08/08/2022 à 10:01, Qiang Liu a écrit : In xlnx_dp_aux_set_command, when the command leads to the default branch, xlxn-dp will abort and then crash. This patch removes this abort and drops this operation. Fixes: 58ac482 ("introduce xlnx-dp") Resolves:

Re: [PATCH v2 2/7] multifd: modifying 'migrate' qmp command to add multifd socket on particular src and dest pair

On Thu, Jul 28, 2022 at 08:32:39PM +0530, Het Gala wrote: > > On 26/07/22 4:43 pm, Daniel P. Berrangé wrote: > > On Thu, Jul 21, 2022 at 07:56:15PM +, Het Gala wrote: > > > i) Modified the format of the qemu monitor command : 'migrate' by adding > > > a list, > > > each element in the

Re: [PATCH v2 2/7] multifd: modifying 'migrate' qmp command to add multifd socket on particular src and dest pair

On Mon, Aug 08, 2022 at 11:41:21AM +0530, Het Gala wrote: > > On 02/08/22 1:23 pm, Markus Armbruster wrote: > > Het Gala writes: > > > > > On 26/07/22 4:43 pm, Daniel P. Berrangé wrote: > > > > On Thu, Jul 21, 2022 at 07:56:15PM +, Het Gala wrote: > > > > > i) Modified the format of the

Re: [PATCH 1/2] hw/arm/virt: Improve address assignment for highmem IO regions

On Wed, 03 Aug 2022 14:02:04 +0100, Gavin Shan wrote: > > Hi Marc, > > On 8/3/22 5:01 PM, Marc Zyngier wrote: > > On Wed, 03 Aug 2022 04:01:04 +0100, > > Gavin Shan wrote: > >> On 8/2/22 7:41 PM, Eric Auger wrote: > >>> On 8/2/22 08:45, Gavin Shan wrote: > There are 3 highmem IO regions

RE: [PATCH] xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command

> -Original Message- > From: Qemu-devel bounces+fkonrad=amd@nongnu.org> On Behalf Of Qiang Liu > Sent: 08 August 2022 08:55 > To: qemu-devel@nongnu.org > Cc: Qiang Liu ; Thomas Huth ; > Alistair Francis ; Edgar E. Iglesias > ; Peter Maydell ; > open list:Xilinx ZynqMP and... >

RE: [PATCH for-7.1] hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses

> -Original Message- > From: Peter Maydell > Sent: 02 August 2022 15:34 > To: Konrad, Frederic > Cc: qemu-devel@nongnu.org; Fabien Chouteau ; > Frederic Konrad ; f4...@amsat.org > Subject: Re: [PATCH for-7.1] hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 > bit accesses > > On Tue, 2 Aug

[PATCH v2 5/8] target/i386/intel-pt: Rework/rename the default INTEL-PT feature set

Historically the Intel PT feature set reported from ICX silicon was chosen as the fixed feature set for Intel PT. If want to enable and expose INTEL-PT to guest, the supported Intel PT reported by host must cover the fixed feature set, which are named with MINIMAL in INTEL_PT_MINIMAL_EBX and

[PATCH v2 3/8] target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID leaf 0xD

CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and capability of Intel PT. Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX and FEAT_14_1_EBX, and complete FEAT_14_0_ECX. Thus all the features of Intel PT can be expanded when "-cpu host/max" and can be configured in named CPU model.

[PATCH v2 4/8] target/i386/intel-pt: print special message for INTEL_PT_ADDR_RANGES_NUM

Bit[2:0] of CPUID.14H_01H:EAX stands as a whole for the number of INTEL PT ADDR RANGES. For unsupported value that exceeds what KVM reports, report it as a whole in mark_unavailable_features() as well. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 9 - 1 file changed, 8

[PATCH v2 0/8] Make Intel PT configurable

Initial virtualization of Intel PT was added by making it as fixed feature set of ICX's capabilities. However, it breaks the Intel PT exposure on SPR machine because SPR has less PT capabilities of CPUID(0x14,1):EBX[15:0]. This series aims to make Intel PT configurable that named CPU model can

[PATCH v2 6/8] target/i386/intel-pt: Enable host pass through of Intel PT

commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support") added the support of Intel PT by making CPUID[14] of PT as fixed feature set (from ICX) for any CPU model on any host. This truly breaks the PT exposure on Intel SPR platform because SPR has less supported bitmap of

[PATCH v2 8/8] target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration

KVM only allows userspace to access legal number of MSR_IA32_RTIT_ADDRn, which is enumrated by guest's CPUID(0x14,0x1):EAX[2:0], i.e., env->features[FEAT_14_1_EAX] & INTEL_PT_ADDR_RANGES_NUM_MASK Signed-off-by: Xiaoyao Li --- target/i386/cpu.h | 2 ++ target/i386/kvm/kvm.c | 8 2

[PATCH v2 1/8] target/i386: Print CPUID subleaf info for unsupported feature

Some CPUID leaves have meaningful subleaf index. Print the subleaf info in feature_word_description for CPUID features. Signed-off-by: Xiaoyao Li Reviewed-by: Eduardo Habkost --- target/i386/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c

[PATCH v2 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge

For IceLake-server, it's just the same as using the default PT feature set since the default one is exact taken from ICX. For Snowridge, define it according to real SNR silicon capabilities. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 18 ++ 1 file changed, 18

[PATCH v2 2/8] target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK

Per Intel SDM, bits 2:0 of CPUID(0x14,0x1).EAX indicate the number of address ranges for INTEL-PT. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f9646e16b872..fa02910ce811 100644

[PATCH] xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command

In xlnx_dp_aux_set_command, when the command leads to the default branch, xlxn-dp will abort and then crash. This patch removes this abort and drops this operation. Fixes: 58ac482 ("introduce xlnx-dp") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/411 Reported-by: Qiang Liu Tested-by:

Re: [PATCH v5 5/8] blockdev: Add a new IF type IF_OTHER

Am 08.08.2022 um 08:26 hat Markus Armbruster geschrieben: > Daniel P. Berrangé writes: > > > On Thu, Aug 04, 2022 at 05:30:40PM +0200, Markus Armbruster wrote: > >> Daniel P. Berrangé writes: > >> > >> > On Thu, Aug 04, 2022 at 04:56:15PM +0200, Markus Armbruster wrote: > >> >> Daniel P.

RE: [PATCH v3 2/2] Test code for AVX512 support for xbzrle_encode_buffer

Hi, Thomas, Thanks for your reply. This test code can only work on system supporting avx512. It's reasonably to add condition check in test code to, agree to your suggestion. I'll add condition check in test code later. Best Regards Ling -Original Message- From: Thomas Huth

Re: [PATCH] error handling: Use TFR() macro where applicable

Good point, thank you! I think it's a bad idea to keep it like I proposed. Though, could I just copy the definition that Markus has posted or there are any objections? On Mon, Aug 8, 2022 at 11:06 AM Markus Armbruster wrote: > Nikita Ivanov writes: > > > Summing up the discussion above, I

Re: [PATCH] xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command

On 08/08/2022 10.01, Qiang Liu wrote: In xlnx_dp_aux_set_command, when the command leads to the default branch, xlxn-dp will abort and then crash. This patch removes this abort and drops this operation. Fixes: 58ac482 ("introduce xlnx-dp") Resolves:

Re: [PATCH v3 2/2] Test code for AVX512 support for xbzrle_encode_buffer

On 08/08/2022 09.48, ling xu wrote: Signed-off-by: ling xu Co-authored-by: Zhou Zhao Co-authored-by: Jun Jin --- tests/unit/test-xbzrle.c | 307 --- 1 file changed, 290 insertions(+), 17 deletions(-) diff --git a/tests/unit/test-xbzrle.c

[PATCH] xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command

In xlnx_dp_aux_set_command, when the command leads to the default branch, xlxn-dp will abort and then crash. This patch removes this abort and drops this operation. Fixes: 58ac482 ("introduce xlnx-dp") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/411 Reported-by: Qiang Liu Tested-by:

Re: [PATCH] error handling: Use TFR() macro where applicable

Nikita Ivanov writes: > Summing up the discussion above, I suggest the following patch for TFR() > macro refactoring. (The patch is sequential to the first one I introduced > in the start of the discussion). > >>From 6318bee052900aa93bba6620b53c7cb2290e5001 Mon Sep 17 00:00:00 2001 > From:

[PATCH v3 2/2] Test code for AVX512 support for xbzrle_encode_buffer

Signed-off-by: ling xu Co-authored-by: Zhou Zhao Co-authored-by: Jun Jin --- tests/unit/test-xbzrle.c | 307 --- 1 file changed, 290 insertions(+), 17 deletions(-) diff --git a/tests/unit/test-xbzrle.c b/tests/unit/test-xbzrle.c index ef951b6e54..653016826f

[PATCH v3 0/2] This patch updates runtime check of AVX512

This patch updates runtime check of AVX512 and update avx512 support for xbzrle_encode_buffer function to accelerate xbzrle encoding speed. The runtime check is updated in meson.build and meson_options.txt. The updated AVX512 algorithm is provided in ram.c, xbzrle.c and xbzrle.h. The test code

[PATCH v3 1/2] Update AVX512 support for xbzrle_encode_buffer function

This commit update runtime check of AVX512, and implements avx512 of xbzrle_encode_buffer function to accelerate xbzrle encoding speed. Compared with C version of xbzrle_encode_buffer function, avx512 version can achieve almost 60%-70% performance improvement on unit test provided by Qemu. In

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