If the vhost memory layout doesn't change, don't need to call the vhost
backend.
The set_mem_table is time consuming when sending to vhost-user backend.
On aarch64, the edk2 uefi firmware will write the pflash which will
trigger the vhost_commit hundreds of times.
Signed-off-by: Li Feng
---
While there are no target-specific nonfaulting probes,
generic code may grow some uses at some point.
Note that the attrs argument was incorrect -- it should have
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 46
Stefan Hajnoczi 于2022年8月23日周二 07:05写道：
>
> On Tue, Aug 16, 2022 at 02:25:16PM +0800, Sam Li wrote:
> > +static int hdev_get_max_segments(int fd, struct stat *st) {
> > +int ret;
> > +if (S_ISCHR(st->st_mode)) {
> > +if (ioctl(fd, SG_GET_SG_TABLESIZE, ) == 0) {
>
> The ioctl must
Stefan Hajnoczi 于2022年8月23日周二 08:54写道：
>
> On Tue, Aug 16, 2022 at 02:25:20PM +0800, Sam Li wrote:
> > Putting zoned/non-zoned BlockDrivers on top of each other is not
> > allowed.
> >
> > Signed-off-by: Sam Li
> > Reviewed-by: Stefan Hajnoczi
> > ---
> > block.c | 14
Stefan Hajnoczi 于2022年8月23日周二 08:49写道：
>
> On Tue, Aug 16, 2022 at 02:25:18PM +0800, Sam Li wrote:
> > By adding zone management operations in BlockDriver, storage controller
> > emulation can use the new block layer APIs including Report Zone and
> > four zone management operations (open, close,
On Fri, Aug 19, 2022 at 6:35 PM Eugenio Perez Martin
wrote:
>
> On Fri, Aug 19, 2022 at 11:01 AM Jason Wang wrote:
> >
> > On Fri, Aug 19, 2022 at 4:30 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Fri, Aug 19, 2022 at 8:29 AM Jason Wang wrote:
> > > >
> > > > On Thu, Aug 11, 2022 at 2:42
> -Original Message-
> From: Jason Wang
> Sent: Tuesday, August 23, 2022 10:03 AM
> To: Zhang, Chen
> Cc: Peter Maydell ; Li Zhijian
> ; qemu-dev
> Subject: Re: [PATCH V5] net/colo.c: Fix the pointer issue reported by
> Coverity.
>
> On Mon, Aug 22, 2022 at 4:29 PM Zhang Chen
On 8/22/22 16:57, Richard Henderson wrote:
This patch set does two things:
(1) Remove assert(!probe) from the x86 tlb_fill
It turns out that this is a prerequisite for
[PATCH v6 00/21] linux-user: Fix siginfo_t contents when jumping
to non-readable pages
because of a new
On Mon, Aug 22, 2022 at 4:29 PM Zhang Chen wrote:
>
> When enabled the virtio-net-pci, guest network packet will
> load the vnet_hdr. In COLO status, the primary VM's network
> packet maybe redirect to another VM, it needs filter-redirect
> enable the vnet_hdr flag at the same time, COLO-proxy
Forgot to append changelog for v2 in the cover letter, so I add it in
this email.
changelog:
1. Add support for vhost-net scenario
2. Add a new vhost-user message VHOST_USER_RESET_VRING
3. Add migration compatibility for virtqueue reset
Looking forward to your review and comments to this
On Wed, Aug 17, 2022 at 10:27:19AM -0500,
Michael Roth wrote:
> > I think the best approach is to turn KVM_TDX_INIT_MEM_REGION into a generic
> > vCPU-scoped ioctl() that allows userspace to pre-map guest memory.
> > Supporting
> > initializing guest private memory with a source page can be
On Tue, Aug 16, 2022 at 02:25:20PM +0800, Sam Li wrote:
> Putting zoned/non-zoned BlockDrivers on top of each other is not
> allowed.
>
> Signed-off-by: Sam Li
> Reviewed-by: Stefan Hajnoczi
> ---
> block.c | 14 ++
> block/raw-format.c | 1 +
On Tue, Aug 16, 2022 at 02:25:18PM +0800, Sam Li wrote:
> By adding zone management operations in BlockDriver, storage controller
> emulation can use the new block layer APIs including Report Zone and
> four zone management operations (open, close, finish, reset).
>
> Add zoned storage commands
On Tue, 23 Aug 2022, Bernhard Beschow wrote:
Resolves duplicate code in the boards.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 16
hw/mips/fuloong2e.c | 4
hw/ppc/pegasos2.c | 4
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git
On Wed, Aug 17, 2022 at 9:24 AM Atish Patra wrote:
>
> From: Atish Patra
>
> Qemu can monitor the following cache related PMU events through
> tlb_fill functions.
>
> 1. DTLB load/store miss
> 3. ITLB prefetch miss
>
> Increment the PMU counter in tlb_fill function.
>
> Reviewed-by: Alistair
On Tue, 23 Aug 2022, Bernhard Beschow wrote:
The object creation now happens in chip-specific init methods which
allows the realize methods to be consolidated into one method. Shifting
the logic into the init methods has the addidional advantage that the
parent object's init methods are called
Use MMU_NESTED_IDX for each memory access, rather than
just a single translation to physical. Adjust svm_save_seg
and svm_load_seg to pass in mmu_idx.
This removes the last use of get_hphys so remove it.
Signed-off-by: Richard Henderson
---
target/i386/cpu.h| 2 -
On Tue, 23 Aug 2022, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 47f2fd2669..ee745d5d49 100644
--- a/hw/isa/vt82c686.c
+++
Replace int is_write1 and magic numbers with the proper
MMUAccessType access_type and enumerators.
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/excp_helper.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git
Use a boolean to control the call to get_hphys instead
of passing a null function pointer.
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/excp_helper.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/i386/tcg/sysemu/excp_helper.c
Allow the target to cache items from the guest page tables.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 5e12cc1854..67239b4e5e 100644
---
We don't need one variable set per translation level,
which requires copying into pte/pte_addr for huge pages.
Standardize on pte/pte_addr for all levels.
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/excp_helper.c | 178 ++-
1 file changed, 91
Now that we have collected all of the page data into
CPUTLBEntryFull, provide an interface to record that
all in one go, instead of using 4 arguments. This interface
allows CPUTLBEntryFull to be extended without having to
change the number of arguments.
Signed-off-by: Richard Henderson
---
This patch set does two things:
(1) Remove assert(!probe) from the x86 tlb_fill
It turns out that this is a prerequisite for
[PATCH v6 00/21] linux-user: Fix siginfo_t contents when jumping
to non-readable pages
because of a new use of probe_access(..., nonfault)
when
Add an interface to return the CPUTLBEntryFull struct
that goes with the lookup. The result is not intended
to be valid across multiple lookups, so the user must
use the results immediately.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 11 +++
accel/tcg/cputlb.c
These new mmu indexes will be helpful for improving
paging and code throughout the target.
Signed-off-by: Richard Henderson
---
target/i386/cpu-param.h | 2 +-
target/i386/cpu.h| 3 +
target/i386/tcg/sysemu/excp_helper.c | 82 ++--
All callers pass s->base.pc_next and s->pc, which we can just
as well compute within the functions. Pull out common helpers
and reduce the amount of code under macros.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 116 ++--
1 file changed,
When PAGE_WRITE_INV is set when calling tlb_set_page,
we immediately set TLB_INVALID_MASK in order to force
tlb_fill to be called on the next lookup. Here in
probe_access_internal, we have just called tlb_fill
and eliminated true misses, thus the lookup must be valid.
This allows us to remove a
Use probe_access_full in order to resolve to a host address,
which then lets us use a host cmpxchg to update the pte.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/279
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/excp_helper.c | 242 +++
1 file
Create TranslateParams for inputs, TranslateResults for successful
outputs, and TranslateFault for error outputs; return true on success.
Move stage1 error paths from handle_mmu_fault to x86_cpu_tlb_fill;
reorg the rest of handle_mmu_fault into get_physical_address.
Signed-off-by: Richard
With gen_jmp_rel, we may chain to the next tb
instead of merely writing to eip and exiting.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 21 ++---
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/target/i386/tcg/translate.c
Drop the unused dest argument to gen_jr().
Remove most of the calls to gen_jr, and use DISAS_JUMP.
Remove some unused loads of eip for lcall and ljmp.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 24 +---
1 file changed, 13 insertions(+), 11
This structure will shortly contain more than just
data for accessing MMIO. Rename the 'addr' member
to 'xlat_section' to more clearly indicate its purpose.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h| 22
accel/tcg/cputlb.c | 102
Subtract cur_insn_len to restart the current insn.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 6d6c751c10..67c803263b 100644
---
Replace with PTE_HPHYS for the page table walk, and a direct call
to mmu_translate for the final stage2 translation. Hoist the check
for HF2_NPT_MASK out to get_physical_address, which avoids the
recursive call when stage2 is disabled.
We can now return all the way out to x86_cpu_tlb_fill before
Create a common helper for pc-relative branches.
The jmp jb insn was missing a mask for CODE32.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 57 ++---
1 file changed, 27 insertions(+), 30 deletions(-)
diff --git
We can set is_jmp early, using only one if, and let that
be overwritten by gen_repz_* etc.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 42 +
1 file changed, 10 insertions(+), 32 deletions(-)
diff --git a/target/i386/tcg/translate.c
This field is only written, not read; remove it.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 1 -
accel/tcg/cputlb.c| 7 +++
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 500503da13..9e47184513 100644
With gen_jmp_rel, we may chain between two translation blocks
which may only be separated because of TB size limits.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
Replace lone calls to gen_eob() with the new enumerator.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 73e4330fc0..1dc3ff67ae
Signed-off-by: Richard Henderson
---
target/i386/cpu-param.h | 1 +
target/i386/tcg/tcg-cpu.c | 8 ++--
target/i386/tcg/translate.c | 86 ++---
3 files changed, 77 insertions(+), 18 deletions(-)
diff --git a/target/i386/cpu-param.h
Create helpers for loading the address of the next insn.
Use tcg_constant_* in adjacent code where convenient.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 44 +++--
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git
Create common routines for computing the length of the insn.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index
Instead of returning the new pc, which is present in
DisasContext, return true if an insn was translated.
This is false when we detect a page crossing and must
undo the insn under translation.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 42
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 846040c1ab..6192a3e30e 100644
--- a/target/i386/tcg/translate.c
+++
Use i32 not int or tl for eip and cs arguments.
Signed-off-by: Richard Henderson
---
target/i386/helper.h | 2 +-
target/i386/tcg/seg_helper.c | 6 ++
target/i386/tcg/translate.c | 3 ++-
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/i386/helper.h
Sync EIP before exiting a translation block.
Replace all gen_jmp_im that use s->pc.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 45 -
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/target/i386/tcg/translate.c
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 ++
target/arm/translate.h | 6
target/arm/cpu.c | 23 +++---
target/arm/translate-a64.c | 37 ++-
target/arm/translate.c | 62 ++
5 files
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 57 -
1 file changed, 18 insertions(+), 39 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 59e7596629..6d6c751c10 100644
---
Replace sequences of gen_update_cc_op, gen_update_eip_next,
and gen_eob with the new is_jmp enumerator.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 40 -
1 file changed, 13 insertions(+), 27 deletions(-)
diff --git
Like gen_update_cc_op, sync EIP before doing something
that could raise an exception. Replace all gen_jmp_im
that use s->base.pc_next.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 52 -
1 file changed, 28 insertions(+), 24 deletions(-)
All callers pass s->base.pc_next and s->pc, which we can just
as well compute within the function.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/i386/tcg/translate.c
Set is_jmp properly in gen_movl_seg_T0, so that the callers
need to nothing special.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 36 +---
1 file changed, 5 insertions(+), 31 deletions(-)
diff --git a/target/i386/tcg/translate.c
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
All callers pass s->base.pc_next - s->cs_base, which we can just
as well compute within the function. Note the special case of
EXCP_VSYSCALL in which s->cs_base didn't have the subtraction,
but cs_base is always zero in 64-bit mode, when vsyscall is used.
Signed-off-by: Richard Henderson
---
Add a few DISAS_TARGET_* aliases to reduce the number of
calls to gen_eob() and gen_eob_inhibit_irq(). So far,
only update i386_tr_translate_insn for exiting the block
because of single-step or previous inhibit irq.
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 23
Based-on: <20220822232338.1727934-1-richard.hender...@linaro.org>
("[PATCH v3 00/17] accel/tcg + target/arm: pc-relative translation")
Improve translation with address space randomization.
Before:
gen code size 232687283/1073577984
TB count434021
TB flush count 1
TB
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 4 ++--
target/arm/translate-a64.c| 28 +++--
target/arm/translate-m-nocp.c | 6 +++---
target/arm/translate-mve.c| 2 +-
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 35 ---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Wrap the bare TranslationBlock pointer into a structure.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 8 ++--
accel/tcg/cpu-exec.c | 9 ++---
accel/tcg/cputlb.c| 2 +-
accel/tcg/translate-all.c | 4 ++--
4 files changed, 15 insertions(+), 8 deletions(-)
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 41 +++---
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 6 +++---
target/arm/translate.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-a64.c
Use the pc coming from db->pc_first rather than the TB.
Use the cached host_addr rather than re-computing for the
first page. We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.
A simple helper to retrieve the length of the current insn.
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 5 +
target/arm/translate-vfp.c | 2 +-
target/arm/translate.c | 5 ++---
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.h
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 40 --
target/arm/translate.c | 10 ++
2 files changed, 27 insertions(+), 23 deletions(-)
diff --git
This bitmap is created and discarded immediately.
We gain nothing by its existence.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 78 ++-
1 file changed, 4 insertions(+), 74 deletions(-)
diff --git a/accel/tcg/translate-all.c
In preparation for TARGET_TB_PCREL, reduce reliance on
absolute values by passing in pc difference.
Signed-off-by: Richard Henderson
---
target/arm/translate-a32.h | 2 +-
target/arm/translate.h | 6 ++--
target/arm/translate-a64.c | 32 +-
target/arm/translate-vfp.c | 2
Prepare for targets to be able to produce TBs that can
run in more than one virtual context.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 3 +++
include/exec/exec-all.h | 41 ++---
include/hw/core/cpu.h | 1 +
accel/tcg/cpu-exec.c | 55
Let tb->page_addr[0] contain the offset within the page of the
start of the translation block. We need to recover this value
anyway at various points, and it is easier to discard the page
offset when it's not needed, which happens naturally via the
existing find_page shift.
Signed-off-by:
Based-on: 20220819032615.884847-1-richard.hender...@linaro.org
("[PATCH v6 00/21] linux-user: Fix siginfo_t contents when jumping to
non-readable pages")
v1:
https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.hender...@linaro.org/
Just a simple refresh from v2 for the
The availability of tb->pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 12 ++
accel/tcg/cpu-exec.c| 20 -
accel/tcg/translate-all.c
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 3fb7ce05f8..4dc0a9ec41 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -283,12
Bool is more appropriate type for the alloc parameter.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 34bf296250..a8f1c34c4e 100644
---
On Thu, 2022-08-18 at 20:26 -0700, Richard Henderson wrote:
> Cache the translation from guest to host address, so we may
> use direct loads when we hit on the primary translation page.
>
> Look up the second translation page only once, during translation.
> This obviates another lookup of the
On Tue, Aug 16, 2022 at 02:25:16PM +0800, Sam Li wrote:
> +static int hdev_get_max_segments(int fd, struct stat *st) {
> +int ret;
> +if (S_ISCHR(st->st_mode)) {
> +if (ioctl(fd, SG_GET_SG_TABLESIZE, ) == 0) {
The ioctl must be within #ifdef CONFIG_LINUX since SG_GET_SG_TABLESIZE
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 9 +
hw/mips/fuloong2e.c | 2 +-
hw/ppc/pegasos2.c | 2 +-
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index c2f2e0039a..b964d1a760 100644
--- a/hw/isa/vt82c686.c
+++
Now that also the super io device is realized in the common realize method,
the isa_bus attribute can be turned into a temporary.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/isa/vt82c686.c
The object creation now happens in chip-specific init methods which
allows the realize methods to be consolidated into one method. Shifting
the logic into the init methods has the addidional advantage that the
parent object's init methods are called implicitly.
Signed-off-by: Bernhard Beschow
Rather than terminating abruptly, make use of the already present errp and
propagate the error to the caller.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 47f2fd2669..ee745d5d49 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -546,6 +546,7 @@ struct ViaISAState
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h| 5
target/i386/ops_sse_header.h | 5
target/i386/tcg/translate.c | 45 +---
3 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/target/i386/ops_sse.h
Resolves duplicate code in the boards.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 12
hw/mips/fuloong2e.c | 3 ---
hw/ppc/pegasos2.c | 4
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index
Resolves duplicate code in the boards.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 16
hw/mips/fuloong2e.c | 4
hw/ppc/pegasos2.c | 4
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index
The IDE function is closely tied to the ISA function (e.g. the IDE
interrupt routing happens there), so it makes sense that the IDE
function is instantiated within the southbridge itself. As a side effect,
duplicated code in the boards is resolved.
Signed-off-by: Bernhard Beschow
---
Unlike get_system_memory(), pci_address_space() respects the memory tree
available to the parent device.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 9d12e1cae4..5582c0b179
As pcmpeqb is used by strlen et al, this is the highest overhead
sse operation, at 2.5%. It's simple to include the other compares
at the same time.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h| 8
target/i386/ops_sse_header.h | 8
This series instantiates all PCI functions of the VT82xx southbridges in the
southbridges themselves.
For the IDE function this is especially important since its interrupt routing
is configured in the
ISA function, hence doesn't make sense to instantiate it as a "Frankenstein"
device. The
Since psubb is the second highest overhead sse operation, at 0.9%.
It's simple to include add and the other sizes at the same time.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h| 10 -
target/i386/ops_sse_header.h | 10 -
target/i386/tcg/translate.c | 39
Low hanging fruit, using gvec to move 16 bytes.
Signed-off-by: Richard Henderson
---
target/i386/cpu.h | 4 ++--
target/i386/tcg/translate.c | 7 +++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 81e5abed86..dbc9a99a3b
As pmovmskb is used by strlen et al, this is the third
highest overhead sse operation at %0.8.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h| 26 ---
target/i386/ops_sse_header.h | 1 -
target/i386/tcg/translate.c | 86 +++-
3 files
These 5 sets of conversions take care of all of the entries that
show up above 0.1% in a normal linux boot, i.e. easy libc usage.
r~
Richard Henderson (6):
target/i386: Define XMMReg and access macros
target/i386: Use tcg gvec for gen_op_movo
target/i386: Use tcg gvec for pcmp{eq,gt}*
This will be used for proper endian adjustments of gvec xmm ops.
Signed-off-by: Richard Henderson
---
target/i386/cpu.h | 53 +--
1 file changed, 42 insertions(+), 11 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index
Avoid bounce buffers when QEMUIOVector elements are within previously
registered bdrv_register_buf() buffers.
The idea is that emulated storage controllers will register guest RAM
using bdrv_register_buf() and set the BDRV_REQ_REGISTERED_BUF on I/O
requests. Therefore no blkio_map_mem_region()
Emulated devices and other BlockBackend users wishing to take advantage
of blk_register_buf() all have the same repetitive job: register
RAMBlocks with the BlockBackend using RAMBlockNotifier.
Add a BlockRAMRegistrar API to do this. A later commit will use this
from hw/block/virtio-blk.c.
Block drivers may optimize I/O requests accessing buffers previously
registered with bdrv_register_buf(). Checking whether all elements of a
request's QEMUIOVector are within previously registered buffers is
expensive, so we need a hint from the user to avoid costly checks.
Add a
Use the enum type so GDB displays the enum members instead of printing a
numeric constant.
Signed-off-by: Stefan Hajnoczi
---
include/block/block_int-common.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/block/block_int-common.h
The blkio block driver will need to look up the file descriptor for a
given pointer. This is possible in softmmu builds where the RAMBlock API
is available for querying guest RAM.
Add stubs so tools like qemu-img that link the block layer still build
successfully. In this case there is no guest
Register guest RAM using BlockRAMRegistrar and set the
BDRV_REQ_REGISTERED_BUF flag so block drivers can optimize memory
accesses in I/O requests.
This is for vdpa-blk, vhost-user-blk, and other I/O interfaces that rely
on DMA mapping/unmapping.
Signed-off-by: Stefan Hajnoczi
---
The only implementor of bdrv_register_buf() is block/nvme.c, where the
size is not needed when unregistering a buffer. This is because
util/vfio-helpers.c can look up mappings by address.
Future block drivers that implement bdrv_register_buf() may not be able
to do their job given only the buffer
When a RAMBlockNotifier is added, ->ram_block_added() is called with all
existing RAMBlocks. There is no equivalent ->ram_block_removed() call
when a RAMBlockNotifier is removed.
The util/vfio-helpers.c code (the sole user of RAMBlockNotifier) is fine
with this asymmetry because it does not rely
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