Re: [PATCH] KVM: use store-release to mark dirty pages as harvested

On 9/2/22 10:19 AM, Paolo Bonzini wrote: The following scenario can happen if QEMU sets more RESET flags while the KVM_RESET_DIRTY_RINGS ioctl is ongoing on another host CPU: CPU0 CPU1 CPU2 --

Re: [PATCH 49/51] io/channel-watch: Fix socket watch on Windows

Hi Clément, On Tue, Sep 6, 2022 at 8:06 PM Clément Chigot wrote: > > > > > I checked your patch, what you did seems to be something one would > > > > naturally write, but what is currently in the QEMU sources seems to be > > > > written intentionally. > > > > > > > > +Paolo Bonzini , you are the

Re: [PATCH v3 0/5] vhost-user-blk: dynamically resize config space based on features

Thanks for the changes. For the whole series: Reviewed-by: Raphael Norwitz On Tue, Sep 06, 2022 at 10:31:06AM +0300, Daniil Tatianin wrote: > This patch set attempts to align vhost-user-blk with virtio-blk in > terms of backward compatibility and flexibility. It also improves > the virtio core

PING: Re: [PATCH v4 1/1] monitor: Support specified vCPU registers

PING! On 8/15/22 20:00, Dr. David Alan Gilbert wrote: * zhenwei pi (pizhen...@bytedance.com) wrote: Originally we have to get all the vCPU registers and parse the specified one. To improve the performance of this usage, allow user specified vCPU id to query registers. Run a VM with 16 vCPU,

RE: [PATCH] hw/xen: set pci Atomic Ops requests for passthrough device

[AMD Official Use Only - General] FYI From: Ji, Ruili Sent: 2022年9月6日 15:40 To: qemu-devel@nongnu.org Cc: Liu, Aaron Subject: [PATCH] hw/xen: set pci Atomic Ops requests for passthrough device >From c54e0714a1e1cac7dc416bd843b9ec7162bcfc47 Mon Sep 17 00:00:00 2001 From: Ruili Ji

Re: [PATCH v2] KVM: dirty ring: add missing memory barrier

On 8/27/22 6:22 PM, Paolo Bonzini wrote: The KVM_DIRTY_GFN_F_DIRTY flag ensures that the entry is valid. If the read of the fields are not ordered after the read of the flag, QEMU might see stale values. Cc: Peter Xu Cc: Gavin Shan Signed-off-by: Paolo Bonzini --- accel/kvm/kvm-all.c | 6

Re: [PATCH 2/4] chardev: src buffer const for write functions

On Wed, Sep 7, 2022 at 12:07 AM Arwed Meyer wrote: > > Make source buffers const for char be write functions. > This allows using buffers returned by fifo as buf parameter and source buffer > should not be changed by write functions anyway. > > Signed-off-by: Arwed Meyer > --- > chardev/char.c

RE: [PATCH] Hexagon (target/hexagon) implement mutability mask for GPRs

> -Original Message- > From: Brian Cain > Sent: Thursday, September 1, 2022 4:30 PM > To: qemu-devel@nongnu.org; Taylor Simpson > Cc: Richard Henderson ; Brian Cain > > Subject: [PATCH] Hexagon (target/hexagon) implement mutability mask for > GPRs > > Some registers are defined to

[RFC PATCH 2/3] hw/peci: add PECI support for NPCM7xx BMCs

This allows BMC firmware for npcm7xx BMCs to talk to a PECI client in qemu. Signed-off-by: Titus Rwantare Reviewed-by: Patrick Venture --- MAINTAINERS| 3 +- hw/arm/Kconfig | 1 + hw/arm/npcm7xx.c | 9 ++ hw/peci/meson.build|

[RFC PATCH 3/3] hw/peci: add support for EndPointConfig reads

Signed-off-by: Titus Rwantare Reviewed-by: Hao Wu --- hw/peci/peci-client.c | 63 ++ hw/peci/peci-core.c| 44 +++-- include/hw/peci/peci.h | 23 +++ 3 files changed, 128 insertions(+), 2 deletions(-) diff --git

[RFC PATCH 0/3] Initial PECI bus support

The Platform Environment Control Interface (PECI), is a way for Intel processors to communicate with management controllers. This series of patches simulate some PECI subsystem functionality. This work is currently used against Nuvoton 7xx BMC, but it can easily be extended to support Aspeed

[RFC PATCH 1/3] hw/peci: add initial support for PECI

PECI - Platform Environment Control Interface This commit adds support for reading basic sensor values from a client on the PECI bus. BMCs can use the PECI wire to get thermal information out of an Intel cpu. Additionally, on hardware, various MSRs are exposed over the PECI bus. Part of PCI

[PATCH 2/4] chardev: src buffer const for write functions

Make source buffers const for char be write functions. This allows using buffers returned by fifo as buf parameter and source buffer should not be changed by write functions anyway. Signed-off-by: Arwed Meyer --- chardev/char.c | 4 ++-- include/chardev/char.h | 4 ++--

[PATCH 3/4] msmouse: Add pnp data

Make msmouse send serial pnp data. Enables you to see nice qemu device name in Win9x. Signed-off-by: Arwed Meyer --- chardev/msmouse.c | 101 +++--- 1 file changed, 68 insertions(+), 33 deletions(-) diff --git a/chardev/msmouse.c b/chardev/msmouse.c

[PATCH 1/4] msmouse: Handle mouse reset

Detect mouse reset via RTS or DTR line: Don't send or process anything while in reset. When coming out of reset, send ID sequence first thing. This allows msmouse to be detected by common mouse drivers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/77 Signed-off-by: Arwed Meyer ---

[PATCH 4/4] serial: Allow unaligned i/o access

Unaligned i/o access on serial UART works on real PCs. This is used for example by FreeDOS CTMouse driver. Without this it can't reset and detect serial mice. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/77 Signed-off-by: Arwed Meyer --- hw/char/serial.c | 3 +++ 1 file changed, 3

[PATCH 0/4] Make serial msmouse work

This series of patches makes `-serial msmouse` work in practice. I tested with FreeDOS/CTMouse driver `ctmouse /V` which identifies a Logitech compatible 3 button mouse. It will probably run as well with any other compatible serial mouse driver on Windows 9x etc. Arwed Meyer (4): msmouse:

Re: [PATCH v1 0/8] migration: introduce dirtylimit capability

On Fri, Sep 02, 2022 at 01:22:28AM +0800, huang...@chinatelecom.cn wrote: > From: Hyman Huang(黄勇) > > v1: > - make parameter vcpu-dirty-limit experimental > - switch dirty limit off when cancel migrate > - add cancel logic in migration test > > Please review, thanks, > > Yong > > Abstract

Re: [RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

On Tue, Sep 6, 2022, at 7:22 PM, Alex Bennée wrote: > > index 3099b38e32..59d5278868 100644 > --- a/target/arm/cpu_tcg.c > +++ b/target/arm/cpu_tcg.c > @@ -588,7 +588,9 @@ static void cortex_a15_initfn(Object *obj) > set_feature(>env, ARM_FEATURE_EL3); > set_feature(>env,

Re: [PATCH v1 4/8] migration: Implement dirty-limit convergence algo

On Fri, Sep 02, 2022 at 01:22:32AM +0800, huang...@chinatelecom.cn wrote: > From: Hyman Huang(黄勇) > > Implement dirty-limit convergence algo for live migration, > which is kind of like auto-converge algo but using dirty-limit > instead of cpu throttle to make migration convergent. > >

Re: Maximum QMP reply size

On Tue, 6 Sept 2022 at 20:41, John Snow wrote: > Hi, I suspect I have asked this before, but I didn't write it down in > a comment, so I forget my justification... > > In the QMP lib, we need to set a buffering limit for how big a QMP > message can be -- In practice, I found that the largest

Re: [RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

On Tue, 6 Sept 2022 at 19:23, Alex Bennée wrote: > > QEMU doesn't model micro-architectural details which includes most > chip errata. The ARM_ERRATA_798181 work around in the Linux > kernel (see erratum_a15_798181_init) currently detects QEMU's > cortex-a15 as broken and triggers additional

Re: [PATCH v2 2/2] dump: fix kdump to work over non-aligned blocks

On 9/5/22 08:57, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau Rewrite get_next_page() to work over non-aligned blocks. When it encounters non aligned addresses, it will try to fill a page provided by the caller. This solves a kdump crash with "tpm-crb-cmd" RAM memory region,

Re: [PATCH v2 0/8] Multiple ppc instructions fixes

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 9/6/22 09:55, Víctor Colombo wrote: This patch set fixes multiple instructions for PPC targets that were producing incorrect results, or setting the wrong bits in FPSCR. Patch 1 is just a style fix, trivial. Patch 8 adds

Re: [PATCH 0/3] target/ppc: Move fsqrt[s] to decodetree

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 9/5/22 09:37, Víctor Colombo wrote: Move fsqrt and fsqrts instructions from decode legacy to decodetree. Víctor Colombo (3): target/ppc: Move fsqrt to decodetree target/ppc: Move fsqrts to decodetree target/ppc:

Re: [PATCH 0/8] Patch series to set up a ppc64le CI

Lucas, If you're still interested, patches 1-4 are worth re-sending in separate. You'll need to address Daniel's comments on patch 1. The other 3 patches LGTM. Patches 5-8 can wait. We're not certain about Unicamp's Minicloud availability in the future, so there's no point in setting up our CI

Maximum QMP reply size

Hi, I suspect I have asked this before, but I didn't write it down in a comment, so I forget my justification... In the QMP lib, we need to set a buffering limit for how big a QMP message can be -- In practice, I found that the largest possible response was the QAPI schema reply, and I set the

Re: [PATCH v4 0/3] Implement Power ISA 3.1B hash insns

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/15/22 17:54, Víctor Colombo wrote: This patch series implements the 4 instructions added in Power ISA 3.1B: - hashchk - hashst - hashchkp - hashstp It's built on top of ppc-next. Working branch for ease of use can be

[PATCH 4/4] usbnet: Report link-up via interrupt endpoint in CDC-ECM mode

Signed-off-by: Michael Brown --- hw/usb/dev-network.c | 27 +-- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/usb/dev-network.c b/hw/usb/dev-network.c index 9d83974ec9..ac1adca543 100644 --- a/hw/usb/dev-network.c +++ b/hw/usb/dev-network.c @@ -91,6

[PATCH 2/4] usbnet: Accept mandatory USB_CDC_SET_ETHERNET_PACKET_FILTER request

The USB_CDC_SET_ETHERNET_PACKET_FILTER request is mandatory for CDC-ECM devices. Accept this request, ignoring the actual filter value (to match the existing behaviour for RNDIS). Signed-off-by: Michael Brown --- hw/usb/dev-network.c | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCH 3/4] usbnet: Detect short packets as sent by the xHCI controller

The xHCI controller will ignore the endpoint MTU and so may deliver packets of any length. Detect short packets as being any packet that has a length of zero or a length that is not a multiple of the MTU. Signed-off-by: Michael Brown --- hw/usb/dev-network.c | 2 +- 1 file changed, 1

[PATCH 1/4] usbnet: Add missing usb_wakeup() call in usbnet_receive()

usbnet_receive() does not currently wake up the USB endpoint, leading to a dead RX datapath when used with a host controller such as xHCI that relies on being woken up. Fix by adding a call to usb_wakeup() at the end of usbnet_receive(). Signed-off-by: Michael Brown --- hw/usb/dev-network.c |

[PATCH 0/4] Fix USB network CDC-ECM mode support

From: Michael Brown Fix some minor violations of the CDC-ECM specification and some interoperability issues with the emulated xHCI controller. This patch series has been working out-of-tree since 2015; my apologies for not getting around to upstreaming it sooner. Michael Brown (4): usbnet:

Re: [RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

On Tue, Sep 6, 2022 at 7:23 PM Alex Bennée wrote: > > QEMU doesn't model micro-architectural details which includes most > chip errata. The ARM_ERRATA_798181 work around in the Linux > kernel (see erratum_a15_798181_init) currently detects QEMU's > cortex-a15 as broken and triggers additional

Re: [PATCH] hw/virtio/vhost-shadow-virtqueue: Silence GCC error "maybe-uninitialized"

On Tue, Sep 6, 2022 at 7:12 PM Bernhard Beschow wrote: > > GCC issues a false positive warning, resulting in build failure with -Werror: > > In file included from /usr/include/glib-2.0/glib.h:114, >from > /home/zcone-pisint/Projects/qemu/src/include/glib-compat.h:32, >

[RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

QEMU doesn't model micro-architectural details which includes most chip errata. The ARM_ERRATA_798181 work around in the Linux kernel (see erratum_a15_798181_init) currently detects QEMU's cortex-a15 as broken and triggers additional expensive TLB flushes as a result. Change the MIDR to report

Re: [PATCH v2 8/8] target/ppc: Clear fpstatus flags on helpers missing it

On 9/6/22 09:55, Víctor Colombo wrote: In ppc emulation, exception flags are not cleared at the end of an instruction. Instead, the next instruction is responsible to clear it before its emulation. However, some helpers are not doing it, causing an issue where the previously set exception

[PATCH] hw/virtio/vhost-shadow-virtqueue: Silence GCC error "maybe-uninitialized"

GCC issues a false positive warning, resulting in build failure with -Werror: In file included from /usr/include/glib-2.0/glib.h:114, from /home/zcone-pisint/Projects/qemu/src/include/glib-compat.h:32, from

[PATCH 3/3] vdpa: Support VLAN on nic control shadow virtqueue

Update the virtio-net device model with each guest's update of vlan through control virtqueue, and accept creating a SVQ with a device exposing vlan feature bit. Done in the same commit since a malicious guest could send vlan commands otherwise. Signed-off-by: Eugenio Pérez ---

[PATCH 1/3] virtio-net: do not reset vlan filtering at set_features

This function is called after virtio_load, so all vlan configuration is lost in migration case. Just allow all the vlan-tagged packets if vlan is not configured, and trust device reset to clear all filtered vlans. Fixes: 0b1eaa8803 ("virtio-net: Do not filter VLANs without F_CTRL_VLAN")

[PATCH 0/3] Vhost-vdpa Shadow Virtqueue VLAN support

This series enables shadowed CVQ to intercept VLAN commands through shadowed CVQ, update the virtio NIC device model so qemu send it in a migration, and the restore of that VLAN state in the destination. It's based on the multiqueue series [1], but it's easy to reorder in case vlan feature is

[PATCH 2/3] vdpa: load vlan configuration at NIC startup

To have enabled vlans at device startup may happen in the destination of a live migration, so this configuration must be restored. At this moment the code is not accessible, since SVQ refuses to start if vlan feature is exposed by the device. Signed-off-by: Eugenio Pérez --- net/vhost-vdpa.c |

[PATCH] tests/qtest: npcm7xx-emc-test: Skip checking MAC

The register tests walks all the registers to verify they are initially 0 when appropriate. However, if the MAC address is set in the register space, this should not be checked against 0. Reviewed-by: Hao Wu Change-Id: I02426e39bdab33ceedd42c49d233e8680d4ec058 Signed-off-by: Patrick Venture

Re: [PATCH] 9pfs: use GHashTable for fid table

Hi Linus, Some more comments below. On Mon, 5 Sep 2022 17:03:00 +0200 Linus Heckemann wrote: > The previous implementation would iterate over the fid table for > lookup operations, resulting in an operation with O(n) complexity on > the number of open files and poor cache locality -- for

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Here's the patch SHA that introduced the offset: 0feb4a7129eb4f120c75849ddc9e50495c50cb63 -Tyler On Mon, Sep 5, 2022 at 6:15 AM Andrew Jones wrote: > On Thu, Sep 01, 2022 at 03:50:06PM -0700, Tyler Ng wrote: > > Fixes a bug in which the index of the interrupt priority is off by 1. > > For

[PATCH v4 6/6] vdpa: Allow MQ feature in SVQ

Finally enable SVQ with MQ feature. Signed-off-by: Eugenio Pérez --- net/vhost-vdpa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index c6cbe2fb5c..4bc3fd01a8 100644 --- a/net/vhost-vdpa.c +++ b/net/vhost-vdpa.c @@ -94,6 +94,7 @@ static const uint64_t

[PATCH v4 5/6] virtio-net: Update virtio-net curr_queue_pairs in vdpa backends

It was returned as error before. Instead of it, simply update the corresponding field so qemu can send it in the migration data. Signed-off-by: Eugenio Pérez Acked-by: Si-Wei Liu --- hw/net/virtio-net.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git

[PATCH v4 3/6] vdpa: Add vhost_vdpa_net_load_mq

Same way as with the MAC, restore the expected number of queues at device's start. Signed-off-by: Eugenio Pérez --- net/vhost-vdpa.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index e799e744cd..3950e4f25d 100644 ---

[PATCH v4 4/6] vdpa: validate MQ CVQ commands

So we are sure we can update the device model properly before sending to the device. Signed-off-by: Eugenio Pérez --- net/vhost-vdpa.c | 9 + 1 file changed, 9 insertions(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index 3950e4f25d..c6cbe2fb5c 100644 --- a/net/vhost-vdpa.c +++

Re: [PATCH 3/3] target/ppc: Merge fsqrt and fsqrts helpers

On 05/09/2022 14:20, Richard Henderson wrote: Well, there would of course be no separate call, but I didn't understand what you meant here with 'no separate call'... do_float_check_status would:     int status = get_float_exception_flags(>fp_status);     set_float_exception_flags(0,

[PATCH v4 1/6] vdpa: Make VhostVDPAState cvq_cmd_in_buffer control ack type

This allows to simplify the code. Rename to status while we're at it. Signed-off-by: Eugenio Pérez --- v3: Rename it to status. --- net/vhost-vdpa.c | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index

[PATCH v4 2/6] vdpa: extract vhost_vdpa_net_load_mac from vhost_vdpa_net_load

Since there may be many commands we need to issue to load the NIC state, let's split them in individual functions Signed-off-by: Eugenio Pérez -- v2: Add vhost_vdpa_net_load_cmd helper v3: Move ctrl header definition to vhost_vdpa_net_load_cmd --- net/vhost-vdpa.c | 62

[PATCH v4 0/6] Vhost-vdpa Shadow Virtqueue multiqueue support.

This series enables shadowed CVQ to intercept multiqueue commands through shadowed CVQ, update the virtio NIC device model so qemu send it in a migration, and the restore of that MQ state in the destination. v3: * Accept ctrl class and cmd in vhost_vdpa_net_load_cmd, so it's in charge of

Re: sphinx-build is really slow, any way to improve that?

On Tue, Sep 06, 2022 at 02:41:13PM +0100, Peter Maydell wrote: > On Tue, 6 Sept 2022 at 08:55, Daniel P. Berrangé wrote: > > > > On Mon, Sep 05, 2022 at 10:21:55PM +0100, Peter Maydell wrote: > > > On Mon, 5 Sept 2022 at 20:51, Claudio Fontana wrote: > > > > when I build qemu, there is a lot of

Re: sphinx-build is really slow, any way to improve that?

On Tue, 6 Sept 2022 at 08:55, Daniel P. Berrangé wrote: > > On Mon, Sep 05, 2022 at 10:21:55PM +0100, Peter Maydell wrote: > > On Mon, 5 Sept 2022 at 20:51, Claudio Fontana wrote: > > > when I build qemu, there is a lot of time spent at the end of the build > > > where one cpu goes 100% on

Re: [PATCH V4 1/3] hw/arm,loongarch: Move load_image_to_fw_cfg() to common location

On 6/9/22 11:02, Sunil V L wrote: load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same function will be required by riscv too. So, it's time to refactor and move this function to a common path. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- hw/arm/boot.c

Re: [PATCH v2 11/23] target/i386: Create cur_insn_len, cur_insn_len_i32

On 6/9/22 12:09, Richard Henderson wrote: Create common routines for computing the length of the insn. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) And tcg_const -> tcg_constant.

Re: [PATCH v4 7/7] accel/tcg: Split log_cpu_exec into inline and slow path

On 6/9/22 11:11, Richard Henderson wrote: Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 7fe42269ea..ac8eec7f54 100644 ---

Re: [PATCH v2 03/23] target/i386: Remove cur_eip argument to gen_exception

On 6/9/22 12:09, Richard Henderson wrote: All callers pass s->base.pc_next - s->cs_base, which we can just as well compute within the function. Note the special case of EXCP_VSYSCALL in which s->cs_base didn't have the subtraction, but cs_base is always zero in 64-bit mode, when vsyscall is

Re: [PATCH v2 22/23] target/i386: Create gen_eip_cur

On 6/9/22 12:09, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v1 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info

On 6/9/22 12:17, Richard Henderson wrote: Trivial but non-mechanical conversion away from pc_tmp. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 04/23] target/i386: Remove cur_eip, next_eip arguments to gen_interrupt

On 6/9/22 12:09, Richard Henderson wrote: All callers pass s->base.pc_next and s->pc, which we can just as well compute within the function. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git

Re: [PATCH v2 02/23] target/i386: Return bool from disas_insn

On 6/9/22 12:09, Richard Henderson wrote: Instead of returning the new pc, which is present in DisasContext, return true if an insn was translated. This is false when we detect a page crossing and must undo the insn under translation. Signed-off-by: Richard Henderson ---

Re: [PATCH v1 01/26] target/s390x: Use tcg_constant_* in local contexts

On 6/9/22 12:17, Richard Henderson wrote: Replace tcg_const_* with tcg_constant_* in contexts where the free to remove is nearby. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 408 +-- 1 file changed, 145 insertions(+), 263 deletions(-)

Re: [PATCH v2 10/11] pytest: add pytest to the meson build system

On Tue, Jul 12, 2022 at 12:22:10PM +0530, Ani Sinha wrote: > > > On Mon, 11 Jul 2022, John Snow wrote: > > > On Sun, Jul 10, 2022 at 1:01 PM Ani Sinha wrote: > > > > > > Integrate the pytest framework with the meson build system. This will > > > make meson > > > run all the pytests under the

Re: [PATCH v1 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal

On 6/9/22 12:17, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 14 +++--- tcg/tcg.c | 20 +++- 2 files changed, 22 insertions(+), 12 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v4 1/7] accel/tcg: Use bool for page_find_alloc

On 6/9/22 11:11, Richard Henderson wrote: Bool is more appropriate type for the alloc parameter. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2] hw/ide/piix: Ignore writes of hardwired PCI command register bits

On Thu, Jun 02, 2022 at 08:47:31PM +, Lev Kujawski wrote: > One method to enable PCI bus mastering for IDE controllers, often used > by x86 firmware, is to write 0x7 to the PCI command register. Neither > the PIIX3 specification nor actual hardware (a Tyan S1686D system) > permit modification

Re: [PATCH v2 00/11] Introduce new acpi/smbios python tests using biosbits

On Tue, Sep 06, 2022 at 03:10:05PM +0100, Daniel P. Berrangé wrote: > On Tue, Sep 06, 2022 at 10:03:55AM -0400, Michael S. Tsirkin wrote: > > On Tue, Sep 06, 2022 at 02:15:41PM +0100, Daniel P. Berrangé wrote: > > > On Thu, Jul 14, 2022 at 02:24:18PM +0100, Peter Maydell wrote: > > > > On Mon, 11

Re: [PATCH 0/1] hw/ide: share bmdma read and write functions

Am 19. Februar 2022 08:08:17 UTC schrieb Liav Albani : >This is a preparation before I send v3 of ich6-ide controller emulation patch. >I figured that it's more trivial to split the changes this way, by extracting >the bmdma functions from via.c and piix.c and sharing them together. Then, >I could

Re: [PATCH v1 25/26] tcg: Introduce tcg_temp_is_normal_*

On 6/9/22 12:17, Richard Henderson wrote: Allow targets to determine if a given temp will die across a branch. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 2 ++ include/tcg/tcg.h| 15 +++ 2 files changed, 17 insertions(+) Reviewed-by: Philippe

Re: [PATCH v2 00/11] Introduce new acpi/smbios python tests using biosbits

On Tue, Sep 06, 2022 at 10:03:55AM -0400, Michael S. Tsirkin wrote: > On Tue, Sep 06, 2022 at 02:15:41PM +0100, Daniel P. Berrangé wrote: > > On Thu, Jul 14, 2022 at 02:24:18PM +0100, Peter Maydell wrote: > > > On Mon, 11 Jul 2022 at 10:34, Michael S. Tsirkin wrote: > > > > > > > > On Sun, Jul

Re: [PATCH v1 07/26] target/s390x: Remove pc argument to pc_to_link_into

On 6/9/22 12:17, Richard Henderson wrote: All callers pass s->pc_tmp. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 2/3] module: add Error arguments to module_load_one and module_load_qom_one

+Markus On 6/9/22 14:32, Claudio Fontana wrote: On 9/6/22 13:55, Claudio Fontana wrote: improve error handling during module load, by changing: bool module_load_one(const char *prefix, const char *lib_name); void module_load_qom_one(const char *type); to: bool module_load_one(const char

[PATCH v2 6/8] target/ppc: Set OV32 when OV is set

According to PowerISA: "OV32 is set whenever OV is implicitly set, and is set to the same value that OV is defined to be set to in 32-bit mode". This patch changes helper_update_ov_legacy to set/clear ov32 when applicable. Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henrique Barboza ---

Re: [PATCH v2 00/11] Introduce new acpi/smbios python tests using biosbits

On Tue, Sep 06, 2022 at 06:58:02PM +0530, Ani Sinha wrote: > On Tue, Sep 6, 2022 at 18:45 Daniel P. Berrangé wrote: > > > On Thu, Jul 14, 2022 at 02:24:18PM +0100, Peter Maydell wrote: > > > On Mon, 11 Jul 2022 at 10:34, Michael S. Tsirkin wrote: > > > > > > > > On Sun, Jul 10, 2022 at

[PATCH v2 3/8] target/ppc: Zero second doubleword in DFP instructions

Starting at PowerISA v3.1, the second doubleword of the registers used to store results in DFP instructions are supposed to be zeroed. >From the ISA, chapter 7.2.1.1 Floating-Point Registers: """ Chapter 4. Floating-Point Facility provides 32 64-bit FPRs. Chapter 5. Decimal Floating-Point also

Re: [PATCH v2 00/11] Introduce new acpi/smbios python tests using biosbits

On Tue, Sep 6, 2022 at 18:45 Daniel P. Berrangé wrote: > On Thu, Jul 14, 2022 at 02:24:18PM +0100, Peter Maydell wrote: > > On Mon, 11 Jul 2022 at 10:34, Michael S. Tsirkin wrote: > > > > > > On Sun, Jul 10, 2022 at 10:30:03PM +0530, Ani Sinha wrote: > > > > Changelog: > > > > v2: > > > > - a

Re: [PATCH v2] hw/ide/piix: Ignore writes of hardwired PCI command register bits

Am 2. Juni 2022 20:47:31 UTC schrieb Lev Kujawski : >One method to enable PCI bus mastering for IDE controllers, often used >by x86 firmware, is to write 0x7 to the PCI command register. Neither >the PIIX3 specification nor actual hardware (a Tyan S1686D system) >permit modification of the Memory

[PATCH v2 2/8] target/ppc: Remove unused xer_* macros

The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and hiding the usage of env. Remove them. Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 4 1 file changed, 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index

[PATCH v2 1/8] target/ppc: Remove extra space from s128 field in ppc_vsr_t

Very trivial rogue space removal. There are two spaces between Int128 and s128 in ppc_vsr_t struct, where it should be only one. Signed-off-by: Víctor Colombo Reviewed-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH v2 00/11] Introduce new acpi/smbios python tests using biosbits

On Tue, Sep 06, 2022 at 02:15:41PM +0100, Daniel P. Berrangé wrote: > On Thu, Jul 14, 2022 at 02:24:18PM +0100, Peter Maydell wrote: > > On Mon, 11 Jul 2022 at 10:34, Michael S. Tsirkin wrote: > > > > > > On Sun, Jul 10, 2022 at 10:30:03PM +0530, Ani Sinha wrote: > > > > Changelog: > > > > v2: >

Re: [PATCH 00/17] acpi:pc/q35: minor PCI refactoring/cleanups

On Tue, Sep 06, 2022 at 01:41:08PM +0200, Igor Mammedov wrote: > On Fri, 1 Jul 2022 09:34:58 -0400 > Igor Mammedov wrote: > > > Flushing out ACPI PCI cleanups that preceed conversion of > > DSDT PCI slots ennumeration to AcpiDevAmlIf interface. > > It's is mostly collection of patches thraet

Re: [PATCH v2 07/11] acpi/tests/bits: add python test that exercizes QEMU bios tables using biosbits

On Tue, Jul 12, 2022 at 12:45:59PM +0530, Ani Sinha wrote: > > > On Mon, 11 Jul 2022, John Snow wrote: > > > On Sun, Jul 10, 2022 at 1:01 PM Ani Sinha wrote: > > > > > > This change adds python based test environment that can be used to run > > > pytest > > > from within a virtual

Re: [PULL v3 00/20] tcg patch queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [RFC PATCH] docs/system: clean up code escape for riscv virt platform

Alistair Francis writes: > On Mon, Sep 5, 2022 at 6:39 PM Alex Bennée wrote: >> >> The example code is rendered slightly mangled due to missing code >> block. Properly escape the code block and add shell prompt and qemu to >> fit in with the other examples on the page. >> >> Signed-off-by:

Re: [PATCH v4 2/9] target/arm: Change gen_goto_tb to work on displacements

Hi Richard, On 6/9/22 12:05, Richard Henderson wrote: In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 40 -- target/arm/translate.c | 10 ++ 2 files

[PATCH v2 4/8] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs

According to the ISA, for instruction DENBCD: "If an invalid BCD digit or sign code is detected in the source operand, an invalid-operation exception (VXCVI) occurs." In the Invalid Operation Exception section, there is the situation: "When Invalid Operation Exception is disabled (VE=0) and

Re: [PATCH v4 1/9] target/arm: Introduce curr_insn_len

On 6/9/22 12:05, Richard Henderson wrote: A simple helper to retrieve the length of the current insn. Signed-off-by: Richard Henderson --- target/arm/translate.h | 5 + target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 5 ++--- 3 files changed, 8 insertions(+), 4

Re: [PATCH v2 00/11] Introduce new acpi/smbios python tests using biosbits

On Thu, Jul 14, 2022 at 02:24:18PM +0100, Peter Maydell wrote: > On Mon, 11 Jul 2022 at 10:34, Michael S. Tsirkin wrote: > > > > On Sun, Jul 10, 2022 at 10:30:03PM +0530, Ani Sinha wrote: > > > Changelog: > > > v2: > > > - a new class of python based tests introduced that is separate from > > >

[PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension

From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 +

Re: [PATCH v4 5/9] target/arm: Change gen_exception_internal to work on displacements

On 6/9/22 12:05, Richard Henderson wrote: In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 6 +++--- target/arm/translate.c | 10 +- 2 files changed, 8 insertions(+), 8 deletions(-)

Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash

Hi Gerd, On Tue, Sep 06, 2022 at 12:41:28PM +0200, Gerd Hoffmann wrote: > Hi, > > > 3)Make the EDK2 image size to match with what qemu flash expects > > truncate -s 32M Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd > > Hmm, we have that kind of padding on arm too (64M for code and 64M for >

[PATCH 05/11] RISC-V: Adding T-Head CondMov instructions

From: Christoph Müllner This patch adds support for the T-Head CondMov instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 +

Re: [PATCH v4 4/7] include/hw/core: Create struct CPUJumpCache

On 6/9/22 11:11, Richard Henderson wrote: Wrap the bare TranslationBlock pointer into a structure. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 8 ++-- accel/tcg/cpu-exec.c | 9 ++--- accel/tcg/cputlb.c| 2 +- accel/tcg/translate-all.c | 4 ++-- 4

[PATCH] hw/xen: set pci Atomic Ops requests for passthrough device

[AMD Official Use Only - General] >From c54e0714a1e1cac7dc416bd843b9ec7162bcfc47 Mon Sep 17 00:00:00 2001 From: Ruili Ji ruili...@amd.com Date: Tue, 6 Sep 2022 14:09:41 +0800 Subject: [PATCH] hw/xen: set pci Atomic Ops requests for passthrough device Make guest os access

Re: [PULL 0/1] baum: better document usb-braille configuration

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

[PATCH 02/11] RISC-V: Adding T-Head CMO instructions

From: Christoph Müllner This patch adds support for the T-Head CMO instructions. To avoid interfering with standard extensions, decoder and translation are in its own T-Head specific files. Future patches should be able to easily add additional T-Head extesions. The implementation does not have

Re: [PATCH v4 8/9] target/arm: Introduce gen_pc_plus_diff for aarch32

On 6/9/22 12:05, Richard Henderson wrote: In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) Reviewed-by: Philippe

Re: [PATCH 2/3] module: add Error arguments to module_load_one and module_load_qom_one

On 9/6/22 13:55, Claudio Fontana wrote: > improve error handling during module load, by changing: > > bool module_load_one(const char *prefix, const char *lib_name); > void module_load_qom_one(const char *type); > > to: > > bool module_load_one(const char *prefix, const char *name, Error

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