On 31.10.2022 16:25, Jiaxun Yang wrote:
I don't have access to Octeon68XX hardware but accroading to
my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk
---
target/mips/tcg/translate.c | 10 +++---
1 file changed, 7 insertions(+), 3
Acked-by: Pavel Dovgalyuk
On 31.10.2022 16:25, Jiaxun Yang wrote:
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
On 10/31/22 19:43, Ake Koomsin wrote:
We need to check HCR_E2H and HCR_TGE to select the right MMU index for
the correct translation regime.
To check for EL2&0 translation regime:
- For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE
- For S1E2* ops, check only HCR_E2H
Since commit f1018ea0a30f ("tests: avoid DOS line endings in PSK file"),
the bug of the helper test_tls_psk_init_common() that caused TLS PSK
tests to fail on Windows was fixed. Let's enable these tests on win32.
Signed-off-by: Bin Meng
---
tests/qtest/migration-test.c | 14 --
1
Hi Alistair,
>> RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
> Newline here
>> +qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_AON_WDT_IRQ));
> and here please
I've deleted the public create function and added newlines in patch v2.
Thank you for the review !
Regards,
Tommy
On Mon,
Hi Alistair,
Sorry for the late reply.
Thank you for the great feedback!
> Can you please keep all variable declarations at the top of the code
block.
I've fixed it in patch v2.
> Does the guest not expect to read the values back?
The devices : AON-LFROSC, AON-BACKUP, AON_PMU haven't been
Add some simple tests of the watchdog timer in the always-on domain device
of HiFive 1 rev b.
Signed-off-by: Tommy Wu
---
tests/qtest/meson.build | 3 +
tests/qtest/sifive-e-aon-watchdog-test.c | 650 +++
2 files changed, 653 insertions(+)
create mode
Create the AON device when we realize the sifive_e machine.
This patch only implemented the functionality of the watchdog timer,
not all the functionality of the AON device.
Signed-off-by: Tommy Wu
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_e.c | 13 +++--
The HiFive 1 rev b includes a watchdog module based on a 32-bit
counter. The watchdog timer is in the always-on domain device of
HiFive 1 rev b, so this patch added the AON device to the sifive_e
machine. This patch only implemented the functionality of the
watchdog timer, not all the
The watchdog timer is in the always-on domain device of HiFive 1 rev b,
so this patch added the AON device to the sifive_e machine. This patch
only implemented the functionality of the watchdog timer.
Signed-off-by: Tommy Wu
---
hw/misc/Kconfig| 3 +
hw/misc/meson.build
On Sat, Oct 29, 2022 at 12:02 AM Eugenio Pérez wrote:
>
> Some fixes that did not get in time for the last net pull request.
>
> Eugenio Pérez (4):
> vhost: Delete useless casting
> vhost: convert byte order on SVQ used event write
> vhost: Fix lines over 80 characters
> vhost: convert
On Fri, Oct 28, 2022 at 2:50 PM Eugenio Perez Martin
wrote:
>
> On Fri, Oct 28, 2022 at 4:44 AM Jason Wang wrote:
> >
> >
> > 在 2022/10/27 04:58, Michael S. Tsirkin 写道:
> > > On Thu, Oct 20, 2022 at 05:52:47PM +0200, Eugenio Pérez wrote:
> > >> Event idx helps to reduce the number of
在 2022/10/31 20:35, Michael S. Tsirkin 写道:
On Mon, Oct 31, 2022 at 09:29:53AM +0100, Eugenio Perez Martin wrote:
On Sat, Oct 29, 2022 at 12:53 AM Philippe Mathieu-Daudé
wrote:
On 28/10/22 18:02, Eugenio Pérez wrote:
This causes errors on virtio modern devices on big endian hosts
On Sun, Oct 30, 2022 at 6:39 PM Yi Liu wrote:
>
> On 2022/10/28 14:14, Jason Wang wrote:
> > We introduce VTDBus structure as an intermediate step for searching
> > the address space. This works well with SID based matching/lookup. But
> > when we want to support SID plus PASID based address
On Mon, Oct 31, 2022 at 5:28 PM Yi Liu wrote:
>
> On 2022/10/31 17:15, Jason Wang wrote:
> > On Mon, Oct 31, 2022 at 2:43 PM Michael S. Tsirkin wrote:
> >>
> >> On Fri, Oct 28, 2022 at 09:49:36PM +0800, Yi Liu wrote:
> >>> On 2022/10/28 14:14, Jason Wang wrote:
> This patch introduce
The items of qapi/virtio.json are introduced at a5ebce38576. They will be
in the version 7.2 not 7.1.
Signed-off-by: Han Han
---
qapi/virtio.json | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/qapi/virtio.json b/qapi/virtio.json
index
On Sat, Oct 29, 2022 at 1:28 AM Si-Wei Liu wrote:
>
> Hi Jason,
>
> This one is a one-line simple bug fix but seems to be missed from the pull
> request. If there's a v2 for the PULL, would appreciate if you can piggyback.
> Thanks in advance!
>
> Regards,
> -Siwei
>
I've queued this for rc1.
Hi Daniel,
On Wed, Oct 26, 2022 at 12:41 AM Bin Meng wrote:
>
> On Wed, Oct 19, 2022 at 6:20 PM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > The maximum number of wait objects for win32 should be
> > MAXIMUM_WAIT_OBJECTS, not MAXIMUM_WAIT_OBJECTS + 1.
> >
> > Signed-off-by: Bin Meng
> > ---
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of a PCIe function which calls
pci_add_capability() in turn is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
Acked-by: Jonathan Cameron (for CXL parts)
---
docs/pcie_sriov.txt
The code generating errors in pci_add_capability has a comment which
says:
> Verify that capabilities don't overlap. Note: device assignment
> depends on this check to verify that the device is not broken.
> Should never trigger for emulated devices, but it's helpful for
> debugging these.
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 20 +---
include/hw/pci/pci.h | 12 ++--
2 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 9e62c8e75d..b352a9c732 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of slotid_cap_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/slotid_cap.c | 8 ++--
1 file changed, 2
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/i82801b11.c | 14 ++
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of shpc_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/pci_bridge_dev.c | 2 +-
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msix_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msix.c | 8 ++--
1 file changed, 2 insertions(+), 6
pci_add_capability() checks whether capabilities overlap, and notifies
its caller so that it can properly handle the case. However, in the
most cases, the capabilities actually never overlap, and the interface
incurred extra error handling code, which is often incorrect or
suboptimal. For such
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msi_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msi.c | 9 +
1 file changed, 1 insertion(+), 8
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
On Fri, Oct 28, 2022 at 02:55:45PM +0800,
Chao Peng wrote:
> On Wed, Oct 26, 2022 at 02:54:25PM -0700, Isaku Yamahata wrote:
> > On Tue, Oct 25, 2022 at 11:13:43PM +0800,
> > Chao Peng wrote:
> >
> > > A memslot with KVM_MEM_PRIVATE being set can include both fd-based
> > > private memory and
Am 31. Oktober 2022 17:41:59 UTC schrieb "Michael S. Tsirkin" :
>On Mon, Oct 31, 2022 at 01:45:29PM +0100, Igor Mammedov wrote:
>> On Fri, 28 Oct 2022 12:34:18 +0200
>> Bernhard Beschow wrote:
>>
>> > The is_piix4 attribute is set once in one location and read once in
>> > another. Doing both in
On 25/10/22 18:39, Peter Maydell wrote:
From: Richard Henderson
Hoist the computation of the mmu_idx for the ptw up to
get_phys_addr_with_struct and get_phys_addr_twostage.
This removes the duplicate check for stage2 disabled
from the middle of the walk, performing it only once.
On 31/10/22 23:09, BALATON Zoltan wrote:
On Mon, 31 Oct 2022, Mark Cave-Ayland wrote:
On 30/10/2022 22:23, BALATON Zoltan wrote:
On Sun, 30 Oct 2022, Mark Cave-Ayland wrote:
On 28/10/2022 12:56, BALATON Zoltan wrote:
Since only one week is left until freeze starts I've included some
more
On Mon, 31 Oct 2022, Mark Cave-Ayland wrote:
On 30/10/2022 22:23, BALATON Zoltan wrote:
On Sun, 30 Oct 2022, Mark Cave-Ayland wrote:
On 28/10/2022 12:56, BALATON Zoltan wrote:
Since only one week is left until freeze starts I've included some
more patches in this version that I've intended to
On 31/10/22 22:35, Chuck Zmudzinski wrote:
When Qemu is built with --enable-xen and --disable-xen-pci-passthrough
and the target os is linux, the build fails with:
meson.build:3477:2: ERROR: File xen_pt_stub.c does not exist.
Fixes: 582ea95f5f93 ("meson: convert hw/xen")
Signed-off-by: Chuck
On 11/1/22 08:27, Mark Cave-Ayland wrote:
On 31/10/2022 20:53, Stefan Hajnoczi wrote:
On Mon, 31 Oct 2022 at 16:42, Richard Henderson
wrote:
On 11/1/22 04:56, Christian Schoenebeck wrote:
On Wednesday, October 26, 2022 4:10:54 AM CET Richard Henderson wrote:
BTW Richard, could you add a
Add a way to examine the unwind data without actually
restoring the data back into env.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 4 +--
include/exec/exec-all.h | 21 ---
accel/tcg/translate-all.c | 74
The value passed is always true.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 2 +-
accel/tcg/tb-maint.c | 4 ++--
accel/tcg/translate-all.c | 15 +++
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git
The helpers for reset_rf, cli, sti, clac, stac are
completely trivial; implement them inline.
Drop some nearby #if 0 code.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/helper.h| 5 -
target/i386/tcg/cc_helper.c |
From: Ilya Leoshkevich
Add a test to detect races between munmap() and creating new threads.
Signed-off-by: Ilya Leoshkevich
Message-Id: <20221028124227.2354792-3-...@linux.ibm.com>
[rth: add more return insns]
Signed-off-by: Richard Henderson
---
tests/tcg/multiarch/munmap-pthread.c | 79
The value passed is always true, and if the target's
synchronize_from_tb hook is non-trivial, not exiting
may be erroneous.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 5 +
accel/tcg/cpu-exec-common.c | 2 +-
Avoid cpu_restore_state, and modifying env->eip out from
underneath the translator with TARGET_TB_PCREL. There is
some slight duplication from x86_restore_state_to_opc,
but it's just a few lines.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1269
Reviewed-by: Claudio Fontana
Delay cpu_list_add until realize is complete, so that cross-cpu
interaction does not happen with incomplete cpu state. For this,
we must delay plugin initialization out of tcg_exec_realizefn,
because no cpu_index has been assigned.
Fixes a problem with cross-cpu jump cache flushing, when the
We have called cpu_restore_state asserting will_exit.
Do not go back on that promise. This affects icount.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Since we do not plan to exit, use cpu_unwind_state_data
and extract exactly the data requested.
This is a bug fix, in that we no longer clobber dflag.
Consider:
l.j L2 // branch
l.mfspr r1, ppc// delay
L1: boom
L2: l.lwa r3, (r4)
Here, dflag
From: Icenowy Zheng
When registering helpers via FFI for TCI, the inner loop that iterates
parameters of the helper reuses (and thus pollutes) the same variable
used by the outer loop that iterates all helpers, thus made some helpers
unregistered.
Fix this logic error by using a dedicated
With sparc64 we need not distinguish between registers that
can hold 32-bit values and those that can hold 64-bit values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-con-set.h | 16 +
tcg/sparc64/tcg-target-con-str.h | 3 -
Emphasize that we only support full 64-bit code generation.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 4 +---
tcg/{sparc => sparc64}/tcg-target-con-set.h | 0
tcg/{sparc =>
Since 9b9c37c36439, we have only supported sparc64 cpus.
Debian and Gentoo now only support 64-bit sparc64 userland,
so it is time to drop the 32-bit sparc64 userland: sparc32plus.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221031-2
for you to fetch changes up to 83d92559cdf0ce842e52e5bbf230f7f62a6206aa:
tests/tcg/multiarch: Add munmap-pthread.c (2022-11-01 08:31:41 +1100)
Remove sparc32plus
Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
as noted in docs/igd-assign.txt in the Qemu source code.
Currently, when the xl toolstack is used to configure a Xen HVM guest with
Intel IGD passthrough to the guest with the Qemu upstream device model,
a Qemu emulated PCI
This is a series of two patches:
The first fixes FTBFS when --enable-xen and --disable-xen-pci-passthrough
configure options are set with when building for the linux target os.
The second fixes a regression that was introduced many years ago with the
upgrade from the Qemu traditional device
When Qemu is built with --enable-xen and --disable-xen-pci-passthrough
and the target os is linux, the build fails with:
meson.build:3477:2: ERROR: File xen_pt_stub.c does not exist.
Fixes: 582ea95f5f93 ("meson: convert hw/xen")
Signed-off-by: Chuck Zmudzinski
---
v2: Remove From: tag at top
On 31/10/2022 20:53, Stefan Hajnoczi wrote:
On Mon, 31 Oct 2022 at 16:42, Richard Henderson
wrote:
On 11/1/22 04:56, Christian Schoenebeck wrote:
On Wednesday, October 26, 2022 4:10:54 AM CET Richard Henderson wrote:
BTW Richard, could you add a message-id tag to your queued TCG patches?
On 10/31/22 22:07, Ilya Leoshkevich wrote:
@@ -1580,15 +1580,13 @@ void tcg_flush_jmp_cache(CPUState *cpu)
{
CPUJumpCache *jc = cpu->tb_jmp_cache;
-if (likely(jc)) {
-for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) {
-qatomic_set(>array[i].tb, NULL);
-}
-
On Mon, 31 Oct 2022 at 16:42, Richard Henderson
wrote:
> On 11/1/22 04:56, Christian Schoenebeck wrote:
> > On Wednesday, October 26, 2022 4:10:54 AM CET Richard Henderson wrote:
> > BTW Richard, could you add a message-id tag to your queued TCG patches?
>
> Sometimes I remember, but I don't use
On 30/10/2022 22:23, BALATON Zoltan wrote:
On Sun, 30 Oct 2022, Mark Cave-Ayland wrote:
On 28/10/2022 12:56, BALATON Zoltan wrote:
Since only one week is left until freeze starts I've included some
more patches in this version that I've intended to submit after the
clean ups but we're running
On Mon, 31 Oct 2022 at 16:37, Michael S. Tsirkin wrote:
>
> On Mon, Oct 31, 2022 at 04:12:24PM -0400, Stefan Hajnoczi wrote:
> > Another CI failure:
> > https://gitlab.com/qemu-project/qemu/-/jobs/3253817492
> >
> > Stefan
>
> Thanks!
> Freeze rules only require pull request on list so I think
On 11/1/22 04:56, Christian Schoenebeck wrote:
On Wednesday, October 26, 2022 4:10:54 AM CET Richard Henderson wrote:
Add a tcg_ops hook to replace the restore_state_to_opc
function call. Because these generic hooks cannot depend
on target-specific types, temporarily, copy the current
On Mon, Oct 24, 2022 at 09:46:20AM +, Lev Kujawski wrote:
> Devices like the PIIX3/4 IDE controller do not support certain modes
> of operation, such as memory space accesses, and indicate this lack of
> support by hardwiring the applicable bits to zero. Extend the QEMU
> PCI device testing
On Mon, Oct 31, 2022 at 04:12:24PM -0400, Stefan Hajnoczi wrote:
> Another CI failure:
> https://gitlab.com/qemu-project/qemu/-/jobs/3253817492
>
> Stefan
Thanks!
Freeze rules only require pull request on list so I think it's ok if I
handle the failout and resubmit day after tomorrow, right?
--
On Mon, Oct 31, 2022 at 08:59:35AM -0400, Emanuele Giuseppe Esposito wrote:
> Remove usage of aio_context_acquire by always submitting asynchronous
> AIO to the current thread's LuringState.
>
> In order to prevent mistakes from the caller side, avoid passing LuringState
> in
On Mon, Oct 31, 2022 at 08:59:34AM -0400, Emanuele Giuseppe Esposito wrote:
> @@ -56,10 +59,8 @@ struct LinuxAioState {
> io_context_t ctx;
> EventNotifier e;
>
> -/* io queue for submit at batch. Protected by AioContext lock. */
> +/* All data is only used in one I/O thread.
On Mon, Oct 31, 2022 at 08:59:36AM -0400, Emanuele Giuseppe Esposito wrote:
> @@ -251,6 +247,9 @@ BlockAIOCB *thread_pool_submit_aio(ThreadPool *pool,
Documentation must be added to explain that thread_pool_submit_aio(),
thread_pool_submit_co(), and thread_pool_submit() must be called on the
From: BALATON Zoltan
The PROM_FILENAME and KERNEL_* defines are used by mac_oldworld and
mac_newworld but they don't have to be identical so these could be
moved to the individual boards.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
From: BALATON Zoltan
All that is left in mac.h now belongs to the nvram emulation so rename
it accordingly and only include it where it is really used.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS
From: BALATON Zoltan
Map regions in ascending order and reorganise code a bit to avoid some
casts and move Uninorth parts together.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac_newworld.c | 37
From: BALATON Zoltan
The tbfreq variable is only set once in an if-else which can be done
at the variable declaration saving some lines of code and making it
simpler.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: BALATON Zoltan
The NVRAM_SIZE constant was defined but not used. Rename it to
MACIO_NVRAM_SIZE to match the device model and use it where appropriate.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: BALATON Zoltan
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few such variables. This is
From: BALATON Zoltan
Several variables are set in if-else branches where the else branch
can be removed by setting a default value at the variable declaration
which leads to simlpler code that is easier to follow.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: BALATON Zoltan
This might allow the compiler to check values.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac_newworld.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git
The following changes since commit 5107fd3effb1cfec3b96d9e819f1605048640e31:
net/vhost-vdpa.c: Fix clang compilation failure (2022-10-31 13:01:31 -0400)
are available in the Git repository at:
https://github.com/mcayland/qemu.git tags/qemu-macppc-20221031
for you to fetch changes up
From: BALATON Zoltan
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 1 +
hw/pci-host/grackle.c | 14 +--
hw/ppc/mac.h | 3 ---
hw/ppc/mac_oldworld.c | 1
From: BALATON Zoltan
By storing the device pointers in a variable with the right type the
number of QOM casts can be reduced which also makes the code more
readable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by:
From: BALATON Zoltan
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac_newworld.c | 6 --
hw/ppc/mac_oldworld.c | 9 ++---
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/mac_newworld.c
From: BALATON Zoltan
Move the parts specific to and only used by mac99 out from the shared
mac.h into mac_newworld.c where they better belong.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac.h | 24
From: BALATON Zoltan
Drop some more local variables additionally to commit b8df32555ce5 to
match clean ups done to mac_newwold in previous patch.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id:
From: BALATON Zoltan
Move the parts specific to and only used by macio out from the shared
mac.h into macio.c where they better belong.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Message-Id:
Signed-off-by: Mark Cave-Ayland
---
Another CI failure:
https://gitlab.com/qemu-project/qemu/-/jobs/3253817492
Stefan
Here is another CI failure:
qemu-system-i386: current -smp configuration requires kernel irqchip
and X2APIC API support.
Broken pipe
../tests/qtest/libqtest.c:179: kill_qemu() tried to terminate QEMU
process but encountered exit status 1 (expected 0)
TAP parsing error: Too few tests run (expected
Hi Michael,
I removed the local variable in virtio_crypto_req_complete() since it's unused:
-g_autofree struct iovec *in_iov_copy = req->in_iov;
Stefan
Hi Michael,
The fuzzer is not happy with qpci_device_enable():
https://gitlab.com/qemu-project/qemu/-/jobs/3253817499
Stefan
On Tue, Oct 25, 2022 at 11:56:17AM +0100, Jonathan Cameron wrote:
> On Mon, 24 Oct 2022 13:42:54 -0400
> Gregory Price wrote:
>
> > On Fri, Oct 14, 2022 at 04:10:44PM +0100, Jonathan Cameron wrote:
> > > From: Huai-Cheng Kuo
> > >
> > > The CDAT can be specified in two ways. One is to add
On Mon, Oct 31, 2022 at 03:35:28PM -0400, Michael S. Tsirkin wrote:
> On Mon, Oct 31, 2022 at 03:31:54PM -0400, Michael S. Tsirkin wrote:
> > On Mon, Oct 31, 2022 at 03:19:25PM -0400, Stefan Hajnoczi wrote:
> > > On Mon, 31 Oct 2022 at 15:14, Stefan Hajnoczi wrote:
> > > >
> > > > On Mon, 31 Oct
On Mon, Oct 31, 2022 at 03:31:54PM -0400, Michael S. Tsirkin wrote:
> On Mon, Oct 31, 2022 at 03:19:25PM -0400, Stefan Hajnoczi wrote:
> > On Mon, 31 Oct 2022 at 15:14, Stefan Hajnoczi wrote:
> > >
> > > On Mon, 31 Oct 2022 at 08:52, Michael S. Tsirkin wrote:
> > > > Lei He (4):
> > > >
On Mon, Oct 31, 2022 at 03:19:25PM -0400, Stefan Hajnoczi wrote:
> On Mon, 31 Oct 2022 at 15:14, Stefan Hajnoczi wrote:
> >
> > On Mon, 31 Oct 2022 at 08:52, Michael S. Tsirkin wrote:
> > > Lei He (4):
> > > virtio-crypto: Support asynchronous mode
> >
> > The following clang warning
On Mon, 31 Oct 2022 at 15:14, Stefan Hajnoczi wrote:
>
> On Mon, 31 Oct 2022 at 08:52, Michael S. Tsirkin wrote:
> > Lei He (4):
> > virtio-crypto: Support asynchronous mode
>
> The following clang warning breaks the build. Please resend a fixed
> pull request, thanks!
On second thought,
On Mon, 31 Oct 2022 at 08:52, Michael S. Tsirkin wrote:
> Lei He (4):
> virtio-crypto: Support asynchronous mode
The following clang warning breaks the build. Please resend a fixed
pull request, thanks!
clang -m64 -mcx16 -Ilibqemu-x86_64-softmmu.fa.p -I. -I.. -Itarget/i386
On 26/10/22 00:22, Thomas Huth wrote:
On 25/10/2022 16.28, Amarjargal Gundjalam wrote:
The TABs should be replaced with spaces, to make sure that we have a
consistent coding style with an indentation of 4 spaces everywhere.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
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On Sat, Oct 29, 2022 at 12:38:54AM +0100, Alberto Faria wrote:
> The nvme-io_uring driver expects a character special file such as
> /dev/ng0n1. Follow the convention of having a "filename" option when a
> regular file is expected, and a "path" option otherwise.
>
> This makes io_uring the only
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