Greg Kurz writes:
> The qemu_v9fs_synth_mkdir() and qemu_v9fs_synth_add_file() functions
> currently return a positive errno value on failure. This causes
> checkpatch.pl to spit several errors like the one below:
>
> ERROR: return of an errno should typically be -ve (return -EAGAIN)
> #79: FILE:
Signed-off-by: Sam Li
---
_posts/2022-11-17-zoned-emulation.md | 69
1 file changed, 69 insertions(+)
create mode 100644 _posts/2022-11-17-zoned-emulation.md
diff --git a/_posts/2022-11-17-zoned-emulation.md
b/_posts/2022-11-17-zoned-emulation.md
new file mode 1006
On 25/11/22 17:08, Evgeny Ermakov wrote:
Signed-off-by: Evgeny Ermakov
---
hw/display/next-fb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On Fri, Nov 25, 2022 at 4:33 PM Thomas Huth wrote:
>
> When running the migration test compiled with Clang from Fedora 37
> and sanitizers enabled, there is an error complaining about unlink():
>
> ../tests/qtest/migration-test.c:1072:12: runtime error: null pointer
> passed as argument 1, whic
Am 25.11.22 um 17:32 schrieb German Maglione:
On Fri, Nov 25, 2022 at 3:40 PM Marc Hartmayer wrote:
The virtiofsd currently crashes on s390x. This is because of a
`sigreturn` system call. See audit log below:
type=SECCOMP msg=audit(1669382477.611:459): auid=4294967295 uid=0 gid=0 ses=429496
On Fri, Nov 25, 2022 at 7:01 PM Alexandre Ghiti wrote:
>
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in turn mus
On Thu, Nov 24, 2022 at 9:57 PM Peter Maydell wrote:
>
> Convert the parent class TYPE_CPU to 3-phase reset. This
> is a necessary prerequisite to converting the subclasses.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/core/cpu-common.c | 7 ---
> 1
On Thu, Nov 24, 2022 at 10:00 PM Peter Maydell wrote:
>
> Convert the riscv CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 4 ++--
> ta
On Thu, Nov 24, 2022 at 9:58 PM Peter Maydell wrote:
>
> Convert the Arm CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alistair Francis
Alistair
> ---
> target/arm/cpu-qom.h | 4 ++--
> tar
On 27/11/22 04:22, Hoa Nguyen wrote:
Signed-off-by: Hoa Nguyen
---
hw/cxl/cxl-host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On Sun, 27 Nov 2022 at 13:09, Stefan Hajnoczi wrote:
>
> On Sat, 26 Nov 2022 at 10:25, Stefan Weil wrote:
> >
> > Signed-off-by: Stefan Weil
> > ---
> > MAINTAINERS | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index cf24910249..6966490c94 100644
>
On Sun, 27 Nov 2022 at 13:31, Stefan Weil wrote:
>
> Am 27.11.22 um 19:23 schrieb Stefan Hajnoczi:
>
> We need to wait for Michael to agree to maintainership in patch 5. If
> we run out of time I suggest splitting out patch 5.
>
> Reviewed-by: Stefan Hajnoczi
>
>
> Citing Michael from a v2 email:
Am 27.11.22 um 19:23 schrieb Stefan Hajnoczi:
We need to wait for Michael to agree to maintainership in patch 5. If
we run out of time I suggest splitting out patch 5.
Reviewed-by: Stefan Hajnoczi
Citing Michael from a v2 email: "pls do".
Stefan
Hello Michael,
I just noticed tha
Am 27.11.22 um 19:14 schrieb Stefan Hajnoczi:
On Sat, 26 Nov 2022 at 10:25, Stefan Weil wrote:
Signed-off-by: Stefan Weil
Reviewed-by: Marc-André Lureau
Message-Id: <20220422070144.1043697-4...@weilnetz.de>
Signed-off-by: Laurent Vivier
---
subprojects/libvhost-user/libvhost-user.c | 13 +
We need to wait for Michael to agree to maintainership in patch 5. If
we run out of time I suggest splitting out patch 5.
Reviewed-by: Stefan Hajnoczi
On Sat, 26 Nov 2022 at 10:25, Stefan Weil wrote:
>
> Signed-off-by: Stefan Weil
> Reviewed-by: Marc-André Lureau
> Message-Id: <20220422070144.1043697-4...@weilnetz.de>
> Signed-off-by: Laurent Vivier
> ---
> subprojects/libvhost-user/libvhost-user.c | 13 -
> 1 file changed, 12 in
On Sat, 26 Nov 2022 at 10:25, Stefan Weil wrote:
>
> Signed-off-by: Stefan Weil
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cf24910249..6966490c94 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2005,6 +2005,7 @@ F: docs/int
On Sat, 26 Nov 2022 at 10:25, Stefan Weil wrote:
>
> This fix is required for 32 bit hosts. The bug was detected by CI
> for arm-linux, but is also relevant for i386-linux.
>
> Reported-by: Stefan Hajnoczi
> Signed-off-by: Stefan Weil
> ---
> subprojects/libvhost-user/libvhost-user.c | 3 ++-
>
On Sat, 26 Nov 2022 at 09:18, Alex Bennée wrote:
>
>
> Stefan Hajnoczi writes:
>
> > On Sat, 26 Nov 2022 at 04:45, Alex Bennée wrote:
> >>
> >>
> >> Alex Bennée writes:
> >>
> >> > Alex Bennée writes:
> >> >
> >> >> Hi,
> >> >>
> >> >
> >> >> I can replicate some of the other failures I've be
Thomas Huth wrote:
> When running the migration test compiled with Clang from Fedora 37
> and sanitizers enabled, there is an error complaining about unlink():
>
> ../tests/qtest/migration-test.c:1072:12: runtime error: null pointer
> passed as argument 1, which is declared to never be null
>
If the number of interrupt is not multiple of 32, PLIC will have
out-of-bound access to source_priority array. Compute the number of
interrupt in the last word to avoid this out-of-bound access of array.
Signed-off-by: Jim Shu
---
hw/intc/sifive_plic.c | 12 +++-
1 file changed, 11 inser
Signed-off-by: Hoa Nguyen
---
hw/cxl/cxl-host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index 1adf61231a..3c1ec8732a 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -47,7 +47,7 @@ static void cxl_fixed_memory_window_confi
From: Tobias Röhmel
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel
---
target/ar
From: Tobias Röhmel
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c | 24 +++-
target/arm/cpu.h | 6 +
target/arm/helper.c | 299 +++
target/arm/machine.c | 28
4 files changed, 356 insertions(+), 1 deletion(-)
diff --git a/target/arm
From: Tobias Röhmel
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2 des
From: Tobias Röhmel
No worries about the delay. I'm glad you are looking at it :)
v5:
1. Adjusted the spacing as requested
2. Removed cp 15
3. Rebased and put assert back
4. Fixed indention issues
5.
- Made hprbar etc pointers instead of arrays
- Fixed the logic/bound issues
- For the VMSTATE ch
From: Tobias Röhmel
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel
---
target/arm/helper.c | 13 +
1 file changed, 9 inser
From: Tobias Röhmel
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c| 6 +-
target/arm/helper.c | 21 +++
From: Tobias Röhmel
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel
---
target/arm/cpu_tcg.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
ind
From: Tobias Röhmel
Add PMSAv8r translation.
Signed-off-by: Tobias Röhmel
---
target/arm/ptw.c | 127 +++
1 file changed, 105 insertions(+), 22 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 7d19829702..0514a83c1b 100644
--- a/t
On 11/24/22 10:25, Pierre Morel wrote:
Gentle ping.
Did I understand the problem or am I wrong?
I guess I was wrong, so I send a new series next week.
Regards,
Pierre
On 11/17/22 17:38, Pierre Morel wrote:
On 11/17/22 10:31, Pierre Morel wrote:
On 11/16/22 17:51, Christian Bornt
On 11/22/22 10:05, Pierre Morel wrote:
On 11/21/22 15:13, Cédric Le Goater wrote:
+static char *s390_top_set_level2(S390Topology *topo, char *p)
+{
+ int i, origin;
+
+ for (i = 0; i < topo->nr_sockets; i++) {
+ if (!topo->socket[i].active_count) {
+ continue;
+
Am 25. November 2022 17:30:40 UTC schrieb "Alex Bennée"
:
>The VM status should always preempt the device status for these
>checks. This ensures the device is in the correct state when we
>suspend the VM prior to migrations. This restores the checks to the
>order they where in before the refact
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