Re: [PATCH v5 4/4] x86: re-enable rng seeding via SetupData

On Sat, Dec 24, 2022 at 04:09:08AM +0100, Jason A. Donenfeld wrote: > Hi Eric, > > Replying to you from my telephone, and I'm traveling the next two days, > but I thought I should mention some preliminary results right away from > doing some termux compiles: > > On Fri, Dec 23, 2022 at

Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test

Hi, On Fri, Dec 23, 2022 at 2:25 PM Bin Meng wrote: > > Hi Anup, > > On Fri, Dec 23, 2022 at 12:56 AM Anup Patel wrote: > > > > On Thu, Dec 22, 2022 at 6:27 PM Bin Meng wrote: > > > > > > On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza > > > wrote: > > > > > > > > > > > > > > > > On

Re: [PATCH v5 4/4] x86: re-enable rng seeding via SetupData

Hi Eric, Replying to you from my telephone, and I'm traveling the next two days, but I thought I should mention some preliminary results right away from doing some termux compiles: On Fri, Dec 23, 2022 at 04:14:00PM -0800, Eric Biggers wrote: > Hi Jason, > > On Wed, Sep 21, 2022 at 11:31:34AM

[PATCH v3 2/2] hw/intc/loongarch_pch_pic: add irq number property

With loongarch 7A1000 manual, irq number supported can be set in PCH_PIC_INT_ID_HI register. This patch adds irq number property for loongarch_pch_pic, so that virt machine can set different irq number when pch_pic intc is added. Signed-off-by: Tianrui Zhao --- hw/intc/loongarch_pch_pic.c

[PATCH v3 1/2] hw/intc/loongarch_pch_msi: add irq number property

This patch adds irq number property for loongarch msi interrupt controller, and remove hard coding irq number macro. Signed-off-by: Tianrui Zhao --- hw/intc/loongarch_pch_msi.c | 33 ++--- hw/loongarch/virt.c | 13 +++-

[PATCH v3 0/2] Add irq number property for loongarch pch interrupt controller

This series add irq number property for loongarch pch_msi and pch_pic interrupt controller. Changes for v3: (1) Fix the valid range of msi_irq_num, it will trigger error_setg() when irq_num is invalid. (2) Using g_new() to alloc msi_irqs when pch_msi realize. (3) Using EXTIOI_IRQS macro to

Re: [PATCH v5 4/4] x86: re-enable rng seeding via SetupData

Hi Jason, On Wed, Sep 21, 2022 at 11:31:34AM +0200, Jason A. Donenfeld wrote: > This reverts 3824e25db1 ("x86: disable rng seeding via setup_data"), but > for 7.2 rather than 7.1, now that modifying setup_data is safe to do. > > Cc: Laurent Vivier > Cc: Michael S. Tsirkin > Cc: Paolo Bonzini

Re: [PATCH v2 4/4] docs/devel: Rules on #include in headers

Markus Armbruster writes: > Rules for headers were proposed a long time ago, and generally liked: > > Message-ID: <87h9g8j57d@blackfin.pond.sub.org> > https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html > > Wortk them into docs/devel/style.rst. nit: spelling

[PATCH v2] linux-user: Fix brk() to release pages

The current brk() implementation does not de-allocate pages if a lower address is given compared to earlier brk() calls. But according to the manpage, brk() shall deallocate memory in this case and currently it breaks a real-world application, specifically building the debian gcl package in

[PATCH] scripts/coverity-scan/model.c: update address_space_*_cached

Make prototypes correspond to their origins. Also drop address_space_rw_cached() which doesn't exist anywhere in the code. Signed-off-by: Vladimir Sementsov-Ogievskiy --- scripts/coverity-scan/model.c | 15 +-- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git

Re: [RFC v4 0/3] migration: reduce time of loading non-iterable vmstate

On 2022/12/23 下午11:50, Peter Xu wrote: Chuang, On Fri, Dec 23, 2022 at 10:23:04PM +0800, Chuang Xu wrote: In this version: - attach more information in the cover letter. - remove changes on virtio_load(). - add rcu_read_locked() to detect holding of rcu lock. The duration of loading

[PATCH v2 03/15] RISC-V: Adding XTheadBa ISA extension

From: Christoph Müllner This patch adds support for the XTheadBa ISA extension. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions Co-developed-by:

[PATCH v2 04/15] RISC-V: Adding XTheadBb ISA extension

From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Make implementation compatible with RV32. - Use single

[PATCH v2 08/15] RISC-V: Adding T-Head MemPair extension

From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_address() to calculate addresses Co-developed-by: LIU

[PATCH v2 07/15] RISC-V: Adding T-Head multiply-accumulate instructions

From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner ---

[PATCH v2 13/15] RISC-V: Add initial support for T-Head C906

From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner Changes in v2: - Drop C910 as it

[PATCH v2 12/15] RISC-V: Set minimum priv version for Zfh to 1.11

From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 +- 1

[PATCH v2 00/15] Add support for the T-Head vendor extensions

From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair *

[PATCH v2 15/15] target/riscv: add a MAINTAINERS entry for XThead* extension support

From: Christoph Müllner The XThead* extensions are maintained by T-Head and VRULL. Adding a point of contact from both companies. Signed-off-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS

[PATCH v2 14/15] RISC-V: Adding XTheadFmv ISA extension

From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/riscv/cpu.h

[PATCH v2 02/15] RISC-V: Adding XTheadSync ISA extension

From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Changes

[PATCH v2 09/15] RISC-V: Adding T-Head MemIdx extension

From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Avoid signed-bitfield-extraction by using signed immediate field

[PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension

From: Christoph Müllner This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific files. Future patches should be able to easily add additional T-Head extension. The implementation does not

[PATCH v2 11/15] RISC-V: Adding T-Head XMAE support

From: Christoph Müllner This patch adds support for the T-Head specific extended memory attributes. Similar like Svpbmt, this support does not have much effect as most behaviour is not modelled in QEMU. We also don't set any EDATA information, because XMAE discovery is done using the vendor ID

[PATCH v2 06/15] RISC-V: Adding XTheadCondMov ISA extension

From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix invalid use of register from dest_gpr() - Use single decoder for XThead extensions Co-developed-by:

[PATCH v2 10/15] RISC-V: Adding T-Head FMemIdx extension

From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_th_address_indexed for address calculations

[PATCH v2 05/15] RISC-V: Adding XTheadBs ISA extension

From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions Co-developed-by:

Re: [PATCH v4 00/12] Compiler warning fixes for libvhost-user,libvduse

On Fri, Dec 23, 2022 at 04:21:33PM +0100, Paolo Bonzini wrote: > On 12/22/22 21:36, Marcel Holtmann wrote: > > The libvhost-user and libvduse libraries are also useful for external > > usage outside of QEMU and thus it would be nice if their files could > > be just copied and used. However due to

[PULL v2 0/6] testing updates

The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b: Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +) are available in the Git repository at: https://gitlab.com/stsquad/qemu.git

Re: [PATCH v3 1/2] hw/arm/virt: Consolidate GIC finalize logic

Hey Cornelia, On 23.12.22 13:30, Cornelia Huck wrote: On Fri, Dec 23 2022, Alexander Graf wrote: Up to now, the finalize_gic_version() code open coded what is essentially a support bitmap match between host/emulation environment and desired target GIC type. This open coding leads to

Re: [PATCH v3] intel-iommu: Document iova_tree

On Fri, Dec 23, 2022 at 03:48:01PM +0800, Jason Wang wrote: > On Wed, Dec 7, 2022 at 6:13 AM Peter Xu wrote: > > > > It seems not super clear on when iova_tree is used, and why. Add a rich > > comment above iova_tree to track why we needed the iova_tree, and when we > > need it. > > > > Also

Re: [PATCH 3/3] intel-iommu: build iova tree during IOMMU translation

On Fri, Dec 23, 2022 at 04:02:29PM +0800, Jason Wang wrote: > On Tue, Dec 6, 2022 at 9:58 PM Peter Xu wrote: > > > > On Tue, Dec 06, 2022 at 11:18:03AM +0800, Jason Wang wrote: > > > On Tue, Dec 6, 2022 at 7:19 AM Peter Xu wrote: > > > > > > > > Jason, > > > > > > > > On Mon, Dec 05, 2022 at

Re: [PATCH 2/2] tests/migration: add support for ppc64le for guestperf.py

On 8/8/22 21:24, Murilo Opsfelder Araujo wrote: Add support for ppc64le for guestperf.py. On ppc, console is usually hvc0 and serial device for pseries machine is spapr-vty. Signed-off-by: Murilo Opsfelder Araujo --- Reviewed-by: Daniel Henrique Barboza

Re: [PATCH 1/2] tests/migration: add sysprof-capture-4 as dependency for stress binary

Until it's upstream or rejected, no patch will be left behind. I wasn't able to compile tests/migration/stress at all without this patch, regardless of having sysprof-4 libraries installed in the host. Reviewed-by: Daniel Henrique Barboza Juan/Dr.David, if you don't mind I'll take this

Re: [RFC v4 3/3] migration: reduce time of loading non-iterable vmstate

On 23.12.22 15:23, Chuang Xu wrote: The duration of loading non-iterable vmstate accounts for a significant portion of downtime (starting with the timestamp of source qemu stop and ending with the timestamp of target qemu start). Most of the time is spent committing memory region changes

Re: [RFC v4 2/3] memory: add depth assert in address_space_to_flatview

Hi, Paolo, On Fri, Dec 23, 2022 at 04:47:57PM +0100, Paolo Bonzini wrote: > On 12/23/22 15:23, Chuang Xu wrote: > > static inline FlatView *address_space_to_flatview(AddressSpace *as) > > { > > +/* > > + * Before using any flatview, sanity check we're not during a memory > > + *

Re: [RFC v4 0/3] migration: reduce time of loading non-iterable vmstate

Chuang, On Fri, Dec 23, 2022 at 10:23:04PM +0800, Chuang Xu wrote: > In this version: > > - attach more information in the cover letter. > - remove changes on virtio_load(). > - add rcu_read_locked() to detect holding of rcu lock. > > The duration of loading non-iterable vmstate accounts for a

Re: [RFC v4 2/3] memory: add depth assert in address_space_to_flatview

On 12/23/22 15:23, Chuang Xu wrote: static inline FlatView *address_space_to_flatview(AddressSpace *as) { +/* + * Before using any flatview, sanity check we're not during a memory + * region transaction or the map can be invalid. Note that this can + * also be called during

Re: [RFC v4 2/3] memory: add depth assert in address_space_to_flatview

On Fri, Dec 23, 2022 at 10:23:06PM +0800, Chuang Xu wrote: > Before using any flatview, sanity check we're not during a memory > region transaction or the map can be invalid. > > Signed-off-by: Chuang Xu > --- > include/exec/memory.h | 9 + > softmmu/memory.c | 5 + > 2 files

Re: [PATCH v4 00/12] Compiler warning fixes for libvhost-user,libvduse

Hi Paolo, >> The libvhost-user and libvduse libraries are also useful for external >> usage outside of QEMU and thus it would be nice if their files could >> be just copied and used. However due to different compiler settings, a >> lot of manual fixups are needed. This is the first attempt at

Re: [PATCH v4 00/12] Compiler warning fixes for libvhost-user,libvduse

On 12/22/22 21:36, Marcel Holtmann wrote: The libvhost-user and libvduse libraries are also useful for external usage outside of QEMU and thus it would be nice if their files could be just copied and used. However due to different compiler settings, a lot of manual fixups are needed. This is the

Re: [PULL v2 07/14] accel/tcg: Use interval tree for user-only page tracking

On Tue, Dec 20, 2022 at 09:03:06PM -0800, Richard Henderson wrote: > Finish weaning user-only away from PageDesc. > > Using an interval tree to track page permissions means that > we can represent very large regions efficiently. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/290 >

Re: [PATCH v2] pflash: Only read non-zero parts of backend image

On Tue, 20 Dec 2022 at 16:33, Gerd Hoffmann wrote: > > On Tue, Dec 20, 2022 at 10:30:43AM +0100, Philippe Mathieu-Daudé wrote: > > [Extending to people using UEFI VARStore on Virt machines] > > > > On 20/12/22 09:42, Gerd Hoffmann wrote: > > > From: Xiang Zheng > > > > > > Currently we fill the

[RFC v4 2/3] memory: add depth assert in address_space_to_flatview

Before using any flatview, sanity check we're not during a memory region transaction or the map can be invalid. Signed-off-by: Chuang Xu --- include/exec/memory.h | 9 + softmmu/memory.c | 5 + 2 files changed, 14 insertions(+) diff --git a/include/exec/memory.h

[RFC v4 1/3] rcu: introduce rcu_read_locked()

add rcu_read_locked() to detect holding of rcu lock. Signed-off-by: Chuang Xu --- include/qemu/rcu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/qemu/rcu.h b/include/qemu/rcu.h index b063c6fde8..42cbd0080f 100644 --- a/include/qemu/rcu.h +++ b/include/qemu/rcu.h @@ -119,6

[RFC v4 0/3] migration: reduce time of loading non-iterable vmstate

In this version: - attach more information in the cover letter. - remove changes on virtio_load(). - add rcu_read_locked() to detect holding of rcu lock. The duration of loading non-iterable vmstate accounts for a significant portion of downtime (starting with the timestamp of source qemu stop

[RFC v4 3/3] migration: reduce time of loading non-iterable vmstate

The duration of loading non-iterable vmstate accounts for a significant portion of downtime (starting with the timestamp of source qemu stop and ending with the timestamp of target qemu start). Most of the time is spent committing memory region changes repeatedly. This patch packs all the changes

Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes

On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis wrote: > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel wrote: > > > > On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis > > wrote: > > > > > > On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote: > > > > > > > > On Thu, Dec 8, 2022 at 9:00 AM

Re: [PATCH 13/15] hw/riscv/spike.c: simplify create_fdt()

On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza wrote: > > 'mem_size' and 'cmdline' aren't being used and the MachineState pointer > is being retrieved via a MACHINE() macro. > > Remove 'mem_size' and 'cmdline' and add MachineState as a parameter. Why do you add MachineState as a

Re: [PATCH 12/15] hw/riscv/boot.c: make riscv_load_initrd() static

On Thu, Dec 22, 2022 at 2:25 AM Daniel Henrique Barboza wrote: > > The only remaining caller is riscv_load_kernel() which belongs to the > same file. > > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 76 - >

Re: [PATCH 11/15] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()

On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza wrote: > > The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > the same steps when '-kernel' is used: > > - execute load_kernel() > - load init_rd() > - write kernel_cmdline > > Let's fold everything inside

Re: [PATCH v3 1/2] hw/arm/virt: Consolidate GIC finalize logic

On Fri, Dec 23 2022, Alexander Graf wrote: > Up to now, the finalize_gic_version() code open coded what is essentially > a support bitmap match between host/emulation environment and desired > target GIC type. > > This open coding leads to undesirable side effects. For example, a VM with > KVM

Re: [PATCH] linux-user: Improve strace output of personality() and sysinfo()

On 12/23/22 12:01, Philippe Mathieu-Daudé wrote: On 23/12/22 11:53, Helge Deller wrote: On 12/23/22 11:50, Philippe Mathieu-Daudé wrote: On 23/12/22 11:01, Helge Deller wrote: Make the strace look nicer for those two syscalls. Signed-off-by: Helge Deller ---   linux-user/strace.list | 4

Re: [PATCH] tests/tcg/multiarch: add vma-pthread.c

On Fri, 2022-12-23 at 13:02 +0100, Ilya Leoshkevich wrote: > Add a test that locklessly changes and exercises page protection bits > from various threads. This helps catch race conditions in the VMA > handling. > > Signed-off-by: Ilya Leoshkevich > --- >  tests/tcg/multiarch/Makefile.target  |  

[PATCH] tests/tcg/multiarch: add vma-pthread.c

Add a test that locklessly changes and exercises page protection bits from various threads. This helps catch race conditions in the VMA handling. Signed-off-by: Ilya Leoshkevich --- tests/tcg/multiarch/Makefile.target | 3 + tests/tcg/multiarch/munmap-pthread.c | 16 +--

[PULL 4/5] hw/9pfs: Drop unnecessary *xattr wrapper API declarations

From: Bin Meng These are not used anywhere in the source tree. Drop them. Signed-off-by: Bin Meng Reviewed-by: Greg Kurz Message-Id: <20221219102022.2167736-3-bin.m...@windriver.com> Signed-off-by: Christian Schoenebeck --- hw/9pfs/9p-util.h | 11 --- 1 file changed, 11 deletions(-)

[PULL 5/5] hw/9pfs: Replace the direct call to xxxat() APIs with a wrapper

From: Bin Meng xxxat() APIs are only available on POSIX platforms. For future extension to Windows, let's replace the direct call to xxxat() APIs with a wrapper. Signed-off-by: Bin Meng Message-Id: <20221219102022.2167736-4-bin.m...@windriver.com> Signed-off-by: Christian Schoenebeck ---

[PULL 3/5] qemu/xattr.h: Exclude for Windows

From: Bin Meng Windows does not have . Signed-off-by: Bin Meng Message-Id: <20221219102022.2167736-2-bin.m...@windriver.com> Signed-off-by: Christian Schoenebeck --- include/qemu/xattr.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/qemu/xattr.h

[PULL 0/5] 9p queue 2022-12-23

The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b: Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +) are available in the Git repository at: https://github.com/cschoenebeck/qemu.git tags/pull-9p-20221223

[PULL 1/5] 9pfs: Fix some return statements in the synth backend

From: Greg Kurz The qemu_v9fs_synth_mkdir() and qemu_v9fs_synth_add_file() functions currently return a positive errno value on failure. This causes checkpatch.pl to spit several errors like the one below: ERROR: return of an errno should typically be -ve (return -EAGAIN) +return

[PULL 2/5] MAINTAINERS: Add 9p test client to section "virtio-9p"

The 9p test cases use a dedicated, lite-weight 9p client implementation (using virtio transport) under tests/qtest/libqos/ to communicate with QEMU's 9p server. It's already there for a long time. Let's officially assign it to 9p maintainers. Signed-off-by: Christian Schoenebeck Reviewed-by:

Re: [PATCH] linux-user: Improve strace output of personality() and sysinfo()

On 23/12/22 11:53, Helge Deller wrote: On 12/23/22 11:50, Philippe Mathieu-Daudé wrote: On 23/12/22 11:01, Helge Deller wrote: Make the strace look nicer for those two syscalls. Signed-off-by: Helge Deller ---   linux-user/strace.list | 4 ++--   1 file changed, 2 insertions(+), 2

Re: [PATCH 10/15] hw/riscv/boot.c: use MachineState in riscv_load_kernel()

On Thu, Dec 22, 2022 at 2:24 AM Daniel Henrique Barboza wrote: > > All callers are using kernel_filename as machine->kernel_filename. > > This will also simplify the changes in riscv_load_kernel() that we're > going to do next. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza >

Re: [PATCH] nubus-device: fix memory leak in nubus_device_realize

On 22/12/22 18:29, Mauro Matteo Cascella wrote: Local variable "name" is allocated through strdup_printf and should be freed with g_free() to avoid memory leak. Fixes: 3616f424 ("nubus-device: add romfile property for loading declaration ROMs") Signed-off-by: Mauro Matteo Cascella ---

Re: [PATCH] linux-user: Improve strace output of personality() and sysinfo()

On 12/23/22 11:50, Philippe Mathieu-Daudé wrote: On 23/12/22 11:01, Helge Deller wrote: Make the strace look nicer for those two syscalls. Signed-off-by: Helge Deller ---   linux-user/strace.list | 4 ++--   1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/strace.list

Re: [PATCH] linux-user: Improve strace output of personality() and sysinfo()

On 23/12/22 11:01, Helge Deller wrote: Make the strace look nicer for those two syscalls. Signed-off-by: Helge Deller --- linux-user/strace.list | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/strace.list b/linux-user/strace.list index

Re: [PATCH v2 4/4] docs/devel: Rules on #include in headers

Am 22. Dezember 2022 12:08:13 UTC schrieb Markus Armbruster : >Rules for headers were proposed a long time ago, and generally liked: > >Message-ID: <87h9g8j57d@blackfin.pond.sub.org> >https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html > >Wortk them into

Re: [PATCH 09/15] hw/riscv/boot.c: use MachineState in riscv_load_initrd()

On Thu, Dec 22, 2022 at 2:24 AM Daniel Henrique Barboza wrote: > > 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be > retrieved by the MachineState object for all callers. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c| 6

Re: [PATCH v2 0/7] include/hw/pci include/hw/cxl: Clean up includes

Am 23. Dezember 2022 05:27:07 UTC schrieb Markus Armbruster : >"Michael S. Tsirkin" writes: > >> On Thu, Dec 22, 2022 at 11:48:25AM +0100, Markus Armbruster wrote: >>> Bernhard Beschow writes: >>> >>> > Am 22. Dezember 2022 10:03:23 UTC schrieb Markus Armbruster >>> > : >>> >>Back in 2016,

Re: [PATCH 08/15] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()

On Thu, Dec 22, 2022 at 2:24 AM Daniel Henrique Barboza wrote: > > The sifive_u, spike and virt machines are writing the 'bootargs' FDT > node during their respective create_fdt(). > > Given that bootargs is written only when '-append' is used, and this > option is only allowed with the '-kernel'

[PATCH] linux-user: Fix brk() to release pages

The current brk() implementation does not de-allocate pages if a lower address is given compared to earlier brk() calls. But according to the manpage, brk() shall deallocate memory in this case and currently it breaks a real-world application, specifically building the debian gcl package in

Re: [PATCH 07/15] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()

On Thu, Dec 22, 2022 at 2:24 AM Daniel Henrique Barboza wrote: > > riscv_load_initrd() returns the initrd end addr while also writing a > 'start' var to mark the addr start. These informations are being used > just to write the initrd FDT node. Every existing caller of > riscv_load_initrd() is

Re: [PATCH 0/2] hw/intc/arm_gicv3: Bump ITT entry size to 16

On 23/12/22 09:50, Alexander Graf wrote: While trying to make Windows work with GICv3 emulation, I stumbled over the fact that it only supports ITT entry sizes that are power of 2 sized. While the spec allows arbitrary sizes, in practice hardware will always expose power of 2 sizes and so this

Re: [PATCH 5/6] hw/arm/xilinx_zynq: Remove tswap32() calls and constify smpboot[]

On 23/12/22 11:01, Philippe Mathieu-Daudé wrote: On 23/12/22 04:54, Edgar E. Iglesias wrote: On Thu, Dec 22, 2022 at 10:55:48PM +0100, Philippe Mathieu-Daudé wrote: ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. We call tswap32() on

Re: [PATCH 06/15] hw/riscv/spike.c: load initrd right after riscv_load_kernel()

On Thu, Dec 22, 2022 at 2:28 AM Daniel Henrique Barboza wrote: > > This will make the code more in line with what the other boards are > doing. We'll also avoid an extra check to machine->kernel_filename since > we already checked that before executing riscv_load_kernel(). > > Signed-off-by:

[PATCH] linux-user: Improve strace output of personality() and sysinfo()

Make the strace look nicer for those two syscalls. Signed-off-by: Helge Deller --- linux-user/strace.list | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/strace.list b/linux-user/strace.list index f9254725a1..909298099e 100644 --- a/linux-user/strace.list +++

Re: [PATCH 5/6] hw/arm/xilinx_zynq: Remove tswap32() calls and constify smpboot[]

On 23/12/22 04:54, Edgar E. Iglesias wrote: On Thu, Dec 22, 2022 at 10:55:48PM +0100, Philippe Mathieu-Daudé wrote: ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. We call tswap32() on the array. tswap32 function swap a 32-bit value

Re: [PATCH v3 1/6] migration: Allow immutable device state to be migrated early (i.e., before RAM)

On 22.12.22 12:02, David Hildenbrand wrote: For virtio-mem, we want to have the plugged/unplugged state of memory blocks available before migrating any actual RAM content. This information is immutable on the migration source while migration is active, For example, we want to use this

Re: [PATCH 05/15] hw/riscv/boot.c: introduce riscv_default_firmware_name()

On Thu, Dec 22, 2022 at 2:28 AM Daniel Henrique Barboza wrote: > > Some boards are duplicating the 'riscv_find_and_load_firmware' call > because the 32 and 64 bits images have different names. Create > a function to handle this detail instead of hardcoding it in the boards. > > Ideally we would

Re: [PATCH v2 1/2] hw/intc/loongarch_pch_msi: add irq number property

Tianrui, We should solve all the issues in the previous mailing list, and send the next version. https://patchwork.kernel.org/project/qemu-devel/patch/20221215065011.2133471-2-zhaotian...@loongson.cn/ We should not be in such hurry:) regards bibo,mao 在 2022/12/23 16:08, Tianrui Zhao

Re: [PATCH 04/15] hw/riscv/boot.c: make riscv_find_firmware() static

On Thu, Dec 22, 2022 at 2:27 AM Daniel Henrique Barboza wrote: > > The only caller is riscv_find_and_load_firmware(), which is in the same > file. > > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 44 - > include/hw/riscv/boot.h

Re: [PATCH 03/15] hw/riscv/sifive_u: use 'fdt' from MachineState

On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza wrote: > > The MachineState object provides a 'fdt' pointer that is already being > used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP > command. > > Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt >

Re: [PATCH 02/15] hw/riscv/spike: use 'fdt' from MachineState

On Thu, Dec 22, 2022 at 2:24 AM Daniel Henrique Barboza wrote: > > The MachineState object provides a 'fdt' pointer that is already being > used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP > command. > > Remove the 'fdt' pointer from SpikeState and use MachineState::fdt >

[PATCH v3 0/2] hw/arm/virt: Handle HVF in finalize_gic_version()

The finalize_gic_version() function tries to determine which GIC version the current accelerator / host combination supports. During the initial HVF porting efforts, I didn't realize that I also had to touch this function. Then Zenghui brought up this function as reply to my HVF GICv3 enablement

[PATCH v3 2/2] hw/arm/virt: Make accels in GIC finalize logic explicit

Let's explicitly list out all accelerators that we support when trying to determine the supported set of GIC versions. KVM was already separate, so the only missing one is HVF which simply reuses all of TCG's emulation code and thus has the same compatibility matrix. Signed-off-by: Alexander Graf

[PATCH v3 1/2] hw/arm/virt: Consolidate GIC finalize logic

Up to now, the finalize_gic_version() code open coded what is essentially a support bitmap match between host/emulation environment and desired target GIC type. This open coding leads to undesirable side effects. For example, a VM with KVM and -smp 10 will automatically choose GICv3 while the

[PATCH 0/2] hw/intc/arm_gicv3: Bump ITT entry size to 16

While trying to make Windows work with GICv3 emulation, I stumbled over the fact that it only supports ITT entry sizes that are power of 2 sized. While the spec allows arbitrary sizes, in practice hardware will always expose power of 2 sizes and so this limitation is not really a problem in real

[PATCH 1/2] hw/intc/arm_gicv3: Make ITT entry size configurable

An ITT entry is opaque to the OS. The only thing it does get told by HW is its size. In theory, that size can be any byte aligned number, in practice HW will always use power of 2s to simplify offset calculation. We currently expose the size as 12, which is not a power of 2. To prepare for a

[PATCH 2/2] hw/intc/arm_gicv3: Bump ITT entry size to 16

Some Operating Systems (like Windows) can only deal with ITT entry sizes that are a power of 2. While the spec allows arbitrarily sized ITT entry sizes, in practice all hardware will use power of 2 because that simplifies offset calculation and ensures that a power of 2 sized region can hold a set

Re: [PATCH v10 1/9] mm: Introduce memfd_restricted system call to create restricted user memory

On Thu, Dec 22, 2022 at 06:15:24PM +, Sean Christopherson wrote: > On Wed, Dec 21, 2022, Chao Peng wrote: > > On Tue, Dec 20, 2022 at 08:33:05AM +, Huang, Kai wrote: > > > On Tue, 2022-12-20 at 15:22 +0800, Chao Peng wrote: > > > > On Mon, Dec 19, 2022 at 08:48:10AM +, Huang, Kai

Re: [PATCH v10 1/9] mm: Introduce memfd_restricted system call to create restricted user memory

On Thu, Dec 22, 2022 at 12:37:19AM +, Huang, Kai wrote: > On Wed, 2022-12-21 at 21:39 +0800, Chao Peng wrote: > > > On Tue, Dec 20, 2022 at 08:33:05AM +, Huang, Kai wrote: > > > > > On Tue, 2022-12-20 at 15:22 +0800, Chao Peng wrote: > > > > > > > On Mon, Dec 19, 2022 at 08:48:10AM +,

[PATCH v2 1/2] hw/intc/loongarch_pch_msi: add irq number property

This patch adds irq number property for loongarch msi interrupt controller, and remove hard coding irq number macro. Signed-off-by: Tianrui Zhao --- hw/intc/loongarch_pch_msi.c | 30 ++--- hw/loongarch/virt.c | 11 +++

[PATCH v2 0/2] Add irq number property for loongarch pch interrupt controller

This series add irq number property for loongarch pch_msi and pch_pic interrupt controller. Changes for v2: (1) Free pch_msi_irq array in pch_msi_unrealize(). Changes for v1: (1) Add irq number property for loongarch_pch_msi. (2) Add irq number property for loongarch_pch_pic. Tianrui Zhao (2):

[PATCH v2 2/2] hw/intc/loongarch_pch_pic: add irq number property

With loongarch 7A1000 manual, irq number supported can be set in PCH_PIC_INT_ID_HI register. This patch adds irq number property for loongarch_pch_pic, so that virt machine can set different irq number when pch_pic intc is added. Signed-off-by: Tianrui Zhao --- hw/intc/loongarch_pch_pic.c

Re: [PATCH 3/3] intel-iommu: build iova tree during IOMMU translation

On Tue, Dec 6, 2022 at 9:58 PM Peter Xu wrote: > > On Tue, Dec 06, 2022 at 11:18:03AM +0800, Jason Wang wrote: > > On Tue, Dec 6, 2022 at 7:19 AM Peter Xu wrote: > > > > > > Jason, > > > > > > On Mon, Dec 05, 2022 at 12:12:04PM +0800, Jason Wang wrote: > > > > I'm fine to go without iova-tree.