On 2023/01/14 14:23, Richard Henderson wrote:
On 1/8/23 22:22, Akihiko Odaki wrote:
libvirt uses "none" machine type to test KVM availability. Before this
change, QEMU used to pass 0 as machine type when calling KVM_CREATE_VM.
The kernel documentation says:
On arm64, the physical address size
During the conversion, the test against get_phys_addr_lpae got inverted,
meaning that successful translations went to the 'failed' label.
Cc: qemu-sta...@nongnu.org
Fixes: f3639a64f60 ("target/arm: Use softmmu tlbs for page table walking")
Resolves:
Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
as noted in docs/igd-assign.txt in the Qemu source code.
Currently, when the xl toolstack is used to configure a Xen HVM guest with
Intel IGD passthrough to the guest with the Qemu upstream device model,
a Qemu emulated PCI
On 1/8/23 22:22, Akihiko Odaki wrote:
libvirt uses "none" machine type to test KVM availability. Before this
change, QEMU used to pass 0 as machine type when calling KVM_CREATE_VM.
The kernel documentation says:
On arm64, the physical address size for a VM (IPA Size limit) is
limited to 40bits
Some definitions in the header files are invalid for igb so extract
them to new header files to keep igb from referring to them.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 1 +
They are duplicate of running throttling timer flags and incomplete as
the flags are not cleared when the interrupts are fired or the device is
reset.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e.c | 5 ++---
hw/net/e1000e_core.c | 19 +++
hw/net/e1000e_core.h | 2 --
The definitions for E1000_VFTA_ENTRY_SHIFT, E1000_VFTA_ENTRY_MASK, and
E1000_VFTA_ENTRY_BIT_SHIFT_MASK were copied from:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.h?h=v6.0.9#n306
The definitions for E1000_NUM_UNICAST,
Signed-off-by: Akihiko Odaki
---
tests/qtest/fuzz/generic_fuzz_configs.h | 5 +
tests/qtest/igb-test.c | 67 ++--
tests/qtest/libqos/igb.c| 139 +---
tests/qtest/libqos/meson.build | 1 +
tests/qtest/meson.build
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000e.c | 10
They will be useful for igb testing.
Signed-off-by: Akihiko Odaki
---
tests/qtest/libqos/e1000e.c | 12
tests/qtest/libqos/e1000e.h | 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c
index
e1000e understands ethernet header so fabricate something convincing.
Signed-off-by: Akihiko Odaki
---
tests/qtest/e1000e-test.c | 17 +++--
tests/qtest/libqos/e1000e.h | 2 ++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/e1000e-test.c
This automates ethtool tests for igb registers, interrupts, etc.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 1 +
.../org.centos/stream/8/x86_64/test-avocado | 1 +
tests/avocado/igb.py | 38 +++
3 files changed,
Start off igb test implementation by copying e1000e code first as igb
resembles e1000e.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 +
tests/qtest/igb-test.c | 242 +++
tests/qtest/libqos/igb.c | 226
This keeps Windows driver 12.18.9.23 from generating an event with ID
30. The description of the event is as follows:
> Intel(R) 82574L Gigabit Network Connection
> PROBLEM: The network adapter is configured for auto-negotiation but
> the link partner is not. This may result in a duplex
Before this change, e1000e_write_packet_to_guest() allocated the
receive descriptor buffer as an array of uint8_t. This does not ensure
the buffer is sufficiently aligned.
Introduce e1000_rx_desc_union type, a union type of all receive
descriptor types to correct this.
Signed-off-by: Akihiko
Based-on: <20230114035919.35251-1-akihiko.od...@daynix.com>
([PATCH 00/19] e1000x cleanups (preliminary for IGB))
igb is a family of Intel's gigabit ethernet controllers. This series implements
82576 emulation in particular. You can see the last patch for the documentation.
Note that there is
Rename identifiers of definitions which will be modified later for igb.
This will also allow to build igb along with e1000e.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
hw/net/igb.c| 368 +-
hw/net/igb_common.h |6 +-
Start off igb implementation by copying e1000e code first as igb
resembles e1000e.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
MAINTAINERS |5 +
hw/net/igb.c| 727 +
hw/net/igb_common.h | 102 ++
hw/net/igb_core.c
This change makes e1000e reset more things when software reset was
triggered. Some registers are exempted from software reset in the
datasheet and this change also implements the behavior accordingly.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 24 +++-
1 file
igb can use this function to change its behavior depending on the
number of virtual functions currently enabled.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pcie_sriov.c | 5 +
Expose the ethernet header so that igb can utilize it to perform the
internal routing among its SR-IOV functions.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
hw/net/net_tx_pkt.c | 6 ++
hw/net/net_tx_pkt.h | 8
2 files changed, 14
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 1 +
docs/system/device-emulation.rst | 1 +
docs/system/devices/igb.rst | 70
3 files changed, 72 insertions(+)
create mode 100644 docs/system/devices/igb.rst
diff --git a/MAINTAINERS
Currently igb functions identically with e1000e.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
hw/net/Kconfig | 5 +
hw/net/meson.build | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
index
This is part of recent efforts of refactoring e1000 and e1000e.
DeviceClass's reset member is deprecated so migrate to ResettableClass.
There is no behavioral difference.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 13
igb implementation first starts off by copying e1000e code. Correct the
code style before that.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
tests/qtest/e1000e-test.c | 2 +-
tests/qtest/libqos/e1000e.c | 6 --
2 files changed, 5 insertions(+), 3 deletions(-)
The register definitions in tests/qtest/libqos/e1000e.h had names
different from hw/net/e1000_regs.h, which made it hard to understand
what test codes corresponds to the implementation. Use
hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove
these duplications.
Signed-off-by: Akihiko
Use memcpy instead of memmove to initialize registers. The initial
register templates and register table instances will never overlap.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 94
The definitions of SW Semaphore Register were copied from:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?h=v6.0.9#n374
Signed-off-by: Akihiko Odaki
---
hw/net/e1000_regs.h | 7 +++
hw/net/e1000e_core.c | 49
We are adding a new device named igb, yet another Intel NIC. As the new
implementation derives from e1000e, overhaul e1000e implementation first.
e1000 has many commonalities with e1000e so we also apply the corresponding
changes to the device if possible.
This was spun off from:
e1000e_write_packet_to_guest() passes the reference of variable ba as a
pointer to an array, and that pointer indirection is just unnecessary;
all functions which uses the passed reference performs no pointer
operation on the pointer and they simply dereference the passed
pointer. Remove the extra
Use memcpy instead of memmove to initialize registers. The initial
register templates and register table instances will never overlap.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000e_core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/e1000e_core.c
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki
---
hw/net/e1000.c | 84
igb implementation first starts off by copying e1000e code. Correct the
code style before that.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 41
hw/net/e1000e.c| 72 ++--
hw/net/e1000e_core.c
hw/net/mii.h provides common definitions for MII.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/fsl_etsec/etsec.c | 11 ++-
hw/net/fsl_etsec/etsec.h | 17 -
hw/net/fsl_etsec/miim.c | 5 +++--
include/hw/net/mii.h | 1 +
4 files
hw/net/mii.h provides common definitions for MII.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 86 ++--
hw/net/e1000_regs.h| 46
hw/net/e1000e.c| 1 +
hw/net/e1000e_core.c | 99
The definitions will be used by igb.
Signed-off-by: Akihiko Odaki
---
include/hw/net/mii.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
index 4ae4dcce7e..c6a767a49a 100644
--- a/include/hw/net/mii.h
+++
Conversion to probe_access_full missed applying the page offset.
Fixes: b8967ddf ("target/arm: Use probe_access_full for MTE")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1416
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 2 +-
1 file changed, 1 insertion(+), 1
On 2023/01/13 22:40, Philippe Mathieu-Daudé wrote:
On 13/1/23 14:08, Akihiko Odaki wrote:
filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
virtio-net header. Having virtio-net header in such PCAP file breaks
PCAP unconsumable. Unfortunately currently there is no LinkType
On 1/10/23 3:16 AM, Michael S. Tsirkin wrote:
> On Tue, Jan 10, 2023 at 02:08:34AM -0500, Chuck Zmudzinski wrote:
>> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
>> as noted in docs/igd-assign.txt in the Qemu source code.
>>
>> Currently, when the xl toolstack is used to
filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
virtio-net header. Having virtio-net header in such PCAP file breaks
PCAP unconsumable. Unfortunately currently there is no LinkType for
virtio-net so for now strip virtio-net header to convert the output to
Ethernet.
On 2023/01/13 22:43, BALATON Zoltan wrote:
On Thu, 5 Jan 2023, BALATON Zoltan wrote:
Hello,
I got reports from several users trying to run AmigaOS4 on sam460ex on
Apple silicon Macs that they get missing graphics that I can't
reproduce on x86_64. With help from the users who get the problem
On 1/5/23 10:15, Alex Bennée wrote:
Currently when we encounter a gdb that is old or not built with
multiarch in mind we fail rather messily. Try and improve the
situation by probing ahead of time and setting
HOST_GDB_SUPPORTS_ARCH=y in the relevant tcg configs. We can then skip
and give a more
We have a test for one of TCG_TARGET_HAS_mulu2_i32 or
TCG_TARGET_HAS_muluh_i32 being defined, but the test
became non-functional when we changed to always define
all of these macros.
Replace this with a build-time test in tcg_gen_mulu2_i32.
Fixes: 25c4d9cc845 ("tcg: Always define all of the
On 1/12/23 07:20, Ilya Leoshkevich wrote:
v3 -> v4:
* s/unsigned long long/uint64_t/g (Richard).
* Fix address resolution with TARGET_TB_PCREL again.
* Open question: do we need something like get_pc_from_opc()?
See FIXME in patch 3.
Looks good. I'll queue this to tcg-next.
Ideally,
From: David Woodhouse
Signed-off-by: David Woodhouse
---
hw/i386/kvm/xen_evtchn.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c
index 18c88229ab..c4103ee98b 100644
--- a/hw/i386/kvm/xen_evtchn.c
+++ b/hw/i386/kvm/xen_evtchn.c
@@
From: David Woodhouse
The way that Xen handles MSI PIRQs is kind of awful.
There is a special MSI message which targets a PIRQ. The vector in the
low bits of data must be zero. The low 8 bits of the PIRQ# are in the
destination ID field, the extended destination ID field is unused, and
instead
From: David Woodhouse
If I advertise XENFEAT_hvm_pirqs then a guest now boots successfully as
long as I tell it 'pci=nomsi'.
[root@localhost ~]# cat /proc/interrupts
CPU0
0: 52 IO-APIC 2-edge timer
1: 16 xen-pirq 1-ioapic-edge i8042
4: 1534
From: David Woodhouse
This wires up the basic infrastructure but the actual interrupts aren't
there yet, so don't advertise it to the guest.
Signed-off-by: David Woodhouse
---
hw/i386/kvm/trace-events | 4 +
hw/i386/kvm/trace.h | 1 +
hw/i386/kvm/xen_evtchn.c | 265
This continues to build on the basic Xen on KVM platform support from
https://lore.kernel.org/qemu-devel/20230110122042.1562155-1-dw...@infradead.org/
We're working on hooking up the PV backend devices, and the biggest
remaining noticeably missing part was PIRQ support. This allows a Xen
guest
From: David Woodhouse
Just hook up the basic hypercalls to stubs in xen_evtchn.c for now.
Signed-off-by: David Woodhouse
---
hw/i386/kvm/xen_evtchn.c | 25
hw/i386/kvm/xen_evtchn.h | 11
target/i386/kvm/xen-compat.h | 19 ++
target/i386/kvm/xen-emu.c| 118
On Fri, Dec 02, 2022, Chao Peng wrote:
> This patch series implements KVM guest private memory for confidential
> computing scenarios like Intel TDX[1]. If a TDX host accesses
> TDX-protected guest memory, machine check can happen which can further
> crash the running host system, this is terrible
On Fri, Dec 02, 2022, Chao Peng wrote:
> @@ -10357,6 +10364,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
>
> if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
> static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
> +
> +
On Fri, Dec 02, 2022, Chao Peng wrote:
> @@ -5599,6 +5652,9 @@ int noinline kvm_mmu_page_fault(struct kvm_vcpu *vcpu,
> gpa_t cr2_or_gpa, u64 err
> return -EIO;
> }
>
> + if (r == RET_PF_USER)
> + return 0;
> +
> if (r < 0)
>
On Fri, Dec 02, 2022, Chao Peng wrote:
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 9a07380f8d3c..5aefcff614d2 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -12362,6 +12362,8 @@ static int kvm_alloc_memslot_metadata(struct kvm *kvm,
> if
On Fri, Dec 02, 2022, Chao Peng wrote:
> diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
> index 99352170c130..d9edb14ce30b 100644
> --- a/Documentation/virt/kvm/api.rst
> +++ b/Documentation/virt/kvm/api.rst
> @@ -6634,6 +6634,28 @@ array field represents return
On Fri, Dec 02, 2022, Chao Peng wrote:
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 283cbb83d6ae..7772ab37ac89 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -38,6 +38,7 @@
> #include
>
> #define
On Fri, Dec 02, 2022, Chao Peng wrote:
> @@ -785,11 +786,12 @@ struct kvm {
>
> #if defined(CONFIG_MMU_NOTIFIER) && defined(KVM_ARCH_WANT_MMU_NOTIFIER)
> struct mmu_notifier mmu_notifier;
> +#endif
> unsigned long mmu_invalidate_seq;
> long mmu_invalidate_in_progress;
>
On 1/13/23 06:04, Fabiano Rosas wrote:
config CHEETAH
bool
+default y if TCG && (ARM || AARCH64)
Shouldn't need both ARM and AARCH64?
r`
On 1/13/23 06:04, Fabiano Rosas wrote:
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific
On Tue, Jan 10, 2023, Chao Peng wrote:
> On Mon, Jan 09, 2023 at 07:32:05PM +, Sean Christopherson wrote:
> > On Fri, Jan 06, 2023, Chao Peng wrote:
> > > On Thu, Jan 05, 2023 at 11:23:01AM +, Jarkko Sakkinen wrote:
> > > > On Fri, Dec 02, 2022 at 02:13:41PM +0800, Chao Peng wrote:
> > > >
On 1/13/23 06:04, Fabiano Rosas wrote:
If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.
We can now write tests without explicit calls to require_accelerator,
just the tag is enough.
Signed-off-by: Fabiano Rosas
---
On 1/13/23 06:04, Fabiano Rosas wrote:
This allows the test to be skipped when TCG is not present in the QEMU
binary.
Signed-off-by: Fabiano Rosas
---
tests/avocado/boot_linux_console.py | 1 +
tests/avocado/reverse_debugging.py | 8
2 files changed, 9 insertions(+)
Reviewed-by:
On 1/13/23 06:04, Fabiano Rosas wrote:
We will soon enable the build without TCG, which does not support many
machines, so only run the bcm2835-dma-test when the corresponding
machine is present.
Signed-off-by: Fabiano Rosas
---
tests/qtest/meson.build | 4 ++--
1 file changed, 2
On 1/13/23 06:04, Fabiano Rosas wrote:
@@ -373,6 +387,11 @@ static void sve_tests_sve_off(const void *data)
{
QTestState *qts;
+if (tcg_disabled()) {
+g_test_skip("TCG support is disabled in this build");
+return;
+}
+
qts = qtest_init(MACHINE "-cpu
On 1/13/23 08:22, Fabiano Rosas wrote:
Claudio Fontana writes:
On 1/13/23 15:04, Fabiano Rosas wrote:
The cortex-a15 is not present anymore when CONFIG_TCG=n, so use the
cortex-a57 as default cpu for KVM.
Signed-off-by: Fabiano Rosas
Our recommendation currently for KVM on ARM is to
On 1/13/23 06:04, Fabiano Rosas wrote:
The cortex-a15 is not present anymore when CONFIG_TCG=n, so use the
cortex-a57 as default cpu for KVM.
Signed-off-by: Fabiano Rosas
Ideally there would not be a default at all, requiring the command-line option
to be used.
Second choice would be
On Fri, Dec 02, 2022, Chao Peng wrote:
> diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
> index fbeaa9ddef59..a8e379a3afee 100644
> --- a/arch/x86/kvm/Kconfig
> +++ b/arch/x86/kvm/Kconfig
> @@ -49,6 +49,7 @@ config KVM
> select SRCU
> select INTERVAL_TREE
> select
On 1/13/23 06:04, Fabiano Rosas wrote:
The cpu_tcg.c file about to be moved into the tcg directory. Move the
code that is needed for cpus that also work with KVM into cpu.c.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu.c | 76 +++
On 1/13/23 06:04, Fabiano Rosas wrote:
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into cpregs.c along with all the others.
Signed-off-by: Fabiano Rosas
---
target/arm/cpregs.c| 59 ++
On 1/13/23 06:04, Fabiano Rosas wrote:
This is in preparation to moving the hflags code into its own file
under the tcg/ directory.
Signed-off-by: Fabiano Rosas
---
I extracted these into a separate patch so we can discuss. If I move
the tcg_enabled check to a header that would add overhead for
On Fri, Dec 02, 2022, Chao Peng wrote:
> The system call is currently wired up for x86 arch.
Building on other architectures (except for arm64 for some reason) yields:
CALL/.../scripts/checksyscalls.sh
:1565:2: warning: #warning syscall memfd_restricted not implemented
[-Wcpp]
Do we
On 1/13/23 06:03, Fabiano Rosas wrote:
This is in preparation for moving debug_helper.c into a TCG-specific
directory.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu.c | 6 --
target/arm/machine.c | 7 +--
2 files changed, 9 insertions(+), 4 deletions(-)
Reviewed-by: Richard
On 1/13/23 06:03, Fabiano Rosas wrote:
Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.
Code moved verbatim.
Signed-off-by: Fabiano Rosas
---
target/arm/cpregs.h | 98 +
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Friday, January 13, 2023 7:39 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; richard.hender...@linaro.org
> Subject: [PATCH 2/2] Hexagon (decode): look for pkts with multiple insns at
> the same slot
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Friday, January 13, 2023 7:39 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; richard.hender...@linaro.org
> Subject: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constraints
>
> The Hexagon
On 1/13/23 05:39, Alex Bennée wrote:
Alex Bennée (4):
docs: add hotlinks to about preface text
docs: add a new section to outline emulation support
semihosting: add semihosting section to the docs
docs: add an introduction to the system docs
Looks ok.
Acked-by: Richard Henderson
On 1/13/23 4:33 AM, Igor Mammedov wrote:
> On Thu, 12 Jan 2023 23:14:26 -0500
> Chuck Zmudzinski wrote:
>
>> On 1/12/23 6:03 PM, Michael S. Tsirkin wrote:
>> > On Thu, Jan 12, 2023 at 10:55:25PM +, Bernhard Beschow wrote:
>> >> I think the change Michael suggests is very minimalistic: Move
From: Emanuele Giuseppe Esposito
bdrv_eject() is categorized as an I/O function, and it currently
doesn't run in a coroutine. We should let it take a graph rdlock since
it traverses the block nodes graph, which however is only possible in a
coroutine.
The only caller of this function is
From: Emanuele Giuseppe Esposito
bdrv_get_info() is categorized as an I/O function, and it currently
doesn't run in a coroutine. We should let it take a graph rdlock since
it traverses the block nodes graph, which however is only possible in a
coroutine.
Therefore turn it into a co_wrapper to
From: Emanuele Giuseppe Esposito
bdrv_debug_event() is categorized as an I/O function, and it currently
doesn't run in a coroutine. We should let it take a graph rdlock since
it traverses the block nodes graph, which however is only possible in a
coroutine.
Therefore turn it into a
From: Emanuele Giuseppe Esposito
The name is not good, not the least because we are going to convert this
to a generated co_wrapper, which adds a _co infix after the first part
of the name.
No functional change intended.
Signed-off-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
From: Emanuele Giuseppe Esposito
bdrv_is_inserted() is categorized as an I/O function, and it currently
doesn't run in a coroutine. We should let it take a graph rdlock since
it traverses the block nodes graph, which however is only possible in a
coroutine.
Therefore turn it into a co_wrapper
From: Emanuele Giuseppe Esposito
bdrv_get_allocated_file_size() is categorized as an I/O function, and it
currently doesn't run in a coroutine. We should let it take a graph
rdlock since it traverses the block nodes graph, which however is only
possible in a coroutine.
Therefore turn it into a
From: Emanuele Giuseppe Esposito
BlockDriver->bdrv_io_unplug is categorized as IO callback, and it
currently doesn't run in a coroutine. We should let it take a graph
rdlock since the callback traverses the block nodes graph, which however
is only possible in a coroutine.
The only caller of
From: Emanuele Giuseppe Esposito
In some places we are sure we are always running in a
coroutine, therefore it's useless to call the generated_co_wrapper,
instead call directly the _co_ function.
Signed-off-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
block/block-backend.c |
From: Emanuele Giuseppe Esposito
Since these functions always run in coroutine context, adjust
their name to include "_co_", just like all other BlockDriver callbacks.
No functional change intended.
Signed-off-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
From: Emanuele Giuseppe Esposito
BlockDriver->bdrv_getlength is categorized as IO callback, and it
currently doesn't run in a coroutine. We should let it take a graph
rdlock since the callback traverses the block nodes graph, which however
is only possible in a coroutine.
Therefore turn it into
From: Emanuele Giuseppe Esposito
bdrv_lock_medium() is categorized as an I/O function, and it currently
doesn't run in a coroutine. We should let it take a graph rdlock since
it traverses the block nodes graph, which however is only possible in a
coroutine.
The only caller of this function is
This series converts some IO_CODE() functions to coroutine_fn because
they access the graph and will need to hold the graph lock in the
future. IO_CODE() functions can be called from iothreads, so taking the
graph lock requires the function to run in coroutine context.
Pretty much all of the
From: Emanuele Giuseppe Esposito
Just omit the various 'return' when the return type is void.
Signed-off-by: Emanuele Giuseppe Esposito
Signed-off-by: Kevin Wolf
---
scripts/block-coroutine-wrapper.py | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git
From: Emanuele Giuseppe Esposito
The only difference is that blk_ checks if the block is available,
but this check is already performed above in blk_check_byte_request().
This is in preparation for the graph rdlock, which will be taken
by both the callers of blk_check_byte_request() and
From: Emanuele Giuseppe Esposito
BlockDriver->bdrv_io_plug is categorized as IO callback, and it
currently doesn't run in a coroutine. We should let it take a graph
rdlock since the callback traverses the block nodes graph, which however
is only possible in a coroutine.
The only caller of this
)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20230113
for you to fetch changes up to 4828656f65324249273ad2f2db80844ba90eeb9b:
scripts/git.orderfile: Display MAINTAINERS changes first (2023-01-13
16:22:57 +0100
Since commit be8d853766 ("iothread: add I/O thread object") we
never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(),
remove these definitions.
Signed-off-by: Philippe Mathieu-Daudé
---
iothread.c | 4
1 file changed, 4 deletions(-)
diff --git a/iothread.c b/iothread.c
index
OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState
declaration for free. Besides, the QOM code style is to use
the structure name as typedef, and QEMU style is to use Camel
Case, so rename qemu_or_irq as OrIRQState.
Mechanical change using:
$ sed -i -e 's/qemu_or_irq/OrIRQState/g'
- remove unused code
- use recent QOM macros
- use CamelCase typedef
Philippe Mathieu-Daudé (4):
iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
hw:
QOM *DECLARE* macros expect a typedef as first argument,
not a structure. Replace 'struct IRQState' by 'IRQState'
to avoid when modifying the macros:
../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a
definition
DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ,
^
Use
Missed during automatic conversion from commit 8063396bf3
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/or-irq.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
index
Hi, Peter,
On 2023/1/12 下午11:13, Peter Xu wrote:
We wanted to capture outliers when you apply the follow up patch to vm load
procedure.
That will make depth>0 for the whole process of vm load during migration,
and we wanted to make sure it's safe, hence this patch, right?
In my perspective,
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