From: Philippe Mathieu-Daudé
The Goldfish interrupt controller is not target specific.
While the Exynos interrupt combiner is only used by the ARM
targets, we can build this device once for all.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221209170042.71169-3-phi...@linaro.org>
The following changes since commit a8d6abe1292e1db1ad9be5b2b124b9c01bcda094:
Merge tag 'mips-20230113' of https://github.com/philmd/qemu into staging
(2023-01-16 11:24:11 +)
are available in the Git repository at:
https://gitlab.com/laurent_vivier/qemu.git
From: Philippe Mathieu-Daudé
While only used by the ARM targets, this device can be built
once for all.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221209170042.71169-2-phi...@linaro.org>
Signed-off-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id:
From: Philippe Mathieu-Daudé
The TPM Physical Presence Interface is not target specific.
Build this file once for all targets.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221209170042.71169-4-phi...@linaro.org>
[thuth: Drop the CONFIG_SOFTMMU statements, they are not needed here]
From: Thomas Huth
Seems like there is nothing target-specific in here, so these files
can be moved to softmmu_ss to avoid that they get compiled twice
(once for qemu-system-arm and once for qemu-system-aarch64).
Signed-off-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id:
From: Philippe Mathieu-Daudé
This argument was added 9 years ago in commit 83d08f2673
("pc: map PCI address space as catchall region for not mapped
addresses") and has never been used since, so remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bernhard Beschow
Message-Id:
From: Marc-André Lureau
../hw/usb/ccid-card-emulated.c: In function 'handle_apdu_thread':
../hw/usb/ccid-card-emulated.c:251:24: error: cast from pointer to integer of
different size [-Werror=pointer-to-int-cast]
251 | assert((unsigned long)event > 1000);
Signed-off-by:
From: Philippe Mathieu-Daudé
arm_ss[] units are built twice: once for 32-bit word size and
once for 64-bit. The following units don't require any word
size knowledge and can be moved to softmmu_ss[] (where they
are built once):
- smmu-common.c
- exynos4_boards.c
- bcm2835_peripherals.c
-
From: Yuval Shaia
Guest driver might execute HW commands when shared buffers are not yet
allocated.
This could happen on purpose (malicious guest) or because of some other
guest/host address mapping error.
We need to protect againts such case.
Fixes: CVE-2022-1050
Reported-by: Raven
From: Michael Tokarev
Introduced by: aba578bdace5303a441f8a37aad781b5cb06f38c
Signed-off-by: Michael Tokarev
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221215123749.1026775-1-...@msgid.tls.msk.ru>
Signed-off-by: Laurent Vivier
---
hw/cxl/cxl-cdat.c | 2 +-
1 file changed, 1
From: Thomas Huth
Running the test-hmp with V=2 up to V=9 runs the test in verbose mode,
but running for example with V=10 falls back to non-verbose mode ...
Improve this oddity by properly treating the argument as a number.
Signed-off-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
From: Guoyi Tu
As qemu_socketpair() was introduced in commit 3c63b4e9
("oslib-posix: Introduce qemu_socketpair()"), it's time
to replace the other existing socketpair() calls with
qemu_socketpair() if possible
Signed-off-by: Guoyi Tu
Acked-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
From: Thomas Huth
Seems like there is nothing target-specific in here, so these files
can be moved to softmmu_ss to avoid that they get compiled twice
(once for qemu-system-arm and once for qemu-system-aarch64).
Signed-off-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id:
From: Thomas Huth
Seems like there is also nothing target-specific in here, so these
files can be moved to softmmu_ss to avoid that they get compiled
twice (once for qemu-system-arm and once for qemu-system-aarch64).
Signed-off-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id:
From: Michael Tokarev
Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0
Signed-off-by: Michael Tokarev
Reviewed-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Message-Id: <20221105115329.306527-1-...@msgid.tls.msk.ru>
Signed-off-by: Laurent Vivier
---
From: Hoa Nguyen
Signed-off-by: Hoa Nguyen
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221127032220.2649-1-hoangu...@ucdavis.edu>
Signed-off-by: Laurent Vivier
---
hw/cxl/cxl-host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-host.c
On 1/18/23 07:53, Joel Stanley wrote:
On Fri, 30 Dec 2022 at 11:35, Philippe Mathieu-Daudé wrote:
IEC binary prefixes ease code review: the unit is explicit.
I strongly prefer the existing code; it tells you the size without
having to do maths.
you mean that it matches better with the
On Jan 17 15:25, Philippe Mathieu-Daudé wrote:
> Hi Klaus,
>
> On 17/1/23 13:30, Klaus Jensen wrote:
> > Hi Philippe,
> >
> > Commit 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using
> > PCI_HOST_BRIDGE MemoryRegionOps") broke my mips64 nvme boot test
> > (little-endian host, mips64 and nvme
On 18/1/23 00:30, Mike Frysinger wrote:
Signed-off-by: Mike Frysinger
---
linux-user/strace.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 9ae5a812cd71..f7912ad67f2b 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -1380,6
On 18/1/23 01:32, BALATON Zoltan wrote:
Use the convention to return bool from functions which take an error
pointer which allows for callers to pass through their error pointer
without needing a local.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 62
On 18/1/23 01:32, BALATON Zoltan wrote:
Drop some local variables that could just be substituted at the single
place they were used. This makes the code shorter and simpler.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 13 +
1 file changed, 5 insertions(+), 8
On 18/1/23 01:32, BALATON Zoltan wrote:
Some functions use sysbus_dev while others sbd name for local variable
storing a sysbus device pointer. Standardise on the shorter name to be
consistent and make the code easier to read as short name is less
distracting and needs less line breaks.
On 18/1/23 01:32, BALATON Zoltan wrote:
At several places we already have the object pointer with the right
type so we don't need to cast it back and forth. Avoiding these casts
improves readability.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 14 +++---
1 file
As replay works well, the reverse debugging should be ok too.
But for "going back" it needs a VM snapshot that can be used for reload.
Snapshots are saved on qcow2 images connected to QEMU.
Therefore you need to add an empty qcow2 to your command line with the
following option: -drive
On Fri, 30 Dec 2022 at 11:35, Philippe Mathieu-Daudé wrote:
>
> IEC binary prefixes ease code review: the unit is explicit.
I strongly prefer the existing code; it tells you the size without
having to do maths.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Peter Delevoryas
> ---
>
Hello QEMU folks.
I was struggling to fix a recent heisenbug in the Linux kernel,
and fortunately the bug was reproducible with TCG and -smp 1.
I'm using qemu version 7.2.0, and guest architecture is i386.
I tried to inspect the bug using record/replay and reverse-debugging
feature in the QEMU.
On 17/01/23 4:22 pm, Claudio Fontana wrote:
Hi,
On 12/26/22 06:33, Het Gala wrote:
Current QAPI 'migrate' command design (for initiating a migration
stream) contains information regarding different migrate transport mechanism
(tcp / unix / exec), dest-host IP address, and binding port number
On 17/01/23 4:17 pm, Dr. David Alan Gilbert wrote:
* Het Gala (het.g...@nutanix.com) wrote:
From: Author Het Gala
Existing 'migrate' QAPI design enforces transport mechanism, ip address
of destination interface and corresponding port number in the form
of a unified string 'uri' parameter.
On 17/01/23 4:13 pm, Dr. David Alan Gilbert wrote:
* Daniel P. Berrangé (berra...@redhat.com) wrote:
On Mon, Dec 26, 2022 at 05:33:25AM +, Het Gala wrote:
From: Author Het Gala
Existing 'migrate' QAPI design enforces transport mechanism, ip address
of destination interface and
On Tue, 17 Jan 2023 19:15:57 -0500
Chuck Zmudzinski wrote:
> On 1/17/2023 6:04 AM, Igor Mammedov wrote:
> > On Mon, 16 Jan 2023 13:00:53 -0500
> > Chuck Zmudzinski wrote:
> >
> > > On 1/16/23 10:33, Igor Mammedov wrote:
> > > > On Fri, 13 Jan 2023 16:31:26 -0500
> > > > Chuck Zmudzinski
On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
> Hi all (linux-nvme, qemu-devel, maintainers),
>
> On QEMU riscv64, which does not use MSI/MSI-X and thus relies on
> pin-based interrupts, I'm seeing occasional completion timeouts, i.e.
>
> nvme nvme0: I/O 333 QID 1 timeout,
aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Joel Stanley
---
hw/arm/aspeed.c | 95 ++---
1 file changed, 43
This helper is useful in board initialization because lets users initialize and
realize an EEPROM on an I2C bus with a single function call.
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Reviewed-by: Joel Stanley
---
hw/arm/aspeed.c | 10 +-
Allows users to specify binary data to initialize an EEPROM, allowing users to
emulate data programmed at manufacturing time.
- Added init_rom and init_rom_size attributes to TYPE_AT24C_EE
- Added at24c_eeprom_init_rom helper function to initialize attributes
- If -drive property is provided, it
EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
I would expect the I2C state machine to be reset to default values, but I
wouldn't really expect the memory to change at all.
The current implementation of the at24c EEPROM resets its internal memory on
reset. This matches
- Create aspeed_eeprom.c and aspeed_eeprom.h
- Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
- Include aspeed_eeprom.h in aspeed.c
- Add fby35_bmc_fruid data
- Use new at24c_eeprom_init_rom helper to initialize BMC FRUID EEPROM with data
from aspeed_eeprom.c
wget
v1: https://lore.kernel.org/qemu-devel/20230114170151.87833-1-pe...@pjd.dev/
v2:
- Squashed 3 commits from original series into extract helper commit
- Dropped last 2 commits from original series
- Changed at24c_eeprom_init to return the I2CSlave object
- Added commit to introduce
在 2023/1/11 22:11, Markus Armbruster 写道:
huang...@chinatelecom.cn writes:
From: Hyman Huang(黄勇)
Implement dirty-limit convergence algo for live migration,
which is kind of like auto-converge algo but using dirty-limit
instead of cpu throttle to make migration convergent.
Enable dirty
在 2023/1/11 22:38, Markus Armbruster 写道:
huang...@chinatelecom.cn writes:
From: Hyman Huang(黄勇)
Export dirty limit throttle time and estimated ring full
time, through which we can observe if dirty limit take
effect during live migration.
Suggest something like "Extend query-migrate to
On Wed, Jan 18, 2023 at 02:22:01AM +, Joel Stanley wrote:
> On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
> >
> > Allows users to specify binary data to initialize an EEPROM, allowing users
> > to
> > emulate data programmed at manufacturing time.
>
> I like it. Is there somewhere
On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
>
> EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
> I would expect the I2C state machine to be reset to default values, but I
> wouldn't really expect the memory to change at all.
>
> The current implementation of
On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
>
> - Create aspeed_eeprom.c and aspeed_eeprom.h
> - Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
> - Include aspeed_eeprom.h in aspeed.c
> - Add fby35_bmc_fruid data
> - Use new at24c_eeprom_init_rom helper to initialize BMC
On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
>
> Allows users to specify binary data to initialize an EEPROM, allowing users to
> emulate data programmed at manufacturing time.
I like it. Is there somewhere sensible to add a description to the
code base? Perhaps as a comment to your new
On 1/16/23 22:24, Philippe Mathieu-Daudé wrote:
On 13/1/23 08:05, Philippe Mathieu-Daudé wrote:
On 13/1/23 02:05, Richard Henderson wrote:
On 1/11/23 08:31, Philippe Mathieu-Daudé wrote:
Implement Richard's suggestion to use __builtin_bswap().
Convert to __builtin_bswap() one patch per OS to
On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
>
> This helper is useful in board initialization because lets users initialize
> and
> realize an EEPROM on an I2C bus with a single function call.
>
> Signed-off-by: Peter Delevoryas
> Reviewed-by: Cédric Le Goater
Reviewed-by: Joel
On Tue, 17 Jan 2023 at 23:24, Peter Delevoryas wrote:
>
> aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.
>
> Signed-off-by: Peter Delevoryas
> Reviewed-by: Cédric Le Goater
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Joel Stanley
> ---
> hw/arm/aspeed.c | 95
Adjust the constraints to allow any int32_t for immediate
addition. Split immediate adds into addu16i + addi, which
covers quite a lot of the immediate space. For the hole in
the middle, load the constant into TMP0 instead.
Signed-off-by: Richard Henderson
---
While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.
Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.
Print both the raw field and the resolved pc-relative
address, as we do for branches.
Signed-off-by: Richard Henderson
---
target/loongarch/disas.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/disas.c
Split out a helper function, tcg_out_setcond_int, which
does not always produce the complete boolean result, but
returns a set of flags to do so.
Accept all int32_t as constant input, so that LE/GT can
adjust the constant to LT.
Signed-off-by: Richard Henderson
---
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc
Based-on: 20230117231051.35-1-richard.hender...@linaro.org
("[PULL 00/22] tcg patch queue")
Includes:
* Disassembler from target/loongarch/.
* Improvements to movi by Rui Wang, with minor tweaks.
* Improvements to setcond.
* Implement movcond.
* Fix the same goto_tb bug that
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.h | 4 ++--
tcg/loongarch64/tcg-target.c.inc | 33
3 files changed, 36 insertions(+), 2 deletions(-)
diff --git
Regenerate with ADDU16I included:
$ cd loongarch-opcodes/scripts/go
$ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
mode change
The old implementation replaces two insns, swapping between
b
nop
and
pcaddu18i tmp,
jirl zero, tmp, & 0x
There is a race condition in which a thread could be stopped at
the jirl, i.e. with the top of the address loaded, and when
restarted we
From: Rui Wang
diff:
Imm Before After
addi.w rd, zero, 0 addi.w rd, zero, 0
lu52i.d rd, zero, 0
f800lu12i.w rd, -1 addi.w rd, zero, -2048
ori rd, rd, 2048
Reuse the decodetree based disassembler from
target/loongarch/ for tcg/loongarch64/.
The generation of decode-insns.c.inc into ./libcommon.fa.p/ could
eventually result in conflict, if any other host requires the same
trick, but this is good enough for now.
Signed-off-by: Richard Henderson
---
Some functions use sysbus_dev while others sbd name for local variable
storing a sysbus device pointer. Standardise on the shorter name to be
consistent and make the code easier to read as short name is less
distracting and needs less line breaks.
Signed-off-by: BALATON Zoltan
---
Drop some local variables that could just be substituted at the single
place they were used. This makes the code shorter and simpler.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/misc/macio/macio.c
Just some small trivial clean ups that I've found while looking at
hw/misc/macio/macio.c
Regards,
BALATON Zoltan
BALATON Zoltan (4):
hw/misc/macio: Avoid some QOM casts
hw/misc/macio: Rename sysbus_dev to sbd for consistency and brevity
hw/misc/macio: Remove some single use local variables
At several places we already have the object pointer with the right
type so we don't need to cast it back and forth. Avoiding these casts
improves readability.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff
Use the convention to return bool from functions which take an error
pointer which allows for callers to pass through their error pointer
without needing a local.
Signed-off-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 62 +--
1 file changed, 25
On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote:
>
> On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done in
> > csr.c:validate_vm).
On Wed, Jan 18, 2023 at 9:05 AM Richard Henderson
wrote:
>
> We failed to update this with the w^x split, so misses the fact
> that true pc-relative offsets are usually small.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 2
On 1/17/2023 6:04 AM, Igor Mammedov wrote:
> On Mon, 16 Jan 2023 13:00:53 -0500
> Chuck Zmudzinski wrote:
>
> > On 1/16/23 10:33, Igor Mammedov wrote:
> > > On Fri, 13 Jan 2023 16:31:26 -0500
> > > Chuck Zmudzinski wrote:
> > >
> > >> On 1/13/23 4:33 AM, Igor Mammedov wrote:
> > >> > On
We should not quote the PKG_CONFIG setting as this deviates from the
canonical upstream behavior that gets integrated with all other build
systems, and deviates from how we treat all other toolchain variables
that we get from the environment.
Ultimately, the point is that it breaks passing custom
Signed-off-by: Mike Frysinger
---
linux-user/strace.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 9ae5a812cd71..f7912ad67f2b 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -1380,6 +1380,7 @@ UNUSED static struct flags
aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed.c | 95 ++---
1 file changed, 43 insertions(+), 52 deletions(-)
- Create aspeed_eeprom.c and aspeed_eeprom.h
- Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
- Include aspeed_eeprom.h in aspeed.c
- Add fby35_bmc_fruid data
- Use new at24c_eeprom_init_rom helper to initialize BMC FRUID EEPROM with data
from aspeed_eeprom.c
wget
EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
I would expect the I2C state machine to be reset to default values, but I
wouldn't really expect the memory to change at all.
The current implementation of the at24c EEPROM resets its internal memory on
reset. This matches
Allows users to specify binary data to initialize an EEPROM, allowing users to
emulate data programmed at manufacturing time.
- Added init_rom and init_rom_size attributes to TYPE_AT24C_EE
- Added at24c_eeprom_init_rom helper function to initialize attributes
- If -drive property is provided, it
v1: https://lore.kernel.org/qemu-devel/20230114170151.87833-1-pe...@pjd.dev/
v2:
- Squashed 3 commits from original series into extract helper commit
- Dropped last 2 commits from original series
- Changed at24c_eeprom_init to return the I2CSlave object
- Added commit to introduce
This helper is useful in board initialization because lets users initialize and
realize an EEPROM on an I2C bus with a single function call.
Signed-off-by: Peter Delevoryas
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 +-
hw/arm/npcm7xx_boards.c | 20
The old sparc64 implementation may replace two insns, which leaves
a race condition in which a thread could be stopped at a PC in the
middle of the sequence, and when restarted does not see the complete
address computation and branches to nowhere.
The new implemetation replaces only one insn,
This can replace four other variables that are references
into the TranslationBlock structure.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 11 +++
accel/tcg/translate-all.c | 2 +-
tcg/tcg-op.c | 14 +++---
tcg/tcg.c
Similar to the existing set_jmp_reset_offset. Move any assert for
TCG_TARGET_HAS_direct_jump into the new function (which now cannot
be build-time). Will be unused if TCG_TARGET_HAS_direct_jump is
constant 0, but we can't test for constant in the preprocessor,
so just mark it G_GNUC_UNUSED.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 3 +++
tcg/aarch64/tcg-target.h | 4
tcg/arm/tcg-target.h | 5 -
tcg/i386/tcg-target.h| 3 ---
tcg/loongarch64/tcg-target.h | 3 ---
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 41 +++-
1 file changed, 12 insertions(+), 29 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index d2d8b46815..26b00d1638 100644
Test TCG_TARGET_HAS_direct_jump instead of testing an
implementation pointer.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/loongarch64/tcg-target.c.inc |
The INDEX_op_exit_tb opcode needs no register allocation.
Split out a dedicated helper function for it.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc | 22
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 32 +---
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index a95e4001d3..b72e266990 100644
---
Stop overloading jmp_target_arg for both offset and address,
depending on TCG_TARGET_HAS_direct_jump. Instead, add a new
field to hold the jump insn offset and always set the target
address in jmp_target_addr[]. This will allow a tcg backend
to use either direct or indirect depending on
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 136fe54d4b..82ca86431e 100644
---
This will shortly be used for more than reset.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 2 +-
accel/tcg/translate-all.c | 8
tcg/tcg.c | 4 ++--
3 files changed, 7 insertions(+), 7
We now have the option to generate direct or indirect
goto_tb depending on the dynamic displacement, thus
the define is no longer necessary or completely accurate.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h |
Now that tcg can handle direct and indirect goto_tb simultaneously,
we can optimistically leave space for a direct branch and fall back
to loading the pointer from the TB for an indirect branch.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 19
The old implementation replaces two insns, swapping between
b
nop
br x30
and
adrpx30,
addix30, x30, lo12:
br x30
There is a race condition in which a thread could be stopped at
the PC of the second insn, and when restarted
This is always true for sparc64, so this is dead since 3a5f6805c7ca.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 62
1 file changed, 21 insertions(+), 41 deletions(-)
Replace 'tc_ptr' and 'addr' with 'tb' and 'n'.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 3 ++-
tcg/arm/tcg-target.h | 3 ++-
tcg/i386/tcg-target.h| 9 ++---
tcg/loongarch64/tcg-target.h | 3 ++-
The old ppc64 implementation replaces 2 or 4 insns, which leaves a race
condition in which a thread could be stopped at a PC in the middle of
the sequence, and when restarted does not see the complete address
computation and branches to nowhere.
The new implemetation replaces only one insn,
repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230117
for you to fetch changes up to 493c9b19a7fb7f387c4fcf57d3836504d5242bf5:
tcg/riscv: Implement direct branch for goto_tb (2023-01-17 22:36:17 +)
tcg: Fix race
Now that tcg can handle direct and indirect goto_tb
simultaneously, we can optimistically leave space for
a direct branch and fall back to loading the pointer
from the TB for an indirect branch.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 52
The INDEX_op_goto_tb opcode needs no register allocation.
Split out a dedicated helper function for it.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4 ++
tcg/aarch64/tcg-target.c.inc | 40
Install empty versions for !TCG_TARGET_HAS_direct_jump hosts.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 6 ++
tcg/mips/tcg-target.c.inc | 6 ++
tcg/riscv/tcg-target.c.inc | 6 ++
Similar to the existing set_jmp_reset_offset. Include the
rw->rx address space conversion done by arm and s390x, and
forgotten by mips and riscv.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 9 +
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index feb257db01..c4ff59e9ee 100644
--- a/tcg/i386/tcg-target.c.inc
We failed to update this with the w^x split, so misses the fact
that true pc-relative offsets are usually small.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc
Am 4. Januar 2023 14:44:31 UTC schrieb Bernhard Beschow :
>This series first renders TYPE_PIIX3_XEN_DEVICE redundant and finally removes
>
>it. The motivation is to 1/ decouple PIIX from Xen and 2/ to make Xen in the PC
>
>machine agnostic to the precise southbridge being used. 2/ will become
>
On 1/17/23 1:42 PM, Richard Henderson wrote:
> Is there a reason why these are separate from m_systemreg?
GDB puts these in a separate file, and J-Link puts them in a separate feature
block.
In general, I think it's nice to separate stuff related to the secure extension
so folks not working with
On 1/17/23 1:40 PM, Richard Henderson wrote:
>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
>> index bf2bce046d..fdbb0d9107 100644
>> --- a/target/arm/cpu.h
>> +++ b/target/arm/cpu.h
>> @@ -856,6 +856,7 @@ struct ArchCPU {
>> DynamicGDBXMLInfo dyn_sysreg_xml;
>>
1 - 100 of 397 matches
Mail list logo
