On Fri, Jan 06, 2023 at 12:38:21AM -0800, Lei Wang wrote:
> CPUID leaf 0x1D and 0x1E enumerate tile and TMUL information for AMX.
>
> Introduce FeatureWord FEAT_1D_1_EAX, FEAT_1D_1_EBX, FEAT_1D_1_ECX and
> FEAT_1E_0_EBX. Thus these features of AMX can be expanded when
> "-cpu host/max" and can be
On 03/02/2023 22.14, Juan Quintela wrote:
Peter Maydell wrote:
On Fri, 3 Feb 2023 at 15:44, Thomas Huth wrote:
On 03/02/2023 13.08, Kevin Wolf wrote:
Am 03.02.2023 um 12:23 hat Thomas Huth geschrieben:
On 30/01/2023 11.58, Daniel P. Berrangé wrote:
On Mon, Jan 30, 2023 at 11:44:46AM
On Fri, Jan 06, 2023 at 12:38:24AM -0800, Lei Wang wrote:
> Some feature words, e.g., feature words in AMX-related CPUID leaf 0x1D and
> 0x1E are not bit-wise but multiple bits represents one value. Handle this
> situation when the values specified are not the same as which are reported
> by KVM.
+s390x/block lists
On 5/2/23 20:10, Michael Tokarev wrote:
There's a bug filed against qemu on debian, about qemu-img hanging on
s390x.
While digging in, I discovered that the thing is broken there indeed,
and it
is broken for a very long time, and it is interesting.
The reproducer is rather
Hi
On Wed, Jan 25, 2023 at 9:28 PM Steve Sistare
wrote:
> When qemu-keymap is not available on the host, and enable-xkbcommon
> is specified, parallel make fails with:
>
> % make clean
> ...
> % make -j 32
> ...
> FAILED: pc-bios/keymaps/is
> ./qemu-keymap -f pc-bios/keymaps/is -l
On 5/2/23 23:32, Mark Cave-Ayland wrote:
On 05/02/2023 22:21, BALATON Zoltan wrote:
On Sun, 5 Feb 2023, Mark Cave-Ayland wrote:
On 26/01/2023 21:17, Bernhard Beschow wrote:
Internal instances now defer interrupt wiring to the caller which
decouples them from the ISABus. User-created devices
Hi
On Sun, Jan 29, 2023 at 10:25 PM wrote:
>
> From: Marc-André Lureau
>
> Hi,
>
> The following series first fixes a few tests on win32. The second part focuses
> on 'add_client' support, by limiting its scope to sockets and adding win32
> support. Finally, it enables vnc-display test on
On Thu, Feb 2, 2023 at 12:54 PM Sunil V L wrote:
>
> ACPI needs OEM_ID and OEM_TABLE_ID for the machine. Add these fields
> in the RISCVVirtState structure and initialize with default values.
>
> Signed-off-by: Sunil V L
> ---
> hw/riscv/virt.c | 4
> include/hw/riscv/virt.h | 2 ++
> -Original Message-
> From: Christian Schoenebeck
> Sent: Saturday, February 4, 2023 01:55
> To: Greg Kurz ; qemu-devel@nongnu.org
> Cc: Meng, Bin ; Marc-André Lureau
> ; Daniel P. Berrangé
> ; Shi, Guohuai
> Subject: Re: [PATCH v4 04/16] hw/9pfs: Implement Windows specific xxxdir()
On 2/5/2023 2:00 AM, Michael S. Tsirkin wrote:
On Sat, Feb 04, 2023 at 03:04:02AM -0800, Si-Wei Liu wrote:
For network hardware device, I thought suspend
just needs to wait until the completion of ongoing Tx/Rx DMA transaction
already in the flight, rather than to drain all the upcoming
Hi, Peter,
IMHO that one will be more straightforward and self contained than this
one. What do you think?
Yes, it is.
When posting new patches, please also remember to copy maintainers. For
this one, it's:
Thanks for your suggestion.
Weinan Liu
For async tx, virtio_net_tx_complete() is called when purge or flush
operation is done. But for purge operation, we should not try to flush
new packet from tx queue. The purge operation means we will stop the
queue soon.
Signed-off-by: Xuan Zhuo
---
hw/net/virtio-net.c | 32
In the current design, we stop the device from operating on the vring
during per-queue reset by resetting the structure VirtQueue.
But before the reset operation, when recycling some resources, we should
stop referencing new vring resources.
This bug is caused by this reason.
When dev/queue reset, we should just purge all packet, not try to flush
the async packets. When flush these async packets, the
callback(virtio_net_tx_complete) will try to flush new packets from tx
queue.
Fixes: 7dc6be52 ("virtio-net: support queue reset")
Fixes:
> 2023年2月5日 11:48，Philippe Mathieu-Daudé 写道：
>
> Hi Jiaxun,
>
> On 2/2/23 14:21, Jiaxun Yang wrote:
>> MIPS virt board is design to utilize existing VirtIO infrastures
>> but also comptitable with MIPS's existing internal simulation tools.
>> It includes virtio-mmio, pcie gpex, flash rom,
Hi Michael
Please correct me if I miss anything...
On 1/29/23 10:57, zhenwei pi wrote:
v4 -> v5:
- suggested by MST, use 'PRIu32' instead of '%u' to print a uint32_t value
- correct *QCryptodevBackendClient* and *QCryptodevInfo* in qapi/cryptodev.json
v3 -> v4:
- a small change in
Am 5. Februar 2023 21:37:01 UTC schrieb Mark Cave-Ayland
:
>On 26/01/2023 21:17, Bernhard Beschow wrote:
>
>> Signed-off-by: Bernhard Beschow
>> ---
>> include/exec/ioport.h | 2 --
>> softmmu/ioport.c | 24
>> 2 files changed, 26 deletions(-)
>>
>> diff
Am 5. Februar 2023 11:12:26 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 4/2/23 16:10, Bernhard Beschow wrote:
>> sysbus_add_io() just wraps memory_region_add_subregion() while also
>> obscuring where the memory is attached. So use
>> memory_region_add_subregion() directly and attach it to the
Am 4. Februar 2023 15:26:13 UTC schrieb BALATON Zoltan :
>On Sat, 4 Feb 2023, Bernhard Beschow wrote:
>> Going through pc_memory_init() seems quite complicated for a simple
>> assignment.
>>
>> Signed-off-by: Bernhard Beschow
>> Reviewed-by: Philippe Mathieu-Daudé
>> ---
>>
On Sat, Feb 4, 2023 at 12:03 AM Vladimir Isaev
wrote:
>
> Character must be returned via ret[0] field (copied to a0 by KVM).
>
> Return value should be set to 0 to indicate successful processing.
>
> Signed-off-by: Vladimir Isaev
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
On Sat, Feb 4, 2023 at 6:25 PM Vladimir Isaev
wrote:
>
> According to spec, ctzw should work with 32-bit register, not 64.
>
> For example, previous implementation returns 33 for (1<<33) input
> when the new one returns 32.
>
> Signed-off-by: Vladimir Isaev
> Suggested-by: Richard Henderson
On Sat, Jan 28, 2023 at 6:36 AM Deepak Gupta wrote:
>
> commit fb3f3730e4 added mechanism to generate virtual instruction
> exception during instruction decode when virt is enabled.
>
> However in some situations, illegal instruction exception can be raised
> due to state of CPU. One such
On 02/02/2023 00:24, BALATON Zoltan wrote:
Same as v1 just split in two patches as suggested by Mark.
Regards,
BALATON Zoltan
BALATON Zoltan (2):
mac_nvram: Add block backend to persist NVRAM contents
mac_oldworld: Allow specifying nvram backing store
hw/nvram/mac_nvram.c |
On 03/02/2023 11:36, Philippe Mathieu-Daudé wrote:
These patches are extracted from a QOM/QDev refactor series,
so they are preliminary cleanups noticed while working on it:
- Use correct type when calling qdev_prop_set_xxx()
- Unify some qdev properties in MIPS models
- Replace intermediate
On 02/02/2023 00:51, Richard Henderson wrote:
Lots of missing trap code for cpu_loop().
r~
Richard Henderson (14):
linux-user/sparc: Raise SIGILL for all unhandled software traps
linux-user/sparc: Tidy syscall trap
linux-user/sparc: Use TT_TRAP for flush windows
linux-user/sparc:
On Sat, Jan 28, 2023 at 6:36 AM Deepak Gupta wrote:
>
> commit fb3f3730e4 added mechanism to generate virtual instruction
> exception during instruction decode when virt is enabled.
>
> However in some situations, illegal instruction exception can be raised
> due to state of CPU. One such
On Wed, Feb 1, 2023 at 6:21 AM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This patch adds support for the XTheadCmo ISA extension.
> To avoid interfering with standard extensions, decoder and translation
> are in its own xthead* specific files.
> Future patches should be able to
On Sat, Feb 4, 2023 at 12:03 AM Vladimir Isaev
wrote:
>
> Character must be returned via ret[0] field (copied to a0 by KVM).
>
> Return value should be set to 0 to indicate successful processing.
>
> Signed-off-by: Vladimir Isaev
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Sat, Feb 4, 2023 at 6:25 PM Vladimir Isaev
wrote:
>
> According to spec, ctzw should work with 32-bit register, not 64.
>
> For example, previous implementation returns 33 for (1<<33) input
> when the new one returns 32.
>
> Signed-off-by: Vladimir Isaev
> Suggested-by: Richard Henderson
On Fri, Feb 3, 2023 at 4:04 PM Alexandre Ghiti wrote:
>
> Currently, the max satp mode is set with the only constraint that it must be
> implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable of,
Ping
On Tue, Sep 27, 2022 at 11:46:53AM -0400, Peter Xu wrote:
> It's possible that we want to reap a dirty ring on a vcpu that is during
> creation, because the vcpu is put onto list (CPU_FOREACH visible) before
> initialization of the structures. In this case:
>
> qemu_init_vcpu
>
Hi, Weinan,
On Sun, Feb 05, 2023 at 06:45:45AM +, Weinan Liu wrote:
> Failed to assert '(dirty_gfns && ring_size)' in kvm_dirty_ring_reap_one if
> the vcpu has not been finished to create yet. This bug occasionally occurs
> when I open 200+ qemu instances on my 16G 6-cores x86 machine. And it
On 03/02/2023 18:08, Philippe Mathieu-Daudé wrote:
Introduce qdev_prop_set_link(), equivalent of
object_property_set_link() for QDev objects.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/qdev-properties.c| 5 +
include/hw/qdev-properties.h | 1 +
2 files changed, 6
On 05/02/2023 22:21, BALATON Zoltan wrote:
On Sun, 5 Feb 2023, Mark Cave-Ayland wrote:
On 26/01/2023 21:17, Bernhard Beschow wrote:
Internal instances now defer interrupt wiring to the caller which
decouples them from the ISABus. User-created devices still fish out the
ISABus from the QOM
On Sun, 5 Feb 2023, Mark Cave-Ayland wrote:
On 26/01/2023 21:17, Bernhard Beschow wrote:
Internal instances now defer interrupt wiring to the caller which
decouples them from the ISABus. User-created devices still fish out the
ISABus from the QOM tree and the interrupt wiring remains in PIIX
On 30/01/2023 20:45, Alex Bennée wrote:
Daniel P. Berrangé writes:
On Mon, Jan 30, 2023 at 11:47:02AM +, Peter Maydell wrote:
On Mon, 30 Jan 2023 at 11:44, Thomas Huth wrote:
Testing 32-bit host OS support takes a lot of precious time during the QEMU
contiguous integration tests, and
On 26/01/2023 21:17, Bernhard Beschow wrote:
Both callers to ide_init_ioport() have access to the I/O memory region
of the ISA bus, so can pass it directly. This allows ide_init_ioport()
to directly call portio_list_init().
Note, now the callers become the owner of the PortioList.
On 26/01/2023 21:17, Bernhard Beschow wrote:
Internal instances now defer interrupt wiring to the caller which
decouples them from the ISABus. User-created devices still fish out the
ISABus from the QOM tree and the interrupt wiring remains in PIIX IDE.
The latter mechanism is considered a
On 26/01/2023 21:17, Bernhard Beschow wrote:
isa_get_irq() asks for an ISADevice which piix-ide doesn't provide.
Passing a NULL pointer works but causes the isabus global to be used
then. By fishing out TYPE_ISA_BUS from the QOM tree it is possible to
achieve the same as isa_get_irq().
This is
On 26/01/2023 21:17, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
include/exec/ioport.h | 2 --
softmmu/ioport.c | 24
2 files changed, 26 deletions(-)
diff --git a/include/exec/ioport.h b/include/exec/ioport.h
index ec3e8e5942..1ef5aebba3
On 26/01/2023 21:17, Bernhard Beschow wrote:
Both functions are always used together and in the same order. Let's
reflect this in the API.
Inspired-by: <20210518215545.1793947-9-phi...@redhat.com>
'hw/isa: Extract bus part from isa_register_portio_list()'
Signed-off-by: Bernhard
On 2/5/23 08:44, BALATON Zoltan wrote:
On Sun, 5 Feb 2023, Richard Henderson wrote:
On 2/4/23 06:57, BALATON Zoltan wrote:
This has just bounced, I hoped to still be able to post after moderation but now I'm
resending it after subscribing to the pixman list. Meanwhile I've found this ticket as
There's a bug filed against qemu on debian, about qemu-img hanging on s390x.
While digging in, I discovered that the thing is broken there indeed, and it
is broken for a very long time, and it is interesting.
The reproducer is rather simple:
qemu-img create -f qcow2 -o preallocation=metadata
On Sun, 5 Feb 2023, Richard Henderson wrote:
On 2/4/23 06:57, BALATON Zoltan wrote:
This has just bounced, I hoped to still be able to post after moderation
but now I'm resending it after subscribing to the pixman list. Meanwhile
I've found this ticket as well:
On 2/4/23 06:57, BALATON Zoltan wrote:
This has just bounced, I hoped to still be able to post after moderation but now I'm
resending it after subscribing to the pixman list. Meanwhile I've found this ticket as
well: https://gitlab.freedesktop.org/pixman/pixman/-/merge_requests/71
See the rest
On Sat, 4 Feb 2023 at 16:33, Richard Henderson
wrote:
>
> The following changes since commit 579510e196a544b42bd8bca9cc61688d4d1211ac:
>
> Merge tag 'pull-monitor-2023-02-03-v2' of https://repo.or.cz/qemu/armbru
> into staging (2023-02-04 10:19:55 +)
>
> are available in the Git repository
On Mon, Jan 30, 2023 at 09:09:47 -1000, Richard Henderson wrote:
> On 1/29/23 23:27, Daniel P. Berrangé wrote:
> > On Sun, Jan 29, 2023 at 05:38:08PM -0500, Emilio Cota wrote:
> > > Since this is a correctness issue, I think we should ship with qtree
> > > and use it when configuring with glib
The only reason to add this implementation is to control the memory allocator
used. Some users (e.g. TCG) cannot work reliably in multi-threaded
environments (e.g. forking in user-mode) with GTree's allocator, GSlice.
See https://gitlab.com/qemu-project/qemu/-/issues/285 for details.
Importing
Changes since v1:
- Add configure check to only use QTree if Glib still implements gslice.
If Glib doesn't, then we call Glib directly with inline functions.
- Add TODO's so that in the future (i.e. when the minimum version of
Glib that we use doesn't implement gslice) we remove QTree.
- Add
qemu-user can hang in a multi-threaded fork. One common
reason is that when creating a TB, between fork and exec
we manipulate a GTree whose memory allocator (GSlice) is
not fork-safe.
Although POSIX does not mandate it, the system's allocator
(e.g. tcmalloc, libc malloc) is probably fork-safe.
Hello,
After installing Qemu on Win, I don't see any shortcut to run it? There is
only a link to 'uninstall'. launching exe files doesn't do anything. Can
you please explain how to launch this application?
Thanks,
J.
Please see the attached image.
On Sun, 5 Feb 2023 at 03:15, Eugenio Perez Martin wrote:
>
> On Fri, Jan 27, 2023 at 4:18 PM Stefan Hajnoczi wrote:
> >
> > Dear QEMU, KVM, and rust-vmm communities,
> > QEMU will apply for Google Summer of Code 2023
> > (https://summerofcode.withgoogle.com/) and has been accepted into
> >
On Sat, 4 Feb 2023 at 20:09, Laurent Vivier wrote:
>
> On 2/4/23 15:57, Peter Maydell wrote:
> > On Thu, 2 Feb 2023 at 06:21, Jason Wang wrote:
> >>
> >> The following changes since commit
> >> 13356edb87506c148b163b8c7eb0695647d00c2a:
> >>
> >>Merge tag 'block-pull-request' of
Hi Jiaxun,
On 2/2/23 14:21, Jiaxun Yang wrote:
MIPS virt board is design to utilize existing VirtIO infrastures
but also comptitable with MIPS's existing internal simulation tools.
It includes virtio-mmio, pcie gpex, flash rom, fw_cfg, goldfish-rtc,
and optional goldfish_pic in case MIPS GIC
On 2/2/23 14:21, Jiaxun Yang wrote:
This board had been deprecated long ago.
s/deprecated/removed/
Indeed, in commit f169413c27 ("hw/mips: Remove the 'r4k' machine").
Signed-off-by: Jiaxun Yang
---
docs/system/target-mips.rst | 14 --
1 file changed, 14 deletions(-)
On 4/2/23 16:10, Bernhard Beschow wrote:
When setting up the CPU's smram memory region alias, the code currently
assumes that the smram size is 4 GiB. While this is true, it repeats a
decision made elsewhere which seems redundant and prone to
inconsistencies. Avoid this by reusing whatever size
On 4/2/23 16:10, Bernhard Beschow wrote:
Treat the smram MemoryRegion analoguous to other memory regions such as
ram, pci, io, ... , making the used memory regions more explicit when
instantiating q35 or i440fx.
Note that the q35 device uses these memory regions only during the
realize phase
On 4/2/23 16:10, Bernhard Beschow wrote:
Unlike pam_update() which takes the subject -- PAMMemoryRegion -- as
first argument, init_pam() takes it as fifth (!) argument. This makes it
quite hard to figure out what an init_pam() invocation actually
initializes. By moving the subject to the front
On 4/2/23 16:10, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
Reviewed-by: Thomas Huth
---
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 4/2/23 16:10, Bernhard Beschow wrote:
sysbus_add_io() just wraps memory_region_add_subregion() while also
obscuring where the memory is attached. So use
memory_region_add_subregion() directly and attach it to the existing
memory region s->mch.address_space_io which is set as an alias to
On 4/2/23 16:10, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
Reviewed-by: Thomas Huth
---
hw/i386/pc_q35.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/3/23 18:16, Philippe Mathieu-Daudé wrote:
part 1 [*] cover:
--
QEMU provides the QOM API for core objects.
Devices are modelled on top of QOM as QDev objects.
There is no point in using the lower level QOM API with
QDev; it makes the code more complex and harder to review.
I first
On 4/2/23 16:10, Bernhard Beschow wrote:
sysbus_add_io() just wraps memory_region_add_subregion() while also
obscuring where the memory is attached. So use
memory_region_add_subregion() directly and attach it to the existing
memory region s->bus->address_space_io which is set as an alias to
On 2/3/23 18:16, Philippe Mathieu-Daudé wrote:
No need to use the low-level QOM API when an object
inherits from QDev. Directly use the QDev API to set
its properties.
All calls use either errp=_fatal or NULL, so
converting to the QDev API is almost a no-op (QDev API
always uses _abort).
On 2/3/23 18:16, Philippe Mathieu-Daudé wrote:
No need to use the low-level QOM API when an object
inherits from QDev. Directly use the QDev API to set
its properties.
One call in pnv_psi_power8_realize() propagate the
Error* argument:
if (!object_property_set_int(OBJECT(ics), "nr-irqs",
On 2/3/23 18:16, Philippe Mathieu-Daudé wrote:
No need to use the low-level QOM API when an object
inherits from QDev. Directly use the QDev API to set
its properties.
All calls use either errp=_abort or _fatal,
so converting to the QDev API is almost a no-op (QDev
API always uses _abort).
On 2/3/23 18:16, Philippe Mathieu-Daudé wrote:
No need to use the low-level QOM API when an object
inherits from QDev. Directly use the QDev API to set
its properties.
All calls use either errp=_abort or _fatal,
so converting to the QDev API is almost a no-op (QDev
API always uses _abort).
On 4/2/23 18:47, Vladimir Sementsov-Ogievskiy wrote:
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/pci/pcie.c | 20
hw/pci/trace-events | 3 +++
2 files changed, 23 insertions(+)
+static const char *pcie_sltctl_pic_str(uint16_t sltctl)
+{
+switch
On 4/2/23 18:47, Vladimir Sementsov-Ogievskiy wrote:
PCI_EXP_SLTCTL_PIC_OFF is a value, and PCI_EXP_SLTCTL_PIC is a mask.
Happily PCI_EXP_SLTCTL_PIC_OFF is a maximum value for this mask and is
equal to the mask itself. Still the code looks like a bug. Let's make
it more reader-friendly.
On 4/2/23 18:47, Vladimir Sementsov-Ogievskiy wrote:
We already have indicator values in
include/standard-headers/linux/pci_regs.h , no reason to reinvent them
in include/hw/pci/pcie_regs.h. (and we already have usage of
PCI_EXP_SLTCTL_PWR_IND_BLINK and PCI_EXP_SLTCTL_PWR_IND_OFF in
On 5/2/23 05:29, Alexander Bulekov wrote:
As we are converting most fuzzers to rely on reboots to reset state,
introduce an API to make sure reboots are invoked in a consistent
manner.
Signed-off-by: Alexander Bulekov
---
tests/qtest/fuzz/fuzz.c | 6 ++
tests/qtest/fuzz/fuzz.h | 2 +-
On 5/2/23 05:29, Alexander Bulekov wrote:
As we have repplaced fork-based fuzzing, with reboots - we can no longer
Typo "replaced".
use a timeout+exit() to avoid slow inputs. Libfuzzer has its own timer
that it uses to catch slow inputs, however these timeouts are usually
seconds-minutes
On 5/2/23 05:29, Alexander Bulekov wrote:
We use sparse-mem for fuzzing. For long-running fuzzing processes, we
eventually end up with many allocated sparse-mem pages. To avoid this,
clear the allocated pages on system-reset.
Signed-off-by: Alexander Bulekov
---
hw/mem/sparse-mem.c | 13
On 5/2/23 05:29, Alexander Bulekov wrote:
* Some device do not completely reset their state. This can lead to
non-reproducible crashes. However, in my local tests, most crashes
were reproducible. OSS-Fuzz shouldn't send us reports unless it can
consistently reproduce a crash.
From: Murilo Opsfelder Araujo
Add support for ppc64le for guestperf.py. On ppc, console is usually
hvc0 and serial device for pseries machine is spapr-vty.
Signed-off-by: Murilo Opsfelder Araujo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Juan Quintela
Message-Id:
From: Bernhard Beschow
This is a follow-up on commit 47a0b1dff7e9 'hw/ppc/mpc8544ds: Add
platform bus': Both mpc85xx boards now have a platform bus
unconditionally.
Signed-off-by: Bernhard Beschow
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230125130024.158721-3-shen...@gmail.com>
From: BALATON Zoltan
Reported-by: Stefan Weil
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230203194312.33834745...@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pegasos2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Bernhard Beschow
Makes the unimplemented region move together with the CCSR address space
if moved by a bootloader. Moving the CCSR address space isn't
implemented yet but this patch is a preparation for it.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Frederic Barrat
PNV_PHB5_DEVICE_ID is defined in two different headers. The definition
in hw/pci-host/pnv_phb4.h was left out in a previous rework.
Remaining definition is in hw/pci-host/pnv_phb.h.
Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Message-Id:
From: BALATON Zoltan
No need to wrap constants in parenthesis.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
<9194546b73b05e7098761ec62b2dfd0699b97b65.1674333199.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/display/sm501.c | 394
From: Bernhard Beschow
This enables support for the 'dumpdtb' QMP/HMP command for all
e500 machines.
Signed-off-by: Bernhard Beschow
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230125130024.158721-2-shen...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/e500.c | 7
From: BALATON Zoltan
This is not needed in C.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
<58f599387dd0739ea1880bfb678872c0be26bf1b.1674333199.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/display/sm501.c | 22 +++---
From: Frederic Barrat
Remove unused structure member 'system_memory'.
Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Message-Id: <20230127122848.550083-2-fbar...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2
From: Murilo Opsfelder Araujo
`make tests/migration/stress` fails with:
FAILED: tests/migration/stress
cc -m64 -mlittle-endian -o tests/migration/stress
tests/migration/stress.p/stress.c.o -Wl,--as-needed -Wl,--no-undefined -pie
-Wl,--warn-common -Wl,-z,relro -Wl,-z,now
From: Frederic Barrat
The name is for the region mapping the PHB xscom registers. It was
apparently a bad cut-and-paste from the per-stack pci xscom area just
above, so we had two regions with the same name.
Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Message-Id:
From: Frederic Barrat
Update register value per its P10 DD2 definition.
Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Message-Id: <20230127122848.550083-4-fbar...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
include/hw/pci-host/pnv_phb4.h | 2 +-
1 file changed,
From: Bernhard Beschow
The "platform" node is available through data->node, so use that instead
of making assumptions about the parent device.
Signed-off-by: Bernhard Beschow
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230125130024.158721-4-shen...@gmail.com>
Signed-off-by: Daniel
-ppc-20230205
for you to fetch changes up to bd591dc1b3c39b7f73b8d9f20be6e9001c905238:
hw/display/sm501: Code style fix (2023-02-05 06:40:28 -0300)
ppc patch queue for 2023-02-05:
This queue includes patches that aren't PPC
From: BALATON Zoltan
Fix checkpatch warning about multi-line comment.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
<8801292992a304609e1eac680fe36b515592b926.1674333199.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/display/sm501.c | 3
From: Bernhard Beschow
mv64361_pcihost_map_irq() is a reimplementation of
pci_swizzle_map_irq_fn(). Resolve this redundancy.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan
Message-Id: <20230106113927.8603-1-shen...@gmail.com>
Signed-off-by:
From: BALATON Zoltan
Slightly improve readability of creating the south btidge by cnamging
type of a local variable to avoid some casts within function arguments
which makes some lines shorter and easier to read.
Also remove an unneded line break.
Signed-off-by: BALATON Zoltan
Reviewed-by:
On Sat, Feb 04, 2023 at 03:04:02AM -0800, Si-Wei Liu wrote:
> For network hardware device, I thought suspend
> just needs to wait until the completion of ongoing Tx/Rx DMA transaction
> already in the flight, rather than to drain all the upcoming packets until
> avail_idx.
It depends I guess but
In preparation for adding stage-2 support. Add Stage-2 PTW code.
Only Aarch64 fromat is supported as stage-1.
Max 48 bits IPA is supported.
Nesting stage-1 and stage-2 is not supported right now.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 112
In smmuv3_notify_iova, read the granule based on translation stage
and use VMID if valid value is sent.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 39 ++-
hw/arm/trace-events | 2 +-
2 files changed, 27 insertions(+), 14 deletions(-)
diff --git
According to SMMUv3 user manual "5.2 Stream Table Entry": All fields
with an S2 prefix (with the exception of S2VMID) are IGNORED when
stage-2 bypasses translation (Config[1] == 0).
Which means that VMID can be used(for TLB tagging) even if stage-2 is
bypassed, so we parse it unconditionally when
Allow TLB to be tagged with VMID.
If stage-1 is only supported, VMID is set to -1 and ignored from STE
and CMD_TLBI_NH* cmds.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmu-common.c | 24 +++-
hw/arm/smmu-internal.h | 2 ++
hw/arm/smmuv3.c | 12
In preparation for adding stage-2 support. Add it's configuration.
They are added as SMMUS2Cfg in SMMUTransCfg, SMMUS2Cfg hold configs
parsed from STE:
-tsz: Input range
-sl0: start level of translation
-affd: AF fault disable
-granule_sz: Granule page shift
-vmid: VMID
-vttb: PA of
Right now, either stage-1 or stage-2 are supported, this simplifies
how we can deal with TLBs.
This patch makes TLB lookup work if stage-2 is enabled instead of
stage-1.
TLB lookup is done before a PTW, if a valid entry is found we won't
do the PTW.
To be able to do TLB lookup, we need the correct
As stall is not supported, if S2S is set the translation would abort.
For S2R, we reuse the same code used for stage-1 with flag
record_faults. However when nested translation is supported we would
need to separate stage-1 and stage-2 faults.
Signed-off-by: Mostafa Saleh
---
As everything is in place, we can use the new system property to
advertise which stage is supported and remove bad_ste from STE
stage2 config.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/arm/smmuv3.c
1 - 100 of 112 matches
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