Optimize the virtio-balloon feature on the ARM platform by adding
a variable to keep track of the current hot-plugged pc-dimm size,
instead of traversing the virtual machine's memory modules to count
the current RAM size during the balloon inflation or deflation
process. This variable can be
On 2023/3/8 20:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
Signed-off-by: Yi Chen
---
target/riscv/csr.c | 18 ++
1 file changed, 14 insertions(+), 4
On 2023/3/9 15:27, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC
Hi Dennis,
Thank for this patch.
On 8/3/23 01:59, dennis.wu wrote:
qatzip https://github.com/intel/QATzip is a project that
supply the zlib like api with the Intel QAT hardware.
compress and decompress performance with small data block
(4kb page) is low with qatzip API. so we compose multiple
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
PRIV_VERSION_LATEST, at this moment assigned to PRIV_VERSION_1_12_0, is
used in all generic CPUs:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
When a new PRIV version is made available we can
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
The setter is doing nothing special. Just set env->priv_ver directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we're not
The patchset tries to:
- Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
- Use env_archcpu() to get RISCVCPU pointer from env directly
- Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp to simplify type conversion
- Remove RISCVCPU argument of
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 9 -
target/riscv/csr.c| 40 ---
target/riscv/gdbstub.c| 4 ++--
3 files changed, 18
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index b8e56d2b7b..a200741083 100644
---
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c |
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or E can be
enabled.
Signed-off-by: Daniel
On 8/3/23 22:14, Stefan Hajnoczi wrote:
Not a coroutine_fn, you say?
static int64_t bdrv_sum_allocated_file_size(BlockDriverState *bs)
{
BdrvChild *child;
int64_t child_size, sum = 0;
QLIST_FOREACH(child, >children, next) {
if (child->role &
Hello Thomas,
one typo below,
On 3/8/23 15:12, Thomas Huth wrote:
Based on the announcement e-mail that Paolo sent to the qemu-devel
mailing list two days ago - let's spread the word via the blog, too!
Signed-off-by: Thomas Huth
---
_posts/2023-03-08-kvm-forum-cfp.md | 62
Reviewed-by: Paolo Bonzini
Il mer 8 mar 2023, 15:12 Thomas Huth ha scritto:
> Based on the announcement e-mail that Paolo sent to the qemu-devel
> mailing list two days ago - let's spread the word via the blog, too!
>
> Signed-off-by: Thomas Huth
> ---
> _posts/2023-03-08-kvm-forum-cfp.md |
> On 08.03.23 01:42, Michael S. Tsirkin wrote:
> > On Wed, Mar 01, 2023 at 06:38:13AM +, Yangming wrote:
> >> Optimize the virtio-balloon feature on the ARM platform by adding a
> >> variable to keep track of the current hot-plugged pc-dimm size,
> >> instead of traversing the virtual
On 2023/2/23 2:51, Daniel Henrique Barboza wrote:
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR, has
always been a no-op as well
On 2023/3/9 11:05, Jim Shu wrote:
On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei wrote:
On 2023/3/5 17:42, Jim Shu wrote:
This patch also enables debugger to set current privilege mode to
VU/VS-mode.
Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
support H-extension.
On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei wrote:
>
>
> On 2023/3/5 17:42, Jim Shu wrote:
> > This patch also enables debugger to set current privilege mode to
> > VU/VS-mode.
> >
> > Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
> > support H-extension.
> >
> > Signed-off-by:
On Wed, Mar 8, 2023 at 8:25 PM Michael S. Tsirkin wrote:
>
> On Wed, Mar 08, 2023 at 01:21:52PM +0100, Philippe Mathieu-Daudé wrote:
> > On 8/3/23 13:17, Michael S. Tsirkin wrote:
> > > On Wed, Mar 08, 2023 at 08:40:42AM +0100, Philippe Mathieu-Daudé wrote:
> > > > On 8/3/23 07:56, Jason Wang
On Mon, Mar 06, 2023 at 05:28:24PM +, David Woodhouse wrote:
> Indeed, I don't think we care about the in-kernel I/OAPIC. I don't
> think we care about the kernel knowing about e.g. "GSI #11" at all. We
> can just deliver it as MSI (for the I/OAPIC) or using KVM_INTERRUPT and
> the interrupt
On 3/8/23 12:19, Daniel Henrique Barboza wrote:
+static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
+{
+CPURISCVState *env = >env;
+int i, priv_version = -1;
+
+if (cpu->cfg.priv_spec) {
+if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+
On 3/8/23 12:19, Daniel Henrique Barboza wrote:
PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0,
};
+#define PRIV_VERSION_LATEST PRIV_VERSION_1_12_0
Any reason not to make this a enumeration value:
PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0
?
r~
This commit adds a test to ensure `all-merge` functions as expected.
We also add a negative test to ensure we haven't regressed previous
functionality.
Signed-off-by: Daniel Xu
---
tests/unit/test-qga.c | 158 +-
1 file changed, 141 insertions(+), 17
Previously capture-output was an optional boolean flag that either
captured all output or captured none. While this is OK in most cases, it
lacks flexibility for more advanced capture cases, such as wanting to
only capture stdout.
This commits refactors guest-exec qapi to take an enum for capture
Currently, any captured output (via `capture-output`) is segregated into
separate GuestExecStatus fields (`out-data` and `err-data`). This means
that downstream consumers have no way to reassemble the captured data
back into the original stream.
This is relevant for chatty and semi-interactive
Currently, the captured output (via `capture-output`) is segregated into
separate GuestExecStatus fields (`out-data` and `err-data`). This means
that downstream consumers have no way to reassemble the captured data
back into the original stream.
This is relevant for chatty and semi-interactive
On 3/8/23 13:02, Nina Schoetterl-Glausch wrote:
Test COMPARE HALFWORD RELATIVE LONG instructions.
Test that the bytes following the second operand do not affect the
instruction.
Test the sign extension performed on the second operand.
Signed-off-by: Nina Schoetterl-Glausch
---
Reviewed-by:
On 3/8/23 13:02, Nina Schoetterl-Glausch wrote:
The second operand of COMPARE HALFWORD RELATIVE LONG is a signed
halfword, it does not have the same size as the first operand.
Fixes: a7e836d5eb ("target-s390: Convert COMPARE, COMPARE LOGICAL")
Signed-off-by: Nina Schoetterl-Glausch
---
v2 is the same as v1. I sent it by accident, sorry :).
Stefan
On Wed, 8 Mar 2023 at 17:18, Stefan Hajnoczi wrote:
>
> Not a coroutine_fn, you say?
>
> static int64_t bdrv_sum_allocated_file_size(BlockDriverState *bs)
> {
> BdrvChild *child;
> int64_t child_size, sum = 0;
>
>
Not a coroutine_fn, you say?
static int64_t bdrv_sum_allocated_file_size(BlockDriverState *bs)
{
BdrvChild *child;
int64_t child_size, sum = 0;
QLIST_FOREACH(child, >children, next) {
if (child->role & (BDRV_CHILD_DATA | BDRV_CHILD_METADATA |
I am looking to emulate a SH2 board, specifically SH7055. I see that there
is already an implementation for SH4, although in places, incomplete from
the comment I saw. Especially interrupts.
Compared to SH4, SH2 is simpler in that it has no MMU, so address 0x1000 is
exactly that. And since SH4 is
Am 08.03.23 um 11:39 schrieb Marc-André Lureau:
Volker, Wim, it would be nice if you could review/comment too!
thanks
Hi,
last weekend I replaced pulseaudio with pipewire on my host computer and
tested the QEMU pipewire backend. It doesn't work well on my computer,
but with a few changes
Not a coroutine_fn, you say?
static int64_t bdrv_sum_allocated_file_size(BlockDriverState *bs)
{
BdrvChild *child;
int64_t child_size, sum = 0;
QLIST_FOREACH(child, >children, next) {
if (child->role & (BDRV_CHILD_DATA | BDRV_CHILD_METADATA |
The second operand of COMPARE HALFWORD RELATIVE LONG is a signed
halfword, it does not have the same size as the first operand.
Fixes: a7e836d5eb ("target-s390: Convert COMPARE, COMPARE LOGICAL")
Signed-off-by: Nina Schoetterl-Glausch
---
target/s390x/tcg/insn-data.h.inc | 4 ++--
Test COMPARE HALFWORD RELATIVE LONG instructions.
Test that the bytes following the second operand do not affect the
instruction.
Test the sign extension performed on the second operand.
Signed-off-by: Nina Schoetterl-Glausch
---
I don't know what the coding style is for inline asm.
The second operand of COMPARE HALFWORD RELATIVE LONG is a signed
halfword, it does not have the same size as the first operand.
Fix this and add a tcg test for c(g)hrl.
Nina Schoetterl-Glausch (2):
target/s390x: Fix emulation of C(G)HRL
tests/tcg/s390x: Add C(G)HRL test
Hello Qianfan Zhao,
Thanks for contributing this work to Qemu! With your contribution, we would
get yet another Allwinner SoC supported, making it three in total
(A10/H3/R40). That's great.
My thoughts are that maybe we should try to re-use commonality between
these SoCs where we can. Ofcourse,
This function will validate and change/disable extensions that aren't
compatible with a certain spec version. Since the function is called
at the start of riscv_cpu_validate_set_extensions(), we're disabling
extensions without guaranteeing that they aren't being turned on again
after the
set_misa() will be tuned up to do more than it's already doing and it
will be redundant to what riscv_cpu_validate_set_extensions() does.
Note that we don't ever change env->misa_mlx in this function, so
set_misa() can be replaced by just assigning env->misa_ext and
env->misa_ext_mask to 'ext'.
Put all the env->priv_spec related validation into a helper to unclog
riscv_cpu_realize a bit.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 81 ++
1 file changed, 46 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.c
PRIV_VERSION_LATEST, at this moment assigned to PRIV_VERSION_1_12_0, is
used in all generic CPUs:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
When a new PRIV version is made available we can just update the LATEST
macro.
Signed-off-by: Daniel
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
object to keep both in sync. At this moment this is being
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we're not updating RVG;
- mask the write using misa_ext_mask to
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should
The 'G' bit in misa_ext is a virtual extension that enables a set of
extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid
setting it for write_misa(). Add it so we can gate write_misa() properly
against it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 4
Center all validations that are scattered in riscv_cpu_realize() in the
same function.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 74 ++
1 file changed, 35 insertions(+), 39 deletions(-)
diff --git a/target/riscv/cpu.c
riscv_cpu_validate_set_extensions() will play a future role in
write_misa(). First we need to ensure that this function is validating
first and setting cfg values later. At this moment this is not the case
of the RVV validation.
Move RVV validation up. Leave the 'ext |= RVV' where it is - next
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5060a98b6d..0baed79ec2
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this moment, this is done at the start of our validation
The extremely tedious code that sets cpu->cfg based on misa_ext, and
vice-versa, is scattered around riscv_cpu_validate_set_extensions() and
set_misa().
Introduce helpers to do this work, cleaning up the logic of both
functions a bit. While we're at it, add a note in cpu.h informing that
any
This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or E can be
enabled.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 12
Hi,
During the review of a series that did some work in the RISCV_FEATURES*
enum, Liu Zhiwei commented on how we could centralize the all the
extension validation code and integrate it with write_misa() [1].
This does at least part of what was suggested. The idea is that, ATM, we
have too many
The code that validates ext_v in riscv_cpu_validate_set_extensions() is
not properly indented - we're missing an extra indent level right after
the first check that uses cfg->elen.
In the end the 'v' verification is a bit too large in comparison with
the others, and can be put in a separated
Now that the function is a no-op if 'env.misa_ext != 0', and no one that
are setting misa_ext != 0 is calling it because set_misa() is setting
the cpu cfg accordingly, remove the now deprecated code and rename the
function to register_generic_cpu_props().
This function is now doing exactly what
From: Kfir Manor
Change requester_freeze so that the VSS backup type queried from the registry
Signed-off-by: Kfir Manor
Reviewed-by: Konstantin Kostiuk
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/requester.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
The custom action uses cmd.exe to run VSS Service installation
and removal which causes an interactive command shell to spawn.
This shell can be used to execute any commands as a SYSTEM user.
Even if call qemu-ga.exe directly the interactive command shell
will be spawned as qemu-ga.exe is a
From: Kfir Manor
Adds registry value VssOption with value 1 to QEMU Guest Agent VSS Provider
service registry key
Signed-off-by: Kfir Manor
Reviewed-by: Konstantin Kostiuk
Signed-off-by: Konstantin Kostiuk
---
qga/installer/qemu-ga.wxs | 4
1 file changed, 4 insertions(+)
diff --git
From: Kfir Manor
Query VSS backup type number (DWORD) from QEMU Guest Agent VSS Provider
registry key registry value VssOption
Translate the VSS backup type number (DWORD) into its VSS backup type
(VSS_BACKUP_TYPE)
Returns the queried VSS backup type if the program encounters unexpected
Remove the 'change' button from "Programs and Features" because it does
not checks if a user is an admin or not. The installer has no components
to choose from and always installs everything. So the 'change' button is
not obviously needed but can create a security issue.
resolves:
The following changes since commit 9832009d9dd2386664c15cc70f6e6bfe062be8bd:
Merge tag 'pull-riscv-to-apply-20230306' of
https://gitlab.com/palmer-dabbelt/qemu into staging (2023-03-07 12:53:00 +)
are available in the Git repository at:
g...@github.com:kostyanf14/qemu.git
On 3/8/23 09:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
Signed-off-by: Yi Chen
---
target/riscv/csr.c | 18 ++
1 file changed, 14 insertions(+), 4
Just checking if this is on the radar to be merged ...
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, March 6, 2023 10:34 PM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; richard.hender...@linaro.org;
> phi...@linaro.org; peter.mayd...@linaro.org; Brian Cain
> ;
From: "Dr. David Alan Gilbert"
Fixup the migration compatibility for existing machine types
so that they do not enable msi-x.
Symptom:
(qemu) qemu: get_pci_config_device: Bad config data: i=0x34 read: 84 device: 98
cmask: ff wmask: 0 w1cmask:0
qemu: Failed to load PCIDevice:config
qemu:
On Wed, 2023-03-08 at 17:42 +, Alex Bennée wrote:
>
> David Woodhouse writes:
>
> > From: David Woodhouse
> >
> > The kernel in Fedora 31 doesn't support 'xen_no_vector_callback' on
> > its command line, so add a slightly newer version as a prelude to
> > enabling avocado tests for Xen
On Wed, 2023-03-08 at 17:45 +, Alex Bennée wrote:
>
> David Woodhouse writes:
>
> > From: David Woodhouse
> >
> > Exercise guests with a few different modes for interrupt delivery. In
> > particular we want to cover:
> >
> > • Xen event channel delivery via GSI to the I/O APIC
> > •
On Wed, 8 Mar 2023, BALATON Zoltan wrote:
On Wed, 8 Mar 2023, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 8/3/23 00:47, Philippe Mathieu-Daudé wrote:
From: BALATON Zoltan
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north
On 3/8/23 10:08, Paolo Bonzini wrote:
On 3/8/23 17:47, Richard Henderson wrote:
The case that I was imagining for smp_mb__before_rmw() is something like this:
wake_me = true;
smp_mb__before_rmw();
if (qatomic_xchg(_sleep, true)) { ... }
where you really need a full barrier.
On Wed, 2023-03-08 at 08:05 -0500, mreza...@redhat.com wrote:
> From: Miroslav Rezanina
>
> Upstream commit ddf0fd9ae1 "hw/xen: Support HVM_PARAM_CALLBACK_TYPE_GSI
> callback"
> added kvm_xen_maybe_deassert_callback usage to target/i386/kvm/kvm.c file
> without
> conditional preprocessing
On 3/8/23 17:47, Richard Henderson wrote:
The case that I was imagining for smp_mb__before_rmw() is something
like this:
wake_me = true;
smp_mb__before_rmw();
if (qatomic_xchg(_sleep, true)) { ... }
where you really need a full barrier.
What is different about this that
On 07.03.23 14:44, Hanna Czenczek wrote:
On 07.03.23 13:22, Fiona Ebner wrote:
Hi,
I am suspecting that commit 7e5cdb345f ("ide: Increment BB in-flight
counter for TRIM BH") introduced an issue in combination with draining.
From a debug session on a costumer's machine I gathered the following
David Woodhouse writes:
> From: David Woodhouse
>
> Exercise guests with a few different modes for interrupt delivery. In
> particular we want to cover:
>
> • Xen event channel delivery via GSI to the I/O APIC
> • Xen event channel delivery via GSI to the i8259 PIC
> • MSIs routed to PIRQ
David Woodhouse writes:
> From: David Woodhouse
>
> The kernel in Fedora 31 doesn't support 'xen_no_vector_callback' on
> its command line, so add a slightly newer version as a prelude to
> enabling avocado tests for Xen guests.
Why slightly newer rather than current release?
Our existing
Am 08.03.2023 um 15:26 hat Stefan Hajnoczi geschrieben:
> On Wed, Mar 08, 2023 at 09:48:17AM +0100, Kevin Wolf wrote:
> > Am 07.03.2023 um 20:20 hat Stefan Hajnoczi geschrieben:
> > > On Tue, Mar 07, 2023 at 06:17:22PM +0100, Kevin Wolf wrote:
> > > > Am 01.03.2023 um 21:57 hat Stefan Hajnoczi
On 7/3/23 19:34, Richard Henderson wrote:
While this enumerator has been present since the first commit,
it isn't ever used. The first actual use of round-to-odd came
with SVE, which currently uses float_round_to_odd instead of
the arm-specific enumerator.
Amusingly, the comment about
On Wed, Mar 08, 2023 at 12:42:11PM +0100, Kevin Wolf wrote:
> Am 07.03.2023 um 15:18 hat Stefan Hajnoczi geschrieben:
> > On Tue, Mar 07, 2023 at 09:48:51AM +0100, Kevin Wolf wrote:
> > > Am 01.03.2023 um 17:16 hat Stefan Hajnoczi geschrieben:
> > > > On Fri, Feb 03, 2023 at 08:17:28AM -0500,
From: "Michael S. Tsirkin"
This reverts commit eebb38a5633a77f5fa79d6486d5b2fcf8fbe3c07.
Fixes: eebb38a563 ("x86: use typedef for SetupData struct")
Signed-off-by: Michael S. Tsirkin
Tested-by: Nathan Chancellor
Tested-by: Dov Murik
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S.
From: Richard Henderson
We forgot to set cc_src, which is used for computing C.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1370
Signed-off-by: Richard Henderson
Message-Id: <20230114180601.2993644-1-richard.hender...@linaro.org>
Cc: qemu-sta...@nongnu.org
Fixes: 1d0b926150e5
Hello!
This is my first attempt to perform a stable qemu release.
Doing it in a way similar to how Michael Roth did it before :)
But since this is my first attempt, this is an RFC for now.
The following new patches are queued for QEMU stable v7.2.1:
From: Guenter Roeck
The values in env->flags are a subset of tb->flags.
Restore only the bits that belong.
Cc: qemu-sta...@nongnu.org
Fixes: ab419fd8a035 ("target/sh4: Fix TB_FLAG_UNALIGN")
Signed-off-by: Guenter Roeck
Message-ID: <20221212011345.ga2235...@roeck-us.net>
[rth: Reduce to only
From: Laszlo Ersek
The modern ACPI CPU hotplug interface was introduced in the following
series (aa1dd39ca307..679dd1a957df), released in v2.7.0:
1 abd49bc2ed2f docs: update ACPI CPU hotplug spec with new protocol
2 16bcab97eb9f pc: piix4/ich9: add 'cpu-hotplug-legacy' property
3
From: Alex Bennée
The latest hexagon compiler picks up that we never consume wcount.
Given the name of the #define that rcount checks against is WCOUNT_MAX
I figured the check just got missed.
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: "Michael S. Tsirkin"
This reverts commit e935b735085dfa61d8e6d276b6f9e7687796a3c7.
Fixes: e935b73508 ("x86: return modified setup_data only if read as memory, not
as file")
Signed-off-by: Michael S. Tsirkin
Tested-by: Nathan Chancellor
Tested-by: Dov Murik
Reviewed-by: Michael S.
From: Kevin Wolf
In order to write the bitmap table to the image file, it is converted to
big endian. If the write fails, it is passed to clear_bitmap_table() to
free all of the clusters it had allocated before. However, if we don't
convert it back to native endianness first, we'll free things
From: Richard Henderson
Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
From: Klaus Jensen
The eventidx and doorbell value are not handling endianness correctly.
Fix this.
Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support")
Cc: qemu-sta...@nongnu.org
Reported-by: Guenter Roeck
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
(cherry
From: "Dr. David Alan Gilbert"
In bad9c5a516 ("virtio-rng-pci: fix migration compat for vectors") I
fixed the virtio-rng-pci migration compatibility, but it was discovered
that we also need to fix the other aliases of the device for the
transitional cases.
Fixes: 9ea02e8f1 ('virtio-rng-pci:
From: Jason Wang
Without caching mode, MAP notifier won't work correctly since guest
won't send IOTLB update event when it establishes new mappings in the
I/O page tables. Let's fail the IOMMU notifiers early instead of
misbehaving silently.
Reviewed-by: Eric Auger
Tested-by: Viktor Prutyanov
From: Paolo Bonzini
When ADCX is followed by ADOX or vice versa, the second instruction's
carry comes from EFLAGS and the condition codes use the CC_OP_ADCOX
operation. Retrieving the carry from EFLAGS is handled by this bit
of gen_ADCOX:
tcg_gen_extract_tl(carry_in, cpu_cc_src,
From: Yajun Wu
After live migration with virtio block device, qemu crash at:
#0 0x55914f46f795 in object_dynamic_cast_assert
(obj=0x559151b7b090, typename=0x55914f80fbc4 "qio-channel", file=0x55914f80fb90
"/images/testvfe/sw/qemu.gerrit/include/io/channel.h", line=30,
From: Richard Henderson
Conversion to probe_access_full missed applying the page offset.
Cc: qemu-sta...@nongnu.org
Reported-by: Sid Manning
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20230126233134.103193-1-richard.hender...@linaro.org
Fixes:
From: Chenyi Qiang
vmem->bitmap indexes the memory region of the virtio-mem backend at a
granularity of block_size. To calculate the index of target section offset,
the block_size should be divided instead of the bitmap_size.
Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager
From: Klaus Jensen
Prior to reading the shadow doorbell cq head, we have to update the
eventidx. Otherwise, we risk that the driver will skip an mmio doorbell
write. This happens on riscv64, as reported by Guenter.
Adding the missing update to the cq eventidx fixes the issue.
Fixes:
From: Jason Wang
Without dt mode, device IOTLB notifier won't work since guest won't
send device IOTLB invalidation descriptor in this case. Let's fail
early instead of misbehaving silently.
Reviewed-by: Laurent Vivier
Tested-by: Laurent Vivier
Tested-by: Viktor Prutyanov
Buglink:
From: Paolo Bonzini
When installing shared libraries, as is the case for libvfio-user.so,
Meson will include relative symbolic links in the output of
"meson introspect --installed":
{
"libvfio-user.so": "/usr/local/lib64/libvfio-user.so",
...
}
In the case of
From: David Hildenbrand
Unfortunately, commit f7b9dcfbcf44 broke populate_read_range(): the loop
end condition is very wrong, resulting in that function not populating the
full range. Lets' fix that.
Fixes: f7b9dcfbcf44 ("migration/ram: Factor out populating pages readable in
From: Chenyi Qiang
It should be the variable rdl2 to revert the already-notified listeners.
Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager interface")
Signed-off-by: Chenyi Qiang
Message-Id: <20221228090312.17276-1-chenyi.qi...@intel.com>
Cc: qemu-sta...@nongnu.org
Reviewed-by:
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