Add asymmetric crypto support in vhost_user backend.
Signed-off-by: Gowrishankar Muthukrishnan
---
backends/cryptodev-vhost-user.c | 9 +++---
hw/virtio/vhost-user.c | 52 -
2 files changed, 43 insertions(+), 18 deletions(-)
diff --git a/backends/crypto
-20230513
for you to fetch changes up to 874c52991e1fbe020812b4b15440b6875369aacf:
target/openrisc: Setup FPU for detecting tininess before rounding
(2023-05-11 15:40:28 +0100)
OpenRISC FPU Updates for 8.1
A few fixes and updates to
From: rmsyn
Adds support for ATmega16u4 and ATmega32u4 MCU definitions.
Defines interrupts, memory layout, and machine types for generic
ATmega16u4 and ATmega32u4 MCUs.
Signed-off-by: rmsyn
---
hw/avr/arduino.c | 36 ++
hw/avr/atmega.c | 122 +
On Thursday, May 11, 2023 4:12:34 PM CEST Christian Schoenebeck wrote:
> Add '9P' to the summary output section of 'VirtFS' to avoid being
> confused with virtiofs.
>
> Based-on: <20230503130757.863824-1-pefo...@google.com>
> Signed-off-by: Christian Schoenebeck
> ---
> meson.build | 4 ++--
> 1
Am 12. Mai 2023 12:04:07 UTC schrieb Juan Quintela :
>Bernhard Beschow wrote:
>> Am 12. Mai 2023 07:35:27 UTC schrieb Juan Quintela :
>>>juan.quint...@gmail.com wrote:
Hi If you are interested in any topic, please let me know. Later, Juan.
>>>
>>>Hi folks
>>>
>>>So far what we have in the
On 2023/05/13 0:43, Tomasz Dzieciol wrote:
Packet-split descriptors are used by Linux VF driver for MTU values from 2048
Signed-off-by: Tomasz Dzieciol
---
hw/net/igb_core.c | 360 ++--
hw/net/igb_regs.h | 9 ++
hw/net/trace-events | 2 +-
3
Am 3. Mai 2023 19:52:41 UTC schrieb Mark Cave-Ayland
:
>On 27/04/2023 19:15, Bernhard Beschow wrote:
>
>> Am 27. April 2023 10:52:17 UTC schrieb Mark Cave-Ayland
>> :
>>> On 26/04/2023 21:14, Bernhard Beschow wrote:
>>>
Am 26. April 2023 18:18:35 UTC schrieb Bernhard Beschow
:
On 5/12/23 16:38, fa...@mail.ustc.edu.cn wrote:
sigframe::pretcode & rt_sigframe::pretcode must align of 16n-sizeof(void*) instead of 16n, Because rsp align
of 16n before instruction "call" in caller, After "call", push address of "call" in
caller. sp of begin in callee is 16n-sizeof(void*)
Re
Am 27. April 2023 12:31:10 UTC schrieb Mark Cave-Ayland
:
>On 26/04/2023 19:25, Bernhard Beschow wrote:
>
>> Am 26. April 2023 11:33:40 UTC schrieb Mark Cave-Ayland
>> :
>>> On 22/04/2023 16:07, Bernhard Beschow wrote:
>>>
isa_get_irq() asks for an ISADevice which piix-ide doesn't provid
Am 21. April 2023 07:38:10 UTC schrieb "Michael S. Tsirkin" :
>On Mon, Apr 03, 2023 at 09:41:17AM +0200, Bernhard Beschow wrote:
>> There is currently a dedicated PIIX3 device model for use under Xen. By
>> reusing
>> existing PCI API during initialization this device model can be eliminated
>
On 5/12/23 15:41, Peter Maydell wrote:
+static bool trans_ERETA(DisasContext *s, arg_reta *a)
+{
+TCGv_i64 dst;
+
+if (!dc_isar_feature(aa64_pauth, s)) {
+return false;
+}
+/* The FGT trap takes precedence over an auth trap. */
+if (s->fgt_eret) {
+gen_exceptio
On 5/12/23 15:41, Peter Maydell wrote:
Convert the last four BR-with-pointer-auth insns to decodetree.
The remaining cases in the outer switch in disas_uncond_b_reg()
all return early rather than leaving the case statement, so we
can delete the now-unused code at the end of that function.
Signed
On 5/12/23 15:41, Peter Maydell wrote:
Convert the single-register pointer-authentication variants of BR,
BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of
the legacy decoder and will be dealt with in the next commit.)
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode
On 5/12/23 15:41, Peter Maydell wrote:
Convert the simple (non-pointer-auth) BR, BLR and RET insns
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 5
target/arm/tcg/translate-a64.c | 55 ++
2 files changed, 54 insertions(
On 5/12/23 22:46, Taylor Simpson wrote:
The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1:
Merge tag 'pull-tcg-20230511-2' ofhttps://gitlab.com/rth7680/qemu into
staging (2023-05-11 11:44:23 +0100)
are available in the Git repository at:
https://github.com/qui
The attribute isn't used since commit 5c9736789b79ea49cd236ac326f0a414f63b1015
"i82378: Cleanup implementation".
Signed-off-by: Bernhard Beschow
---
hw/isa/i82378.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c
index 5432ab5065..63e0857208 100644
--- a/hw/i
This series:
* Removes dead code from omap_uart and i82378
* Resolves redundant code in the i8254 timer devices
* Replaces string literals by macro usage for TYPE_ISA_PARALLEL devices
Bernhard Beschow (4):
hw/timer/i8254_common: Share "iobase" property via base class
hw/arm/omap: Remove unused
Rather than using a string literal which is prone to typos let's use a macro
instead which is caught by the compiler if mistyped.
Signed-off-by: Bernhard Beschow
---
include/hw/char/parallel.h | 2 ++
hw/char/parallel-isa.c | 2 +-
hw/char/parallel.c | 1 -
hw/isa/isa-superio.c
The function is unused since commit
bdad3654d3c55f478e538037d9eccd204e5fc8ee ('hw/arm/nseries: Remove
invalid/unnecessary n8x0_uart_setup()').
Signed-off-by: Bernhard Beschow
---
include/hw/arm/omap.h | 1 -
hw/char/omap_uart.c | 9 -
2 files changed, 10 deletions(-)
diff --git a/incl
Both TYPE_KVM_I8254 and TYPE_I8254 have their own but same implementation of
the "iobase" property. The storage for the property already resides in
PITCommonState, so also move the property definition there.
Signed-off-by: Bernhard Beschow
---
hw/i386/kvm/i8254.c | 1 -
hw/timer/i8254.c
Rename virtio_error function to virtio_error_impl and wrap it with
virtio_error macro, it adds the "virtio" prefix to the error message.
Remove redundant "virtio" prefixes in virtio_error calls.
Signed-off-by: Maxim Kostin
---
hw/virtio/virtio.c | 10 +-
include/hw/virtio/virtio
On 5/12/23 16:34, Peter Maydell wrote:
Hi; here's a relatively small target-arm queue, pretty much all
bug fixes. (There are a few non-arm patches that I've thrown in
there too for my convenience :-))
thanks
-- PMM
The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1:
The following changes since commit c1eb2ddf0f8075faddc5f7c3d39feae3e8e9d6b4:
Update version for v8.0.0 release (2023-04-19 17:27:13 +0100)
are available in the Git repository at:
https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20230513
for you to fetch changes up to
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa..61d7
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed-by: Rich
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/fpu_helper.c b/target/o
On 5/12/23 15:41, Peter Maydell wrote:
Convert the test-and-branch-immediate insns TBZ and TBNZ
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 7 +++
target/arm/tcg/translate-a64.c | 25 +
2 files changed, 12 insertions(+), 20 d
On 5/12/23 15:41, Peter Maydell wrote:
Convert the immediate conditional branch insn B.cond to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 30 ++
2 files changed, 8 insertions(+), 24 deletio
On 5/12/23 15:41, Peter Maydell wrote:
+@cbzsf:1 .. nz:1 ... rt:5 &cbz imm=%imm19
+
+CBZ . 011010 . ... . @cbz
Similarly re the single-use @format.
Either way,
Reviewed-by: Richard Henderson
r~
Hi Philippe,
On 2023/5/10 18:13, Philippe Mathieu-Daudé wrote:
> Hi Yang,
>
> On 5/1/23 10:16, Michael S. Tsirkin wrote:
>> From: Yicong Yang
>>
>> Currently we'll always generate a cluster node no matter user has
>> specified '-smp clusters=X' or not. Cluster is an optional level
>> and will pa
On 5/12/23 15:40, Peter Maydell wrote:
Convert the unconditional branch immediate insns B and BL to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 9 +
target/arm/tcg/translate-a64.c | 31 +++
2 files changed, 20 insertions(
On 5/12/23 15:40, Peter Maydell wrote:
+# Extract
+
+&extractrd rn rm imm sf
+@extract_64 1 .. .. 1 . rm:5 imm:6 rn:5 rd:5 &extract sf=1
+@extract_32 0 .. .. 0 . rm:5 0 imm:5 rn:5 rd:5&extract sf=0
+
+EXTR. 00 100111 . 0 . .. . . @extra
On 5/12/23 15:40, Peter Maydell wrote:
+!disas_sme(s,insn) &&
Space after comma. Otherwise,
Reviewed-by: Richard Henderson
r~
On 5/12/23 15:40, Peter Maydell wrote:
The A64 translator uses a hand-written decoder for everything except
SVE or SME. It's fairly well structured, but it's becoming obvious
that it's still more painful to add instructions to than the A32
translator, because putting a new instruction into the r
34 matches
Mail list logo
