On 6/30/23 09:58, Song Gao wrote:
@@ -1315,3 +1315,17 @@ xvreplgr2vr_b0111 01101001 0 0 . .
@vr
xvreplgr2vr_h0111 01101001 0 1 . .@vr
xvreplgr2vr_w0111 01101001 0 00010 . .@vr
xvreplgr2vr_d0111 01101001 0 00011
On 6/30/23 09:58, Song Gao wrote:
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 10 ++
target/loongarch/insn_trans/trans_lasx.c.inc | 5 +
target/loongarch/insn_trans/trans_lsx.c.inc | 13 +++--
On 6/30/23 09:58, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lasx.c.inc | 6 ++
target/loongarch/translate.c | 1 +
2 files changed, 7 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_lasx.c.inc
Reviewed-by: Richard
On 6/30/23 09:58, Song Gao wrote:
This patch includes:
- XVADD.{B/H/W/D/Q};
- XVSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 23 +
target/loongarch/insn_trans/trans_lasx.c.inc | 52 +-
target/loongarch/insn_trans/trans_lsx.c.inc | 511
On 6/30/23 09:58, Song Gao wrote:
+#if HOST_BIG_ENDIAN
+#define B(x) B[(x) ^ 15]
+#define H(x) H[(x) ^ 7]
+#define W(x) W[(x) ^ 3]
+#define D(x) D[(x) ^ 2]
+#define UB(x) UB[(x) ^ 15]
+#define UH(x) UH[(x) ^ 7]
+#define UW(x) UW[(x) ^ 3]
+#define UD(x) UD[(x) ^ 2]
+#define Q(x) Q[(x) ^ 1]
On Sat, Jul 01, 2023 at 04:01:18PM +0900, Akihiko Odaki wrote:
> The function number must be lower than the next function number
> advertised with ARI. Add a check to enforce this.
>
> I suggested this change at:
>
On Sat, Jul 01, 2023 at 04:01:21PM +0900, Akihiko Odaki wrote:
> The next function numbers are expected to form a linked list ending with
> 0.
>
> Fixes: 3a977deebe ("Intrdocue igb device emulation")
> Signed-off-by: Akihiko Odaki
> ---
> hw/net/igb_core.h | 3 +++
> hw/net/igb.c | 4 +---
On Sat, Jul 01, 2023 at 04:01:22PM +0900, Akihiko Odaki wrote:
> The function number must be lower than the next function number
> advertised with ARI.
>
> Signed-off-by: Akihiko Odaki
I don't get this logic at all - where is the limitation coming from?
All I see in the spec is:
Next
On Sat, Jul 01, 2023 at 04:09:31PM +0900, Akihiko Odaki wrote:
> Yes, I want the slot number restriction to be enforced. If it worries you
> too much for regressions, you may implement it as a warning first and then
> turn it a hard error when the next development phase starts.
That's not a bad
From: Eugenio Pérez
QEMU does not emulate it so it must be disabled as long as the backend
does not support it.
Signed-off-by: Eugenio Pérez
Message-Id: <20230602173328.1917385-1-epere...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Acked-by: Jason Wang
From: Vivek Kasireddy
In the case where the console does not have gl capability, and
if blob is set to true, make sure that the display updates still
work. Commit e86a93f55463 accidentally broke this by misplacing
the return statement (in resource_flush) causing the updates to
be silently
From: Shameer Kolothum
When vfio_enable_vectors() returns with less than requested nr_vectors
we retry with what kernel reported back. But the retry path doesn't
call vfio_prepare_kvm_msi_virq_batch() and this results in,
qemu-system-aarch64: vfio: Error: Failed to enable 4 MSI vectors, retry
The following patches are queued for QEMU stable v7.2.4:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2023-07-06, and the release is planned for 2023-07-08:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any additional
From: Zhenzhong Duan
The kvm irqchip notifier is only registered if the device supports
INTx, however it's unconditionally removed in vfio realize error
path. If the assigned device does not support INTx, this will cause
QEMU to crash when vfio realize fails. Change it to conditionally
remove
From: Nicholas Piggin
It is possible to store a very large value to the decrementer that it
does not raise the decrementer exception so the timer is scheduled, but
the next time value wraps and is treated as in the past.
This can occur if (u64)-1 is stored on a zero-triggered exception, or
From: Nicholas Piggin
The icount-based QEMU_CLOCK_VIRTUAL runs ahead of the RT clock at times.
When warping, it is possible it is still ahead at the end of the warp,
which causes icount adaptive mode to adjust it backward. This can result
in the machine observing time going backwards.
Prevent
On 2023/07/01 23:31, Ani Sinha wrote:
On 01-Jul-2023, at 12:31 PM, Akihiko Odaki wrote:
The next function numbers are expected to form a linked list ending with
0.
Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in
docs/pcie_sriov.txt")
Signed-off-by: Akihiko Odaki
---
On Sun, Jun 25, 2023 at 9:59 AM Bin Meng wrote:
>
> The minimum Ethernet frame length is 60 bytes. For short frames with
> smaller length like ARP packets (only 42 bytes), on a real world NIC
> it can choose either padding its length to the minimum required 60
> bytes, or sending it out directly
Hi Peter,
> The reference manual is very unclear about what this "emulated
> system off" mode actually does. I think that implementing
> real "system off" is probably simpler. For that you should be able
> to implement it something like this:
>
> (1) the power management device implements the
Hi Phil,
> What problem are you getting with a single CPU?
> The "arm/arm-powerctl.h" API should work well.
> If you scheduled a timer, I expect it to awake
> your CPU on expiration. You can also use a QMP
> command to toggle a GPIO and trigger an IRQ.
>
> You can use the qtest API to test your
According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA—BUS
MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is
32bit wide. To properly reset it to default values, all 32bit need to be
cleared. Bit #0 "Resource Type Indicator (RTE)" needs to be enabled.
The initial
Sat, 1 Jul 2023 15:34:40 +0200 (CEST) BALATON Zoltan :
> If all 32 bits should be writtern does this need pci_set_long instead of
> pci_set_word?
Thanks for spotting. After a number of experiments I used the wrong variant.
Olaf
pgpCw5bEslAgv.pgp
Description: Digitale Signatur von OpenPGP
> On 01-Jul-2023, at 12:31 PM, Akihiko Odaki wrote:
>
> The next function numbers are expected to form a linked list ending with
> 0.
>
> Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in
> docs/pcie_sriov.txt")
> Signed-off-by: Akihiko Odaki
> ---
> docs/pcie_sriov.txt | 5
On Sat, 1 Jul 2023, Olaf Hering wrote:
According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA—BUS
MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is
32bit wide. To properly reset it to default values, all 32bit need to be
cleared. Bit #1 "Resource Type Indicator
On 6/27/23 06:26, Jason Chien wrote:
RVA23 Profiles states:
The RVA23 profiles are intended to be used for 64-bit application
processors that will run rich OS stacks from standard binary OS
distributions and with a substantial number of third-party binary user
applications that will be
On 6/30/23 13:07, Bin Meng wrote:
The 32-bit Spike boot issue has been fixed in the OpenSBI v1.3.
Let's enable the 32-bit Spike OpenSBI boot testing.
Signed-off-by: Bin Meng
---
(03/17) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike: PASS
(0.10 s)
Nice!
Reviewed-by:
On 6/30/23 13:07, Bin Meng wrote:
Upgrade OpenSBI from v1.2 to v1.3 and the pre-built bios images.
The v1.3 release includes the following commits:
440fa81 treewide: Replace TRUE/FALSE with true/false
6509127 Makefile: Remove -N ldflag to prevent linker RWX warning
65638f8 lib: utils/sys:
On 01/07/2023 10:53, Bernhard Beschow wrote:
Am 30. Juni 2023 08:48:02 UTC schrieb Paolo Bonzini :
Il mer 28 giu 2023, 13:28 Bernhard Beschow ha scritto:
Am 27. Juni 2023 12:07:40 UTC schrieb Olaf Hering :
Tue, 27 Jun 2023 10:12:50 + Bernhard Beschow :
The BAR is a 32 bit register
According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA—BUS
MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is
32bit wide. To properly reset it to default values, all 32bit need to be
cleared. Bit #1 "Resource Type Indicator (RTE)" needs to be enabled.
The initial
On Fri Jun 23, 2023 at 5:25 PM AEST, Narayana Murty N wrote:
> Currently on PPC64 qemu always dumps the guest memory in
> Big Endian (BE) format even though the guest running in Little Endian
> (LE) mode. So crash tool fails to load the dump as illustrated below:
>
> Log :
> $ virsh dump DOMAIN
On Fri Jun 30, 2023 at 1:55 PM AEST, Joel Stanley wrote:
> Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
> this warning doesn't trigger report the core thread state is 0.
>
> Signed-off-by: Joel Stanley
> ---
> hw/ppc/pnv_core.c | 10 ++
> 1 file changed, 10
On 7/1/23 10:04, Philippe Mathieu-Daudé wrote:
On 1/7/23 08:28, Richard Henderson wrote:
On 6/30/23 23:41, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Commit commit 6cc5a615 ("ui/dbus: win32 support") has broken audio/dbus
compilation when pixman is not included.
Images repairing in parallels_open() was added, thus parallels tests fail.
Access to an image leads to repairing the image. Further image check don't
detect any corruption. Remove reads after image creation in test 131.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/131 | 6 ++
In this test cluster size is 64k, but modern tools generate images with
cluster size 1M. Calculate cluster size using track field from image header.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/131 | 5 -
tests/qemu-iotests/131.out | 44 +++---
Write a pattern to the first cluster. Corrupt the data_off field and check
if the field was repaired on image opening and the pattern has not changed.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/tests/parallels-checks | 15 +++
Fill a parallels image with a pattern and write another pattern to the
second cluster. Corrupt the image and check if the pattern changes. Repair
the image and check the patterns on guest and host sides.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/tests/parallels-checks | 32
Fill the image with a pattern to generate entries in the BAT, set the first
BAT entry outside the image, try to read the corrupted image. At the image
opening it should be repaired, check for zeroes in the first cluster.
Signed-off-by: Alexander Ivanov
---
Write a pattern to the last cluster, extend the image by 1 claster, repair
and check that the last cluster still has the same pattern.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/tests/parallels-checks | 27 +++
tests/qemu-iotests/tests/parallels-checks.out | 22
Replace hardcoded numbers by variables.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/131 | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/tests/qemu-iotests/131 b/tests/qemu-iotests/131
index a847692b4c..601546c84c 100755
---
This patchset should be applied on top of [PATCH v7 0/8] parallels: Add
duplication check, repair at open, fix bugs
Add out-of-image, leak and BAT entries duplication checks tests.
Old parallels images check test (131): Refactor, fix cluster size and fix
after repairing was added to
On Fri Jun 30, 2023 at 1:55 PM AEST, Joel Stanley wrote:
> The quad model implements the EC xscoms for the p9 machine, reusing the
> same model for p10 which isn't quite correct. This series adds a PnvQuad
> class and subclasses it for P9 and P10. Implement the core thread state
> xscom as an
Repair an image at opening if the image is unclean or out-of-image
corruption was detected.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 70 +--
1 file changed, 38 insertions(+), 32 deletions(-)
diff --git a/block/parallels.c
In the next patch we will need the offset of the data area for host cluster
index calculation. Add this field and setting up code.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 7 ---
block/parallels.h | 1 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git
data_off field of the parallels image header can be corrupted. Check if
this field greater than the header + BAT size and less than file size.
Change checking code in parallels_open() accordingly.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 98
The BDRVParallelsState structure contains data_end field that is measured
in sectors. In parallels_open() initially this field is set by data_off
field from parallels image header.
According to the parallels format documentation, data_off field contains
an offset, in sectors, from the start of
Cluster offsets must be unique among all the BAT entries. Find duplicate
offsets in the BAT and fix it by copying the content of the relevant
cluster to a newly allocated cluster and set the new cluster offset to the
duplicated entry.
Add host_cluster_index() helper to deduplicate the code.
When
In the on of the next patches we need to repair leaks without changing
leaks and leaks_fixed info in res. Also we don't want to print any warning
about leaks. Add "explicit" argument to skip info changing if the argument
is false.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 19
Initially data_end is set to the data_off image header field and must not be
greater than the file size.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/block/parallels.c b/block/parallels.c
index 86bc3bfcb8..40a26908db 100644
---
Fix incorrect data end calculation in parallels_open().
Check if data_end greater than the file size.
Add change_info argument to parallels_check_leak().
Add checking and repairing duplicate offsets in BAT
Image repairing in parallels_open().
v7:
3: Renamed "change_info" argument to
bdrv_co_getlength() should be used in coroutine context. Replace
bdrv_getlength() by bdrv_co_getlength() in parallels_check_outside_image().
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/parallels.c
On 7/1/23 06:39, BALATON Zoltan wrote:
On Sat, 1 Jul 2023, Daniel Henrique Barboza wrote:
On 6/30/23 19:57, BALATON Zoltan wrote:
On Fri, 30 Jun 2023, Daniel Henrique Barboza wrote:
Patches 1, 2, 3, 5, 7 and 11 are queued.
If you would be so kind to get the remaining patches, rebase them
Am 30. Juni 2023 08:48:02 UTC schrieb Paolo Bonzini :
>Il mer 28 giu 2023, 13:28 Bernhard Beschow ha scritto:
>
>>
>>
>> Am 27. Juni 2023 12:07:40 UTC schrieb Olaf Hering :
>> >Tue, 27 Jun 2023 10:12:50 + Bernhard Beschow :
>> >
>> >> The BAR is a 32 bit register whose default value is
On Sat, 1 Jul 2023, Daniel Henrique Barboza wrote:
On 6/30/23 19:57, BALATON Zoltan wrote:
On Fri, 30 Jun 2023, Daniel Henrique Barboza wrote:
Patches 1, 2, 3, 5, 7 and 11 are queued.
If you would be so kind to get the remaining patches, rebase them
on top of my ppc-next and resend, I believe
On 6/30/23 14:25, Anton Johansson via wrote:
CPUNegativeOffsetState is a struct placed immediately before
CPUArchState in the ArchCPU struct. Its purpose is to ensure that
certain fields (CPUTLBDescFast, IcountDecr) lay within a small negative
offset of CPUArchState in memory. This is desired
When you start building the next PPC PR, I think you can also take
this patch :
[4/4] target/ppc: Implement core timebase state machine and TFMR
https://patchwork.ozlabs.org/project/qemu-ppc/patch/20230603233612.125879-5-npig...@gmail.com/
It belongs to the same series.
That doesn't
On Sat Jul 1, 2023 at 5:38 AM AEST, Daniel Henrique Barboza wrote:
>
>
> On 6/29/23 01:58, Cédric Le Goater wrote:
> > On 6/25/23 14:03, Nicholas Piggin wrote:
> >> Cedric kindly reviewed these already so I think they should be
> >> good to go now. This is just a rebase and slight rewording the
>
/rth7680/qemu.git tags/pull-tcg-20230701
for you to fetch changes up to 605a8b5491a119a2a6efbf61e5a38f9374645990:
linux-user: Avoid mmap of the last byte of the reserved_va (2023-07-01
08:33:08 +0200)
dbus: Two hot fixes, per
On 1/7/23 08:28, Richard Henderson wrote:
On 6/30/23 23:41, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Commit commit 6cc5a615 ("ui/dbus: win32 support") has broken audio/dbus
compilation when pixman is not included.
Fixes:https://gitlab.com/qemu-project/qemu/-/issues/1739
On 2023/07/01 0:29, Michael S. Tsirkin wrote:
On Fri, Jun 30, 2023 at 08:36:38PM +0900, Akihiko Odaki wrote:
On 2023/06/30 19:37, Ani Sinha wrote:
On 30-Jun-2023, at 3:30 PM, Michael S. Tsirkin wrote:
On Fri, Jun 30, 2023 at 02:52:52PM +0530, Ani Sinha wrote:
On 30-Jun-2023, at 2:13
On 2023/06/30 22:56, Ani Sinha wrote:
On 30-Jun-2023, at 5:25 PM, Akihiko Odaki wrote:
On 2023/06/30 20:36, Akihiko Odaki wrote:
On 2023/06/30 19:37, Ani Sinha wrote:
On 30-Jun-2023, at 3:30 PM, Michael S. Tsirkin wrote:
On Fri, Jun 30, 2023 at 02:52:52PM +0530, Ani Sinha wrote:
The function number must be lower than the next function number
advertised with ARI. Add a check to enforce this.
I suggested this change at:
https://lore.kernel.org/qemu-devel/bf351f8b-1c8a-8a7a-7f44-17c9ba18f...@daynix.com/
Implementing this change, I found the devices implementing ARI do not
The next function numbers are expected to form a linked list ending with
0.
Fixes: 44c2c09488 ("hw/nvme: Add support for SR-IOV")
Signed-off-by: Akihiko Odaki
---
hw/nvme/ctrl.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index
The next function numbers are expected to form a linked list ending with
0.
Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in
docs/pcie_sriov.txt")
Signed-off-by: Akihiko Odaki
---
docs/pcie_sriov.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
The next function numbers are expected to form a linked list ending with
0.
Fixes: 3a977deebe ("Intrdocue igb device emulation")
Signed-off-by: Akihiko Odaki
---
hw/net/igb_core.h | 3 +++
hw/net/igb.c | 4 +---
hw/net/igbvf.c| 5 -
3 files changed, 8 insertions(+), 4 deletions(-)
The function number must be lower than the next function number
advertised with ARI.
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index e2eb4c3b4a..568665ee42 100644
--- a/hw/pci/pci.c
+++
On 6/30/23 18:06, Michael Tokarev wrote:
29.06.2023 11:08, Richard Henderson wrote:
There is an overflow problem in mmap_find_vma_reserved:
when reserved_va == UINT32_MAX, end may overflow to 0.
Rather than a larger rewrite at this time, simply avoid
the final byte of the VA, which avoids
There is an overflow problem in mmap_find_vma_reserved:
when reserved_va == UINT32_MAX, end may overflow to 0.
Rather than a larger rewrite at this time, simply avoid
the final byte of the VA, which avoids searching the
final page, which avoids the overflow.
Cc: qemu-sta...@nongnu.org
Resolves:
The standard floating point results are provided by the generic routine.
We only need handle the extra Z flag result afterward.
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Message-Id: <20230527141910.1885950-5-richard.hender...@linaro.org>
---
target/arm/vfp_helper.c | 71
The following changes since commit 408015a97dbe48a9dde8c0d2526c9312691952e7:
Merge tag 'pull-vfio-20230630' of https://github.com/legoater/qemu into
staging (2023-06-30 08:11:08 +0200)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230701
From: Peter Maydell
When we generate code for guest loads and stores, at the moment they
end up being requests for a host-endian access. So for target-system-nios2
(little endian) a load like
ldwr3,0(r4)
results on an x86 host in the TCG IR
qemu_ld_a32_i32 r3,loc2,al+leul,0
but on
Test for invalid, integer overflow, and inexact.
Test for proper result, modulo 2**64.
Signed-off-by: Richard Henderson
Acked-by: Alex Bennée
Message-Id: <20230527141910.1885950-3-richard.hender...@linaro.org>
---
tests/tcg/alpha/test-cvttq.c| 78 +
From: Mark Cave-Ayland
Ensure that that both the start and last addresses are within
the same guest page.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230629082522.606219-3-mark.cave-ayl...@ilande.co.uk>
[rth: Use tcg_debug_assert, simplify the
For the most part we can use the new generic routine,
though exceptions need some post-processing to sort
invalid from integer overflow.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230527141910.1885950-4-richard.hender...@linaro.org>
---
Add some ifdefs to avoid an unused function and unused variable.
Fixes: de1f8ce0abb8 ("ui/dbus: use shared D3D11 Texture2D when possible")
Co-developed-by: BALATON Zoltan
Message-Id: <336f7697-bcfa-1f5f-e411-6859815aa...@eik.bme.hu>
Signed-off-by: Richard Henderson
---
ui/dbus-listener.c | 4
From: Philippe Mathieu-Daudé
tcg_assert_listed_vecop() is only used in tcg-op-vec.c.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20230629091107.74384-1-phi...@linaro.org>
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 6 --
From: Mark Cave-Ayland
Due to a copy-paste error in tb_invalidate_phys_range, the wrong
start address was passed to tb_invalidate_phys_page_range__locked.
Correct is to use the start of each page in turn.
Signed-off-by: Mark Cave-Ayland
Fixes: e506ad6a05 ("accel/tcg: Pass last not end to
Add versions of float64_to_int* which do not saturate the result.
Reviewed-by: Christoph Muellner
Tested-by: Christoph Muellner
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Message-Id: <20230527141910.1885950-2-richard.hender...@linaro.org>
---
include/fpu/softfloat.h | 3 ++
From: Marc-André Lureau
Commit commit 6cc5a615 ("ui/dbus: win32 support") has broken audio/dbus
compilation when pixman is not included.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1739
Signed-off-by: Marc-André Lureau
Message-Id:
On 6/30/23 19:57, BALATON Zoltan wrote:
On Fri, 30 Jun 2023, Daniel Henrique Barboza wrote:
Patches 1, 2, 3, 5, 7 and 11 are queued.
If you would be so kind to get the remaining patches, rebase them
on top of my ppc-next and resend, I believe there's more stuff
to be queued.
Thanks for
On 6/30/23 23:41, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Commit commit 6cc5a615 ("ui/dbus: win32 support") has broken audio/dbus
compilation when pixman is not included.
Fixes:https://gitlab.com/qemu-project/qemu/-/issues/1739
Signed-off-by: Marc-André Lureau
---
On 2023/04/21 17:09, Michael S. Tsirkin wrote:
On Tue, Apr 11, 2023 at 12:11:30PM +0200, Philippe Mathieu-Daudé wrote:
On 11/4/23 11:04, Akihiko Odaki wrote:
pci_new() automatically retains a reference to a virtual function when
registering it so we need to release the reference when
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