*** This bug is a duplicate of bug 2025591 ***
https://bugs.launchpad.net/bugs/2025591
** This bug has been marked a duplicate of bug 2025591
Align the iov length to the logical block size
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** Changed in: qemu
Assignee: (unassigned) => ChengEn, Du (chengendu)
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https://bugs.launchpad.net/bugs/2025586
Title:
Align the iov length to the logical block size
Status in
Hello Peter and Michael, thanks for reviewing!
On Thu, 2023-06-29 at 16:56 -0400, Peter Xu wrote:
> On Thu, Jun 29, 2023 at 04:06:53PM -0400, Michael S. Tsirkin wrote:
> > On Thu, Jun 29, 2023 at 04:01:41PM -0400, Peter Xu wrote:
> > > On Thu, Jun 29, 2023 at 03:33:06PM -0400, Michael S. Tsirkin
> On 02-Jul-2023, at 2:03 PM, Akihiko Odaki wrote:
>
> The ARI next function number field is undefined for VF. The PF should
> end the linked list formed with the field by specifying 0.
>
> Supersedes: <20230701070133.24877-1-akihiko.od...@daynix.com>
> ("[PATCH 0/4] pci: Compare function
On 2023/07/03 13:52, Michael S. Tsirkin wrote:
On Mon, Jul 03, 2023 at 12:17:16PM +0900, Akihiko Odaki wrote:
On 2023/07/02 21:43, Michael S. Tsirkin wrote:
On Sun, Jul 02, 2023 at 09:02:25PM +0900, Akihiko Odaki wrote:
The ARI next function number field is undefined for VF. The PF should
end
On Mon, Jul 03, 2023 at 12:17:16PM +0900, Akihiko Odaki wrote:
> On 2023/07/02 21:43, Michael S. Tsirkin wrote:
> > On Sun, Jul 02, 2023 at 09:02:25PM +0900, Akihiko Odaki wrote:
> > > The ARI next function number field is undefined for VF. The PF should
> > > end the linked list formed with the
On Sun, Jun 25, 2023 at 8:27 AM Peter Samir
wrote:
>
> hello,
> I built RISC-V toolchain and QEMU as follows:
> # Install prerequisites:
> https://github.com/riscv-collab/riscv-gnu-toolchain#prerequisites
> # Install additional prerequisites:
>
On Mon, Jun 26, 2023 at 4:24 PM Alexandre IOOSS wrote:
>
> On 6/20/23 00:18, Lucas Villa Real wrote:
> > This patch adds support for the emulation of different density lines
> > (low, medium, and high). A new class property stm32f100-soc.density=
> > has been introduced to allow users to state
On Sun, Jun 25, 2023 at 1:43 PM Lucas C. Villa Real wrote:
>
> On Thu, Jun 22, 2023 at 10:30 PM Alistair Francis
> wrote:
>>
>> > +
>> > +object_class_property_add_str(oc, "density", stm32f100_get_density,
>> > +stm32f100_set_density);
>> > +
On Sat, Jul 1, 2023 at 3:04 AM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This patch introduces the RISC-V Zfa extension, which introduces
> additional floating-point instructions:
> * fli (load-immediate) with pre-defined immediates
> * fminm/fmaxm (like fmin/fmax but with
If the devicetree is created before machine initialization is complete,
it misses dynamic devices. Specifically, the tpm device is not added
to the devicetree file and is therefore not instantiated in Linux.
Create devicetree in virt_machine_done() to solve the problem.
Cc: Alistair Francis
Public bug reported:
[Impact]
When the logical block size of the virtual block device is smaller than the
block device it is backed by on the host,
qemu encounters a situation where it needs to bounce unaligned buffers during
the use of direct IO.
In the past, the logical block size happened to
On Tue, Jun 27, 2023 at 11:32 PM Jason Chien wrote:
>
> The privileged spec states:
> For a memory access made to support VS-stage address translation (such as
> to read/write a VS-level page table), permissions are checked as though
> for a load or store, not for the original access type.
On Tue, Jun 27, 2023 at 11:32 PM Jason Chien wrote:
>
> The privileged spec states:
> For a memory access made to support VS-stage address translation (such as
> to read/write a VS-level page table), permissions are checked as though
> for a load or store, not for the original access type.
On Fri, Jun 23, 2023 at 8:29 PM Alex Bennée wrote:
>
>
> Alistair Francis writes:
>
> > On Thu, Jun 1, 2023 at 4:58 AM Alex Bennée wrote:
> >>
> >>
> >> Brian Cain writes:
> >>
> >> >> -Original Message-
> >> >> From: Alex Bennée
> >> >> Sent: Wednesday, May 31, 2023 6:24 AM
> >> >>
On 2023/07/02 21:43, Michael S. Tsirkin wrote:
On Sun, Jul 02, 2023 at 09:02:25PM +0900, Akihiko Odaki wrote:
The ARI next function number field is undefined for VF. The PF should
end the linked list formed with the field by specifying 0.
Supersedes:
On Wed, Jun 21, 2023 at 4:34 PM Guenter Roeck wrote:
>
> On Mon, Jun 19, 2023 at 01:32:34PM -0700, Guenter Roeck wrote:
> > Hi Alistair,
> >
> > On Wed, Apr 20, 2022 at 03:52:48PM +1000, Alistair Francis wrote:
> > > From: Alistair Francis
> > >
> > > Imply the TPM sysbus devices. This allows
On Thu, Jun 15, 2023 at 4:36 PM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
I have applied the first 5 patches, do you mind rebasing this patch
and resending it?
Alistair
> ---
> disas/riscv.c | 44
> 1 file
On Thu, Jun 15, 2023 at 4:34 PM Weiwei Li wrote:
>
> Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
> Add require check for BF16 extensions.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
>
On Tue, Jun 27, 2023 at 10:35 PM Robbin Ehn wrote:
>
> On Fri, 2023-06-23 at 12:24 +1000, Alistair Francis wrote:
> > On Mon, Jun 19, 2023 at 6:25 PM Robbin Ehn wrote:
> > >
> > > This patch adds the new syscall for the
> > > "RISC-V Hardware Probing Interface"
> > >
On Thu, Jun 29, 2023 at 10:12 PM Philippe Mathieu-Daudé
wrote:
>
> The Advanced Core Local Interruptor (ACLINT) device can
> only be used with TCG. Check for TCG enabled instead of
> KVM being not. Only add the property when TCG is used.
>
> Signed-off-by: Philippe Mathieu-Daudé
Thanks!
On Thu, Jun 29, 2023 at 10:12 PM Philippe Mathieu-Daudé
wrote:
>
> The Advanced Core Local Interruptor (ACLINT) device can
> only be used with TCG. Check for TCG enabled instead of
> KVM being not. Only add the property when TCG is used.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by:
On Wed, Jun 28, 2023 at 11:34 PM Ruibo Lu wrote:
>
> the check of top PMP is redundant and will not influence the return
> value, so consider remove it
>
> Signed-off-by: Ruibo Lu
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmp.c | 5 -
> 1 file changed, 5 deletions(-)
>
On Thu, Jun 29, 2023 at 6:39 PM Ivan Klokov wrote:
>
> Print RvV extension register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> v5:
>- Fix typo, move macros out of function, direct access to cfg.vlen field.
> ---
On Thu, Jun 29, 2023 at 6:39 PM Ivan Klokov wrote:
>
> Print RvV extension register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov
Reviewed-by: Alistair Francis
Alistair
> ---
> v5:
>- Fix typo, move macros out of function, direct access to cfg.vlen field.
> ---
>
On Wed, Jun 28, 2023 at 12:33 AM Philippe Mathieu-Daudé
wrote:
>
> Per Anup Patel in [*]:
>
> > Currently, we only support running rv64 guest on rv64 host
> > and rv32 guest on rv32 host.
> >
> > In the future, we might support running rv32 guest on rv64
> > host but as of now we don't see a
On Wed, Jun 28, 2023 at 12:33 AM Philippe Mathieu-Daudé
wrote:
>
> Per Anup Patel in [*]:
>
> > Currently, we only support running rv64 guest on rv64 host
> > and rv32 guest on rv32 host.
> >
> > In the future, we might support running rv32 guest on rv64
> > host but as of now we don't see a
On 5/31/2023 4:43 PM, Xiaoyao Li wrote:
Initial virtualization of Intel PT was added by making it as fixed
feature set of ICX's capabilities. However, it breaks the Intel PT exposure
on SPR machine because SPR has less PT capabilities of
CPUID(0x14,1):EBX[15:0].
This series aims to make Intel
On Sun, Jun 25, 2023 at 5:30 AM Philippe Mathieu-Daudé
wrote:
>
> These fields shouldn't be accessed when KVM is not available.
>
> Restrict the KVM timer migration state. Rename the KVM timer
> post_load() handler accordingly, because cpu_post_load() is
> too generic.
>
> Signed-off-by: Philippe
On Wed, Jun 28, 2023 at 12:13 AM Tommy Wu wrote:
>
> The HiFive 1 rev b includes a watchdog module based on a 32-bit
> counter. The watchdog timer is in the always-on domain device of
> HiFive 1 rev b, so this patch added the AON device to the sifive_e
> machine. This patch only implemented the
On Wed, 28 Jun 2023 10:09:47 -0700
"ni...@outlook.com" wrote:
> The 05/15/2023 16:22, Jonathan Cameron wrote:
> > On Thu, 11 May 2023 17:56:40 +
> > Fan Ni wrote:
> >
> > > From: Fan Ni
> > >
> > > Before the change, read from or write to dynamic capacity of the memory
> > > device is
On Wed, Jun 28, 2023 at 4:34 PM Philippe Mathieu-Daudé
wrote:
>
> As requested by Daniel in [1], these patches are extracted from
> my "target/riscv: Allow building without TCG (KVM-only so far)"
> series and cleanly rebased onto Alistair's riscv-to-apply.next.
>
> [1]
>
On Tue, Jun 20, 2023 at 6:17 PM Philippe Mathieu-Daudé
wrote:
>
> Since we always check whether KVM is enabled before calling
> kvm_riscv_reset_vcpu() and kvm_riscv_set_irq(), their call
> is elided by the compiler when KVM is not available.
> Therefore the stubs are not even linked. Remove them.
On Tue, Jun 20, 2023 at 6:17 PM Philippe Mathieu-Daudé
wrote:
>
> Since we always check whether KVM is enabled before calling
> kvm_riscv_reset_vcpu() and kvm_riscv_set_irq(), their call
> is elided by the compiler when KVM is not available.
> Therefore the stubs are not even linked. Remove them.
On Sat, Jul 1, 2023 at 2:08 AM Bin Meng wrote:
>
> The 32-bit Spike boot issue has been fixed in the OpenSBI v1.3.
> Let's enable the 32-bit Spike OpenSBI boot testing.
>
> Signed-off-by: Bin Meng
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> tests/avocado/riscv_opensbi.py | 2
On Sat, Jul 1, 2023 at 2:08 AM Bin Meng wrote:
>
> The 32-bit Spike boot issue has been fixed in the OpenSBI v1.3.
> Let's enable the 32-bit Spike OpenSBI boot testing.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> tests/avocado/riscv_opensbi.py | 2 --
> 1
On Sat, Jul 1, 2023 at 2:08 AM Bin Meng wrote:
>
> Upgrade OpenSBI from v1.2 to v1.3 and the pre-built bios images.
>
> The v1.3 release includes the following commits:
>
> 440fa81 treewide: Replace TRUE/FALSE with true/false
> 6509127 Makefile: Remove -N ldflag to prevent linker RWX warning
>
Am 1. Juli 2023 11:58:57 UTC schrieb Mark Cave-Ayland
:
>On 01/07/2023 10:53, Bernhard Beschow wrote:
>
>> Am 30. Juni 2023 08:48:02 UTC schrieb Paolo Bonzini :
>>> Il mer 28 giu 2023, 13:28 Bernhard Beschow ha scritto:
>>>
Am 27. Juni 2023 12:07:40 UTC schrieb Olaf Hering :
Am 1. Juli 2023 17:46:59 UTC schrieb Olaf Hering :
>According to the 82371FB documentation (82371FB.pdf, 2.3.9. BMIBA—BUS
>MASTER INTERFACE BASE ADDRESS REGISTER, April 1997), the register is
>32bit wide. To properly reset it to default values, all 32bit need to be
>cleared. Bit #0 "Resource
30.06.2023 20:53, Richard Henderson wrote:
Ping 2.
On 6/20/23 15:26, Richard Henderson wrote:
Ping.
On 5/24/23 07:46, Richard Henderson wrote:
The beginning of the structure, with pretaddr, should be just below
16-byte alignment. Disconnect fpstate from sigframe, just like the
kernel does.
From: Nicholas Piggin
The icount-based QEMU_CLOCK_VIRTUAL runs ahead of the RT clock at times.
When warping, it is possible it is still ahead at the end of the warp,
which causes icount adaptive mode to adjust it backward. This can result
in the machine observing time going backwards.
Prevent
From: Richard Henderson
There is an overflow problem in mmap_find_vma_reserved:
when reserved_va == UINT32_MAX, end may overflow to 0.
Rather than a larger rewrite at this time, simply avoid
the final byte of the VA, which avoids searching the
final page, which avoids the overflow.
Cc:
From: Laurent Vivier
in vhost_dev_enable_notifiers(), if virtio_bus_set_host_notifier(true)
fails, we call vhost_dev_disable_notifiers() that executes
virtio_bus_set_host_notifier(false) on all queues, even on queues that
have failed to be initialized.
This triggers a core dump in
From: Dongwon Kim
x and y offsets and width and height of the scanout texture
is not correctly configured in case guest scanout frame is
dmabuf.
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
Message-ID: <20230621213150.29573-1-dongwon@intel.com>
From: Shameer Kolothum
When vfio_enable_vectors() returns with less than requested nr_vectors
we retry with what kernel reported back. But the retry path doesn't
call vfio_prepare_kvm_msi_virq_batch() and this results in,
qemu-system-aarch64: vfio: Error: Failed to enable 4 MSI vectors, retry
From: Nicholas Piggin
It is possible to store a very large value to the decrementer that it
does not raise the decrementer exception so the timer is scheduled, but
the next time value wraps and is treated as in the past.
This can occur if (u64)-1 is stored on a zero-triggered exception, or
The following patches are queued for QEMU stable v8.0.3:
https://gitlab.com/qemu-project/qemu/-/commits/staging-8.0
Patch freeze is 2023-07-06, and the release is planned for 2023-07-08:
https://wiki.qemu.org/Planning/8.0
Please respond here or CC qemu-sta...@nongnu.org on any additional
From: Zhenzhong Duan
The kvm irqchip notifier is only registered if the device supports
INTx, however it's unconditionally removed in vfio realize error
path. If the assigned device does not support INTx, this will cause
QEMU to crash when vfio realize fails. Change it to conditionally
remove
From: Markus Armbruster
This reverts commit 1881f336a33a8a99cb17ab1c57ed953682e8e107.
This commit breaks "-drive if=pflash,readonly=on,file=image.iso". It
claims to merely replace an open-coded version of blk_name() by a
call, but that's not the case. Sorry for the inconvenience!
From: Eugenio Pérez
QEMU does not emulate it so it must be disabled as long as the backend
does not support it.
Signed-off-by: Eugenio Pérez
Message-Id: <20230602173328.1917385-1-epere...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Acked-by: Jason Wang
From: Vivek Kasireddy
In the case where the console does not have gl capability, and
if blob is set to true, make sure that the display updates still
work. Commit e86a93f55463 accidentally broke this by misplacing
the return statement (in resource_flush) causing the updates to
be silently
From: Marc-André Lureau
VNC may try to get the current cursor even when there are no consoles
and crashes. Simple reproducer is qemu with -nodefaults.
Fixes: (again)
https://gitlab.com/qemu-project/qemu/-/issues/1548
Fixes: commit 385ac97f8 ("ui: keep current cursor with QemuConsole")
30.06.2023 16:21, Hawkins Jiawei wrote:
This patchset removes the duplicated VIRTIO_NET_F_RSS entry
in vdpa_feature_bits array and sorts the vdpa_feature_bits array
alphabetically in ascending order to avoid future duplicates.
Changelog
=
v3:
- sort array alphabetically suggested by
From: Lawrence Hunter
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:
* vsm3me.vv
* vsm3c.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
From: Nazar Kazakov
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
* vghsh.vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Reviewed-by: Richard Henderson
Signed-off-by: Max Chou
---
include/crypto/sm4.h | 8
target/arm/tcg/crypto_helper.c | 10 ++
2 files changed, 10
From: Nazar Kazakov
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 31 +
1 file
From: Nazar Kazakov
This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:
* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi
Translation functions are defined in
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Signed-off-by: Max Chou
---
crypto/sm4.c | 10 ++
include/crypto/sm4.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/crypto/sm4.c
From: Dickon Hood
Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions. Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.
Signed-off-by: Dickon Hood
Reviewed-by: Richard Henderson
From: Kiran Ostrolenk
This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:
* vsha2ms.vv
* vsha2c[hl].vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
From: Kiran Ostrolenk
Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
---
From: Lawrence Hunter
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vclmulh.[vx,vv]
* vclmul.[vx,vv]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
This commit adds support for the Zvksed vector-crypto extension, which
consists of the following instructions:
* vsm4k.vi
* vsm4r.[vv,vs]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Signed-off-by:
From: Dickon Hood
This commit adds support for the Zvbb vector-crypto extension, which
consists of the following instructions:
* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vwsll.[vv,vx,vi]
Translation functions are defined in
From: Kiran Ostrolenk
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Richard Henderson
Reviewed-by: Alistair
From: Nazar Kazakov
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
From: Kiran Ostrolenk
Take some functions/macros out of `vector_helper` and put them in a new
module called `vector_internals`. This ensures they can be used by both
vector and vector-crypto helpers (latter implemented in proceeding
commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei
This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh,
Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography
extensions as per the v20230620 version of the specification(1)(168e7b4).
This is an update to the patchset submitted to qemu-devel on
Sun, 2 Jul 2023 23:27:00
Tests on real Q800 hardware show that the ESCC is addressable at multiple
locations
within the ESCC memory region - at least 0xc000, 0xc020 (as expected by the
MacOS
toolbox ROM) and 0xc040.
All released NetBSD kernels before 10 use the 0xc000 address which causes a
fatal
error when running
During the kernel timer calibration routine A/UX performs an unaligned access
across the T2CL and T2CH registers to read the entire 16-bit value in a
single memory access.
Allow unaligned accesses to the VIA1 memory region such that the unaligned
address and size are available within the
NetBSD switches directly to IDLE state without switching the shift register to
input mode. Duplicate the existing ADB_STATE_IDLE logic in input mode from when
the shift register is in output mode which allows the ADB autopoll handler to
handle the response.
Signed-off-by: Mark Cave-Ayland
---
[MCA: the original series has now been split into 2 separate parts. Here is
the second and final series of patches. As there are a number of differences
from the original series, I've left off any previous review tags.]
This series contains the remaining patches needed to allow QEMU's q800
The A/UX timer calibration loop runs continuously until 2 consecutive iterations
differ by at least 0x492 timer ticks. Modern hosts execute the timer calibration
loop so fast that this situation never occurs causing a hang on boot.
Use a similar method to Shoebill which is to randomly add 0x500
MacOS reads this address to identify the hardware.
This is a basic implementation returning the ID of Quadra 800.
Details:
http://mess.redump.net/mess/driver_info/mac_technical_notes
"There are 3 ID schemes [...]
The third and most scalable is a machine ID register at 0x5ffc.
The top
The swim chip provides an implementation of both Apple's IWM and ISM floppy disk
controllers. Split the existing implementation into separate register banks for
each controller, whilst also switching the IWM registers from 16-bit to 8-bit
as implemented in real hardware.
Signed-off-by: Mark
This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
(default) or to original mode. The real Q800 hardware used an EASC chip however
a lot of older software only works with the older ASC chip.
Adding this as a machine parameter allows QEMU to be used as an developer aid
for
According to the Apple Quadra 800 Developer Note document, the Quadra 800 ROM
consists of 2 ROM code sections based at offsets 0x0 and 0x80. A/UX attempts
to access the toolbox ROM at the lower offset during startup, so provide a
memory alias to allow the access to succeed.
Signed-off-by:
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
hw/misc/mac_via.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 0787a0268d..baeb73eeb3 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@
MacOS (un)helpfully leaves the FIFO engine running even when all the samples
have
been written to the hardware, and expects the FIFO status flags and IRQ to be
updated continuously.
Since not all audio backends guarantee an all-zero output when no data is
provided, explicitly generate at least
MacOS attempts a series of writes and reads over the entire RAM area in order
to determine the amount of RAM within the machine. Allow accesses to the
entire RAM area ignoring writes and always reading zero for areas where there
is no physical RAM installed to allow MacOS to detect the memory size
Convert the GLUE device to 3-phase reset. The legacy method
doesn't do anything that's invalid in the hold phase, so the
conversion is simple and not a behaviour change.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800-glue.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
The MacOS toolbox ROM calculates the number of branches that can be executed
per millisecond as part of its timer calibration. Since modern hosts are
considerably quicker than original hardware, the negative counter reaches zero
before the calibration completes leading to division by zero later in
NetBSD assumes it can send its first ADB command after sending the ADB_BUSRESET
command in ADB_STATE_NEW without changing the state back to ADB_STATE_IDLE
first as detailed in the ADB protocol.
Add a workaround to detect this condition at the start of ADB enumeration
and send the next command
Update the IWM/ISM register block decoding to match the description given in the
"SWIM Chip Users Reference". This allows us to validate the device response to
the guest OS which currently only does just enough to indicate that the floppy
drive is unavailable.
Signed-off-by: Mark Cave-Ayland
---
When the NetBSD kernel initialises it can leave the ADB interrupt asserted
depending upon where in the ADB poll cycle the MacOS ADB interrupt handler
is when the NetBSD kernel disables interrupts.
The NetBSD ADB driver uses the ADB interrupt state to determine if the ADB
is busy and refuses to
The Quadra 800 has the enhanced ASC (EASC) audio chip which supports both the
legacy IRQ routing through VIA2 and also "A/UX" mode routing direct to the
CPU.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800-glue.c | 11 ++-
hw/m68k/q800.c
The Apple Sound Chip was primarily used by the Macintosh II to generate sound
in hardware which was previously handled by the toolbox ROM with software
interrupts.
Implement both the standard ASC and also the enhanced ASC (EASC) functionality
which is used in the Quadra 800.
Note that whilst
Signed-off-by: Mark Cave-Ayland
---
hw/block/swim.c | 14 ++
hw/block/trace-events | 7 +++
2 files changed, 21 insertions(+)
diff --git a/hw/block/swim.c b/hw/block/swim.c
index 333da08ce0..7df36ea139 100644
--- a/hw/block/swim.c
+++ b/hw/block/swim.c
@@ -19,6 +19,7 @@
It is needed because it defines the BIOSConfig area.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS| 2 +
hw/m68k/Kconfig| 1 +
hw/m68k/q800.c | 9 +++
hw/misc/Kconfig| 3 +
hw/misc/iosb.c | 137
The djMEMC controller is used to store information related to the physical
memory
configuration.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 2 +
hw/m68k/Kconfig | 1 +
hw/m68k/q800.c | 10 +++
hw/misc/Kconfig
On Wed, Jun 21, 2023 at 9:39 AM Dongli Zhang wrote:
>
> The QEMU side calls kvm_get_msrs() to save the pmu registers from the KVM
> side to QEMU, and calls kvm_put_msrs() to store the pmu registers back to
> the KVM side.
>
> However, only the Intel gp/fixed/global pmu registers are involved.
On Wed, Jun 21, 2023 at 9:39 AM Dongli Zhang wrote:
>
> The "perf stat" at the VM side still works even we set "-cpu host,-pmu" in
> the QEMU command line. That is, neither "-cpu host,-pmu" nor "-cpu EPYC"
> could disable the pmu virtualization in an AMD environment.
>
> We still see below at VM
On Sun, Jul 02, 2023 at 08:19:43PM +0900, Akihiko Odaki wrote:
> On 2023/07/02 19:40, Michael S. Tsirkin wrote:
> > On Sun, Jul 02, 2023 at 06:46:25PM +0900, Akihiko Odaki wrote:
> > > The ARI next function number field is undefined for VF so the PF should
> > > end the linked list formed with the
On Sun, Jul 02, 2023 at 09:02:25PM +0900, Akihiko Odaki wrote:
> The ARI next function number field is undefined for VF. The PF should
> end the linked list formed with the field by specifying 0.
>
> Supersedes: <20230701070133.24877-1-akihiko.od...@daynix.com>
> ("[PATCH 0/4] pci: Compare
On Sat, 1 Jul 2023, Daniel Henrique Barboza wrote:
On 7/1/23 06:39, BALATON Zoltan wrote:
On Sat, 1 Jul 2023, Daniel Henrique Barboza wrote:
On 6/30/23 19:57, BALATON Zoltan wrote:
On Fri, 30 Jun 2023, Daniel Henrique Barboza wrote:
Patches 1, 2, 3, 5, 7 and 11 are queued.
If you would be
The current implementers of ARI are all SR-IOV devices. The ARI next
function number field is undefined for VF. The PF should end the linked
list formed with the field by specifying 0.
Fixes: 2503461691 ("pcie: Add some SR/IOV API documentation in
docs/pcie_sriov.txt")
Fixes: 44c2c09488
Currently the only implementers of ARI is SR-IOV devices, and they
behave similar. Share the ARI next function number.
Signed-off-by: Akihiko Odaki
---
docs/pcie_sriov.txt | 4 ++--
include/hw/pci/pcie.h | 2 +-
hw/net/igb.c | 2 +-
hw/net/igbvf.c| 2 +-
hw/nvme/ctrl.c
The ARI next function number field is undefined for VF. The PF should
end the linked list formed with the field by specifying 0.
Supersedes: <20230701070133.24877-1-akihiko.od...@daynix.com>
("[PATCH 0/4] pci: Compare function number and ARI next function number")
V2 -> V3:
Moved the logic to
On 1/7/23 08:19, Akihiko Odaki wrote:
On 2023/04/21 17:09, Michael S. Tsirkin wrote:
On Tue, Apr 11, 2023 at 12:11:30PM +0200, Philippe Mathieu-Daudé wrote:
On 11/4/23 11:04, Akihiko Odaki wrote:
pci_new() automatically retains a reference to a virtual function when
registering it so we need
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