From: Jiajie Chen
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by:
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by:
From: Jiajie Chen
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Reviewed-by: Philippe
From: Jiajie Chen
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-ID: <20230822032724.1353391-3-gaos...@loongson.cn>
---
target/loongarch/cpu-csr.h| 7 +++
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20230822032724.1353391-7-gaos...@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
From: Jiajie Chen
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the
translator to reject doubleword instructions in LA32 mode for example.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-ID:
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20230822032724.1353391-6-gaos...@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by:
From: Jiajie Chen
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-ID: <20230822032724.1353391-2-gaos...@loongson.cn>
---
target/loongarch/cpu-csr.h| 9
From: Jiajie Chen
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Message-ID: <20230822032724.1353391-4-gaos...@loongson.cn>
---
target/loongarch/cpu-csr.h| 6 --
target/loongarch/tlb_helper.c |
(all series reviewed, for Song Gao to pick whichever v4/v5 is preferred)
Hi,
This series adds some checks before translating instructions
This includes:
CPUCFG[1].IOCSR
CPUCFG[2].FP
CPUCFG[2].FP_SP
CPUCFG[2].FP_DP
CPUCFG[2].LSPW
CPUCFG[2].LAM
CPUCFG[2].LSX
V5:
- Split 2 patches, extracting
On 22/8/23 05:27, Song Gao wrote:
From: Jiajie Chen
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loongarch/translate.c | 8
On 22/8/23 05:27, Song Gao wrote:
From: Jiajie Chen
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Song
On 22/8/23 05:27, Song Gao wrote:
Allow virt machine to be used with la132 instead of la464.
Co-authored-by: Jiajie Chen
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 5 -
1 file changed, 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 22/8/23 05:27, Song Gao wrote:
From: Jiajie Chen
Add LoongArch32 cpu la132.
Due to lack of public documentation of la132, it is currently a
synthetic LoongArch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie Chen
Signed-off-by: Song Gao
---
Xiaoyao Li writes:
> From: Isaku Yamahata
>
> For GetQuote, delegate a request to Quote Generation Service. Add property
> of address of quote generation server and On request, connect to the
> server, read request buffer from shared guest memory, send the request
> buffer to the server and
Daniel P. Berrangé writes:
> On Fri, Aug 18, 2023 at 05:50:03AM -0400, Xiaoyao Li wrote:
>> From: Isaku Yamahata
>>
>> When creating TDX vm, three sha384 hash values can be provided for
>> TDX attestation.
>>
>> So far they were hard coded as 0. Now allow user to specify those values
>> via
On 22/8/23 06:25, Richard Henderson wrote:
From: Aaron Lindsay
An instruction is a 'combined' Pointer Authentication instruction
if it does something in addition to PAC -- for instance, branching
to or loading an address from the authenticated pointer.
Knowing whether a PAC operation is
Daniel P. Berrangé writes:
> On Fri, Aug 18, 2023 at 05:49:58AM -0400, Xiaoyao Li wrote:
>> Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
>> EPT violation conversion to #VE on guest TD access of PENDING pages.
>>
>> Some guest OS (e.g., Linux TD guest) may require
Xiaoyao Li writes:
> Introduce tdx-guest object which implements the interface of
> CONFIDENTIAL_GUEST_SUPPORT, and will be used to create TDX VMs (TDs) by
>
> qemu -machine ...,confidential-guest-support=tdx0 \
>-object tdx-guset,id=tdx0
Typo: tdx-guest
> It has only one property
On 22/8/23 06:25, Richard Henderson wrote:
From: Aaron Lindsay
Signed-off-by: Aaron Lindsay
[PMM: drop the HVF part of the patch and just comment that
we need to do something when the register appears in that API]
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 1 +
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