> On 14-Sep-2023, at 2:07 PM, David Hildenbrand wrote:
>
> On 14.09.23 07:53, Ani Sinha wrote:
>>> On 12-Sep-2023, at 9:04 PM, David Hildenbrand wrote:
>>>
>>> [...]
>>>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 54838c0c41..d187890675 100644
> --- a/hw/i386/pc.c
>
://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230915
for you to fetch changes up to e0d9f49c143359b4a34cb80737af57228c62a008:
accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG (2023-09-15 19:06:29
-0700)
*: Delete checks
From: Jiajie Chen
Lower the following ops:
- rotrv_vec
- rotlv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-1...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 14
Signed-off-by: Richard Henderson
Tested-by: Song Gao
Reviewed-by: Song Gao
Message-Id: <20230831030904.1194667-2-richard.hender...@linaro.org>
---
accel/tcg/tcg-runtime.h | 25 ++
include/tcg/tcg-op-gvec-common.h | 6 ++
accel/tcg/tcg-runtime-gvec.c | 26 ++
From: Jiajie Chen
Lower the following ops:
- shli_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-1...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
From: Akihiko Odaki
PA-RISC host support is already removed with commit
b1cef6d02f ("Drop remaining bits of ia64 host support").
Signed-off-by: Akihiko Odaki
Message-Id: <20230810225922.21600-1-akihiko.od...@daynix.com>
Signed-off-by: Richard Henderson
---
softmmu/async-teardown.c | 3 ---
1
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/cpuinfo.h | 1 +
util/cpuinfo-aarch64.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/host/include/aarch64/host/cpuinfo.h
b/host/include/aarch64/host/cpuinfo.h
index
Avoid multiple calls to io_prepare for unaligned acceses.
One call to do_st_mmio_leN will never cross pages.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 82 +-
1 file changed, 30 insertions(+), 52 deletions(-)
diff --git
Rather than saving MemoryRegionSection and offset,
save phys_addr and MemoryRegion. This matches up
much closer with the plugin api.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/plugin-memory.h | 11 ++-
accel/tcg/cputlb.c | 16 +---
Split out int_st_mmio_leN, to be used by both do_st_mmio_leN
and do_st16_mmio_leN. Move the locks down into the two
functions, since each one now covers all accesses to once page.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 88 ++
1
From: Jiajie Chen
If LSX is available, use LSX instructions to implement 128-bit load &
store when MO_128 is required, otherwise use two 64-bit loads & stores.
Signed-off-by: Jiajie Chen
Message-Id: <20230908022302.180442-1...@jia.je>
Reviewed-by: Richard Henderson
Signed-off-by: Richard
Split out int_ld_mmio_beN, to be used by both do_ld_mmio_beN
and do_ld16_mmio_beN. Move the locks down into the two
functions, since each one now covers all accesses to once page.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 91 ++
1
Push computation down into the if statements to the point
the data is used.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 33 +
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/accel/tcg/cputlb.c
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 8
2 files changed, 9 insertions(+), 1
From: Jiajie Chen
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec
- dupi_vec
- dupm_vec
- ld_vec
- st_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-...@jia.je>
Signed-off-by: Richard Henderson
---
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-1...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 21 +
2 files changed, 22
These are common code from io_readx and io_writex.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 77 +++---
1 file changed, 45 insertions(+), 32 deletions(-)
diff --git a/accel/tcg/cputlb.c
From: Jiajie Chen
Lower the following ops:
- ssadd_vec
- usadd_vec
- sssub_vec
- ussub_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-1...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
From: Akihiko Odaki
IA-64 and PA-RISC host support is already removed with commit
b1cef6d02f ("Drop remaining bits of ia64 host support").
Signed-off-by: Akihiko Odaki
Message-Id: <20230810225922.21600-1-akihiko.od...@daynix.com>
Signed-off-by: Richard Henderson
---
util/oslib-posix.c | 15
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f3635afb36..cc36e681a7 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2342,7 +2342,8 @@ static uint8_t
Since the introduction of CPUTLBEntryFull, we can recover
the full cpu address space physical address without having
to examine the MemoryRegionSection.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 12
1 file changed, 4
For linux aarch64 host supporting BTI, map the buffer
to require BTI instructions at branch landing pads.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/region.c | 41 ++---
1 file changed, 30 insertions(+), 11 deletions(-)
From: Nicholas Piggin
mttcg asserts that an execution ending with EXCP_HALTED must have
cpu->halted. However between the event or instruction that sets
cpu->halted and requests exit and the assertion here, an
asynchronous event could clear cpu->halted.
This leads to crashes running AIX on
From: LIU Zhiwei
When memory region is ram, the lower TARGET_PAGE_BITS is not the
physical section number. Instead, its value is always 0.
Add comment and assert to make it clear.
Signed-off-by: LIU Zhiwei
Message-Id: <20230901060118.379-1-zhiwei_...@linux.alibaba.com>
Reviewed-by: Richard
From: Jiajie Chen
Lower the following ops:
- add_vec
- sub_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h |
From: Jiajie Chen
Lower the following ops:
- shlv_vec
- shrv_vec
- sarv_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-1...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
From: Jiajie Chen
Lower the following ops:
- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
- not_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-...@jia.je>
Signed-off-by: Richard Henderson
---
This hook may emit code at the beginning of the TB.
Suggested-by: Jordan Niethe
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 3 +++
tcg/aarch64/tcg-target.c.inc | 5 +
tcg/arm/tcg-target.c.inc | 5 +
Signed-off-by: Richard Henderson
Reviewed-by: Song Gao
Message-Id: <20230831030904.1194667-3-richard.hender...@linaro.org>
---
target/arm/tcg/translate.c | 56 ++
1 file changed, 9 insertions(+), 47 deletions(-)
diff --git a/target/arm/tcg/translate.c
The prologue is entered via "call"; the epilogue, each tb,
and each goto_tb continuation point are all reached via "jump".
As tcg_out_goto_long is only used by tcg_out_exit_tb, merge
the two functions. Change the indirect register used to
TCG_REG_TMP1, aka X17, so that the BTI condition created
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-1...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc |
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 8
2 files changed, 9 insertions(+), 1
From: Akihiko Odaki
Alpha, IA-64, and PA-RISC hosts are no longer supported.
Signed-off-by: Akihiko Odaki
Reviewed-by: Peter Maydell
Message-Id: <20230808152314.102036-1-akihiko.od...@daynix.com>
Signed-off-by: Richard Henderson
---
include/exec/user/thunk.h | 3 +--
1 file changed, 1
Motorola treats denormals with explicit integer bit set as
having unbiased exponent 0, unlike Intel which treats it as
having unbiased exponent 1 (more like all other IEEE formats
that have no explicit integer bit).
Add a flag on FloatFmt to differentiate the behaviour.
Reported-by: Keith
From: LIU Zhiwei
We missed these functions when upstreaming the bfloat16 support.
Signed-off-by: LIU Zhiwei
Message-Id: <20230531065458.2082-1-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
include/fpu/softfloat.h | 12 +
fpu/softfloat.c | 58
-20230915
for you to fetch changes up to e0d9f49c143359b4a34cb80737af57228c62a008:
accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG (2023-09-15 19:06:29
-0700)
*: Delete checks for old host definitions
tcg/loongarch64: Generate LSX
From: Jiajie Chen
Lower the following ops:
- smin_vec
- smax_vec
- umin_vec
- umax_vec
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-1...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
From: Jiajie Chen
Pass vece to tcg_target_const_match() to allow correct interpretation of
const args of vector ops.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230908022302.180442-...@jia.je>
Signed-off-by: Richard Henderson
Now that we defer address space update and tlb_flush until
the next async_run_on_cpu, the plugin run at the end of the
instruction no longer has to contend with a flushed tlb.
Therefore, delete SavedIOTLB entirely.
Properly return false from tlb_plugin_lookup when we do
not have a tlb match.
Avoid multiple calls to io_prepare for unaligned acceses.
One call to do_ld_mmio_beN will never cross pages.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 84 +-
1 file changed, 30 insertions(+), 54 deletions(-)
diff --git
From: Jiajie Chen
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20230908022302.180442-...@jia.je>
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target-con-str.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 65
On Fri, Sep 15, 2023 at 08:05:07AM -0300, Daniel Henrique Barboza wrote:
> Update all relevant PowerPC entries as follows:
>
> - Nick Piggin is promoted to Maintainer in all qemu-ppc subsystems.
> Nick has been a solid contributor for the last couple of years and
> has the required knowledge
On Fri, Sep 15, 2023 at 07:20:13PM +0300, Andrey Drobyshev wrote:
> When rebasing an image from one backing file to another, we need to
> compare data from old and new backings. If the diff between that data
> happens to be unaligned to the target cluster size, we might end up
> doing partial
W dniu 15.09.2023 o 20:54, Peter Maydell pisze:
This patchset implements a model of the Neoverse-N2 CPU.
Because it's very similar to the Cortex-A710 we don't
need to implement any new features for it; but because it
supports 48 bit physical addresses we can use it in the
sbsa-ref board.
Patch
On Fri, 15 Sept 2023 at 05:55, Mattias Nissler wrote:
>
> On Thu, Sep 14, 2023 at 8:49 PM Stefan Hajnoczi wrote:
> >
> > On Thu, Sep 07, 2023 at 06:04:07AM -0700, Mattias Nissler wrote:
> > > When DMA memory can't be directly accessed, as is the case when
> > > running the device model in a
On 15/9/23 21:00, Philippe Mathieu-Daudé wrote:
Prepare the stub for parity with accel_cpu_realize().
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 6 ++
accel/accel-common.c | 4
cpu.c| 3 ++-
3 files changed, 12 insertions(+), 1 deletion(-)
On Fri, Sep 15, 2023 at 07:20:12PM +0300, Andrey Drobyshev wrote:
> Add @chsize param to the function which, if non-zero, would represent
> the chunk size to be used for comparison. If it's zero, then
> BDRV_SECTOR_SIZE is used as default chunk size, which is the previous
> behaviour.
>
> In
On 9/15/23 21:39, Eric Blake wrote:
> On Fri, Sep 15, 2023 at 07:20:11PM +0300, Andrey Drobyshev wrote:
>> Since commit bb1c05973cf ("qemu-img: Use qemu_blockalign"), buffers for
>> the data read from the old and new backing files are aligned using
>> BlockDriverState (or BlockBackend later on)
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have tcg_exec_realizefn() return
a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-all.h | 2 +-
accel/tcg/cpu-exec.c | 4 +++-
2
We don't need to expose these TCG-specific methods to the
whole code base. Register them as AccelClass handlers, they
will be called by the generic accel_cpu_[un]realize() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal.h | 3 +++
include/exec/cpu-all.h | 2 --
Currently accel_cpu_realize() only performs target-specific
realization. Introduce the [un]realize_cpu fields in the
base AccelClass to be able to perform target-agnostic
[un]realization of vCPUs.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 2 ++
accel/accel-common.c | 21
We use the '*fn' suffix for handlers, this is a public method.
Drop the suffix.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 4 ++--
accel/accel-common.c | 2 +-
cpu.c | 2 +-
target/i386/kvm/kvm-cpu.c | 2 +-
4 files changed, 5 insertions(+), 5
Prepare the stub for parity with accel_cpu_realize().
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 6 ++
accel/accel-common.c | 4
cpu.c| 3 ++-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/qemu/accel.h
- Add missing accel_cpu_unrealize()
- Add AccelClass::[un]realize_cpu handlers
- Use tcg_exec_[un]realizefn as AccelClass handlers
Philippe Mathieu-Daudé (5):
accel: Rename accel_cpu_realizefn() -> accel_cpu_realize()
accel: Introduce accel_cpu_unrealize() stub
accel: Declare
This patchset implements a model of the Neoverse-N2 CPU.
Because it's very similar to the Cortex-A710 we don't
need to implement any new features for it; but because it
supports 48 bit physical addresses we can use it in the
sbsa-ref board.
Patch 1 fixes a few minor errors in the A710 definition
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A
processor very similar to the Cortex-A710. The differences are:
* no FEAT_EVT
* FEAT_DGH (data gathering hint)
* FEAT_NV (not yet implemented in QEMU)
* Statistical Profiling Extension (not implemented in QEMU)
* 48 bit physical
Correct a couple of minor errors in the Cortex-A710 definition:
* ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture)
* ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support)
* there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1
Fixes: e3d45c0a89576 ("target/arm:
On 9/15/23 09:32, Richard Henderson wrote:
Supercedes: 20230914174436.1597356-1-richard.hender...@linaro.org
("[PATCH 0/6] accel/tcg: Always require can_do_io (#1866)")
An alternate fix for #1866 without touching can_do_io, and is
perhaps a bit cleaner and clearer.
Instead, the current cpu
This patch contains test which minimally tests discard and new cluster
allocation logic.
The following checks are added:
* write 2 clusters, discard the first allocated
* write another cluster, check that the hole is filled
* write 2 clusters, discard the first allocated, write 1 cluster at
The access to the bitmap is not optimized completely.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 51 ---
1 file changed, 39 insertions(+), 12 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index a6d2f05863..2efa578e21
This would be useful in the next patch in allocate_clusters(). This
change would not imply serious performance drawbacks as usually image
is full of data or are at the end of the bitmap.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 18 ++
1 file changed, 10
This series introduces new block allocator scheme into unused data
blocks inside the image first and only after that extends the file.
On top of that naive implementation of discard and write-zeroes
(through the discard) is added.
There are also a bunch of bugs revealed in the code during the
Parallels driver indeed support Parallels Dirty Bitmap Feature in
read-only mode. The patch adds bdrv_supports_persistent_dirty_bitmap()
callback which always return 1 to indicate that.
This will allow to copy CBT from Parallels image with qemu-img.
Note: read-write support is signalled through
If the operation is failed, we need to check image consistency if the
problem is not about memory allocation.
Bitmap adjustments in allocate_cluster are not performed yet.
They worth to be separate. This was proven useful during debug of this
series. Kept as is for future bissecting.
It should
Replace 'space' representing the amount of data to preallocate with
'bytes'.
Rationale:
* 'space' at each place is converted to bytes
* the unit is more close to the variable name
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 13 +
1 file changed, 5 insertions(+), 8
More conditions follows thus the check should be more scalable.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index 8f223bfd89..aa29df9f77 100644
---
Original check is broken as supposed reading from 2 different clusters
results in read from the same file offset twice. This is definitely
wrong.
We should be sure that
* the content of both clusters is correct after repair
* clusters are at the different offsets after repair
In order to check
We should extend the bitmap ff the file is extended and set the bit in
the image used bitmap once the cluster is allocated. Sanity check at
that moment also looks like a good idea.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 14 ++
1 file changed, 14 insertions(+)
diff
The zero flag is missed in the Parallels format specification. We can
resort to discard if we have no backing file.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/block/parallels.c b/block/parallels.c
index
If the operation is failed, we need to check image consistency if the
problem is not about memory allocation.
Bitmap adjustments in allocate_cluster are not performed yet.
They worth to be separate. This was proven useful during debug of this
series. Kept as is for future bissecting.
It should
* Discarding with backing stores is not supported by the format.
* There is no buffering/queueing of the discard operation.
* Only operations aligned to the cluster are supported.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 47 +++
1 file
This functionality is used twice already and next patch will add more
code with it.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 34 +-
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index
Parallels driver indeed support Parallels Dirty Bitmap Feature in
read-only mode. The patch adds bdrv_supports_persistent_dirty_bitmap()
callback which always return 1 to indicate that.
This will allow to copy CBT from Parallels image with qemu-img.
Note: read-write support is signalled through
The test is quite similar with the original one for duplicated clusters.
There is the only difference in the operation which should fix the
image.
Signed-off-by: Denis V. Lunev
---
tests/qemu-iotests/tests/parallels-checks | 36 +++
Once we have repaired data_off field in the header we should update
s->data_start which is calculated on the base of it.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/parallels.c b/block/parallels.c
index 60ad41b49b..bdc4dd081b
Since
commit cfce1091d55322789582480798a891cbaf66924e
Author: Alexander Ivanov
Date: Tue Jul 18 12:44:29 2023 +0200
parallels: Image repairing in parallels_open()
there is a potential pit fall with calling
qemu-io -c "read"
The image is opened in read-write mode and thus
This patch contains test which minimally tests write-zeroes on top of
working discard.
The following checks are added:
* write 2 clusters, write-zero to the first allocated cluster
* write 2 cluster, write-zero to the half the first allocated cluster
Signed-off-by: Denis V. Lunev
---
We have only check through self-repair and that proven to be not enough.
Signed-off-by: Denis V. Lunev
---
tests/qemu-iotests/tests/parallels-checks | 17 +
tests/qemu-iotests/tests/parallels-checks.out | 18 ++
2 files changed, 35 insertions(+)
diff --git
At the beginning of the function we can return immediately until we
really allocate s->header.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index
This patch creates above mentioned helper and moves its usage to the
beginning of parallels_open(). This simplifies parallels_open() a bit.
The patch also ensures that we store prealloc_size on block driver state
always in sectors. This makes code cleaner and avoids wrong opinion at
the
Old code is ugly and contains tabulations. There are no functional
changes in this patch.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 36 +++-
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index
We do not need to perform any deallocation/cleanup if wrong format is
detected.
Signed-off-by: Denis V. Lunev
---
block/parallels.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/block/parallels.c b/block/parallels.c
index 1d5409f2ba..0f127427bf 100644
---
On Fri, Sep 15, 2023 at 07:20:11PM +0300, Andrey Drobyshev wrote:
> Since commit bb1c05973cf ("qemu-img: Use qemu_blockalign"), buffers for
> the data read from the old and new backing files are aligned using
> BlockDriverState (or BlockBackend later on) referring to the target image.
> However,
On 15.09.23 16:47, Alex Williamson wrote:
On Fri, 15 Sep 2023 16:19:29 +0200
Cédric Le Goater wrote:
Hello Ankit,
On 9/15/23 04:45, ank...@nvidia.com wrote:
From: Ankit Agrawal
For devices which allow CPU to cache coherently access their memory,
it is sensible to expose such memory as
On Fri, 15 Sep 2023 09:59:36 +0200
Cédric Le Goater wrote:
> NVLink2 support was removed from the PPC PowerNV platform and VFIO in
> Linux 5.13 with commits :
>
> 562d1e207d32 ("powerpc/powernv: remove the nvlink support")
> b392a1989170 ("vfio/pci: remove vfio_pci_nvlink2")
>
> This was
On 15/9/23 19:08, Eugenio Pérez wrote:
Otherwise it continues the CVQ isolation probing.
Fixes: 152128d646 ("vdpa: move CVQ isolation check to net_init_vhost_vdpa")
Reported-by: Peter Maydell
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
On 15/9/23 19:08, Eugenio Pérez wrote:
It incorrectly prints "error setting features", probably because a copy
paste miss.
Fixes: 152128d646 ("vdpa: move CVQ isolation check to net_init_vhost_vdpa")
Reported-by: Peter Maydell
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 2 +-
1 file
On 9/15/23 09:57, Philippe Mathieu-Daudé wrote:
On 15/9/23 18:32, Richard Henderson wrote:
Synchronously check and update the address space for the
current cpu for any slow path access.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1866
Signed-off-by: Richard Henderson
---
On 9/15/23 09:55, Philippe Mathieu-Daudé wrote:
On 15/9/23 18:32, Richard Henderson wrote:
Supercedes: 20230914174436.1597356-1-richard.hender...@linaro.org
("[PATCH 0/6] accel/tcg: Always require can_do_io (#1866)")
Patches 1-4 (5?) are cleanups although, isn't it?
Yes, 1-4 are good
On 2023/09/16 2:01, Viktor Prutyanov wrote:
Windows Server 2022 and Windows 11 require more careful kernel PE image
search and handling of PDB than previous Windows versions.
Also, improve support of large ELF dump files, dumps with unaligned
memory ranges and with big number of ranges.
Viktor
On Fri, 15 Sept 2023 at 09:50, Peter Maydell wrote:
>
> On Fri, 15 Sept 2023 at 10:54, Daniel P. Berrangé wrote:
> > My summary, is that I'd personally be in favour of opening the door
> > to Rust code as a mandatory pre-requisite for QEMU, at the very least
> > for system emulators. Not because
This patch solves a few issues. The most obvious is that the feature
set was done previous to ACKNOWLEDGE | DRIVER status bit set. Current
vdpa devices are permissive with this, but it is better to follow the
standard.
Fixes: 152128d646 ("vdpa: move CVQ isolation check to net_init_vhost_vdpa")
Otherwise it continues the CVQ isolation probing.
Fixes: 152128d646 ("vdpa: move CVQ isolation check to net_init_vhost_vdpa")
Reported-by: Peter Maydell
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
It incorrectly prints "error setting features", probably because a copy
paste miss.
Fixes: 152128d646 ("vdpa: move CVQ isolation check to net_init_vhost_vdpa")
Reported-by: Peter Maydell
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
This series solves a few issues. The most obvious is that the feature set was
done previous to ACKNOWLEDGE | DRIVER status bit set. Current vdpa devices are
permissive with this, but it is better to follow the standard.
Apart from that it fixes two issues reported by Peter Maydell:
* Stop
On 9/15/23 7:33 AM, Stefan Hajnoczi wrote:
On Fri, 15 Sept 2023 at 05:54, Daniel P. Berrangé wrote:
On Thu, Sep 14, 2023 at 01:58:27PM -0400, Tyler Fanelli wrote:
These patches are submitted as an RFC mainly because I'm a relative
newcomer to QEMU with no knowledge of the community's views on
On Fri, 15 Sep 2023 18:01:30 +0100
Jonathan Cameron via wrote:
> On Thu, 14 Sep 2023 15:57:55 +0300
> Michael Tokarev wrote:
>
> > 13.09.2023 18:05, Jonathan Cameron via wrote:
> > > Michael Tsirkin observed that there were some unnecessarily
> > > long lines in the CXL code in a recent
On 15/9/23 19:03, Eugenio Pérez wrote:
Otherwise it continues the CVQ isolation probing.
Fixes: 152128d646 ("vdpa: move CVQ isolation check to net_init_vhost_vdpa")
Reviewed-by: Philippe Mathieu-Daudé
Reported-by: Peter Maydell
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 1 +
Michael Tsirkin observed that there were some unnecessarily
long lines in the CXL code in a recent review.
This patch is intended to rectify that where it does not
hurt readability.
Reviewed-by: Michael Tokarev
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_component.h | 3 ++-
On 15/9/23 19:03, Eugenio Pérez wrote:
It incorrectly prints "error setting features", probably because a copy
paste miss.
Reported-by: Peter Maydell
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe
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