On Thu, Oct 19, 2023 at 11:29 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/translate.c | 12 +---
> 1 file changed, 1 insertion(+), 11 deletions(-)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
At present, to enable the VIRTIO_NET_F_RSS feature, eBPF must
be loaded for the vhost backend.
Given that vhost-vdpa is one of the vhost backend, we need to
implement the SetSteeringEBPF method to support RSS for vhost-vdpa,
even if vhost-vdpa calculates the rss hash in the hardware device
This series enables shadowed CVQ to intercept RSS command
through shadowed CVQ, update the virtio NIC device model
so qemu send it in a migration, and the restore of that
RSS state in the destination.
Note that this patch should be based on
patch "Vhost-vdpa Shadow Virtqueue Hash calculation
This patch reuses vhost_vdpa_net_load_rss() with some
refactorings to restore the receive-side scaling state
at device's startup.
Signed-off-by: Hawkins Jiawei
---
v4:
- add do_rss argument and relative code in vhost_vdpa_net_load_rss()
v3:
Enable SVQ with VIRTIO_NET_F_RSS feature.
Signed-off-by: Hawkins Jiawei
---
v4: no code changes
v3:
https://lore.kernel.org/all/2d2a378291bfac4144a0c0c473cf80415bb580b3.1693299194.git.yin31...@gmail.com/
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c
This patch introduces vhost_vdpa_net_load_rss() to restore
the hash calculation state at device's startup.
Signed-off-by: Hawkins Jiawei
---
v3:
- remove the `do_rss` argument in vhost_vdpa_net_load_rss()
- zero reserved fields in "cfg" manually instead of using memset()
to prevent compiler
This series enables shadowed CVQ to intercept
VIRTIO_NET_CTRL_MQ_HASH_CONFIG command through shadowed CVQ,
update the virtio NIC device model so qemu send it in a
migration, and the restore of that Hash calculation state
in the destination.
ChangeLog
=
v3:
- remove the `do_rss` argument
Enable SVQ with VIRTIO_NET_F_HASH_REPORT feature.
Signed-off-by: Hawkins Jiawei
---
v3: no code changes
v2:
https://lore.kernel.org/all/a67d4abc2c8c5c7636addc729daa5432fa8193bd.1693297766.git.yin31...@gmail.com/
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On 10/21/23 00:59, Paolo Bonzini wrote:
On 10/19/23 23:57, Philippe Mathieu-Daudé wrote:
On 19/10/23 20:29, Richard Henderson wrote:
- default:
+ if (memop_size(size) == TARGET_LONG_BITS) {
return src;
}
Any opinions about adding something like this on top?
On 10/20/23 00:45, Daniel Henrique Barboza wrote:
Commit f57d5f8004 deprecated the 'any' CPU type but failed to change the
default CPU for linux-user. The result is that all linux-users
invocations that doesn't specify a different CPU started to show a
deprecation warning:
$
On 10/20/23 06:03, Philippe Mathieu-Daudé wrote:
Missing review: 6-9
Hi,
Extracted from a bigger series which enforce QDev state machine
(qdev instance must be realized before external API is used on
it).
While here, pxa2xx i2c/intc devices received some qdev fondness.
Since v3:
- Added
On 10/20/23 01:49, Song Gao wrote:
Hi,
This series adds the cpu model 'max' support. and allow users
enable/disable LSX/LASX features.
V3:
- Remove patch 2, add cpu feature flags;
- Remove unused code has_lsx, has_lasx.
V2:
- Use qapi type OnOffAuto;
- Add patch2, add cpu feature flags;
-
On 10/20/23 08:06, Philippe Mathieu-Daudé wrote:
Avoid QOM objects poking at each other internals:
- Pass "link" properties
- Access MMIO via SysBus API
- Simplify using sysbus_create_simple()
Philippe Mathieu-Daudé (6):
hw/m68k/irqc: Pass CPU using QOM link property
hw/m68k/mcf5206: Pass
On 10/20/23 03:54, Philippe Mathieu-Daudé wrote:
Since v2:
- Propagate error in hw/i386/
Philippe Mathieu-Daudé (5):
hw/i386/pc: Pass Error** argument to pc_basic_device_init()
hw/i386/pc: Propagate error if HPET device creation failed
hw/i386/pc: Inline legacy pcspk_init() in
This is a part of patchset where scratchpad is introduced.
The scratchpad provides a set of non-functional registers. The firmware
is free to use them, hardware does not support any special management
support. The scratchpad registers can be read or written from LBUS
slave.
In this model, The
Added basic qtests for FSI model.
Signed-off-by: Ninad Palsule
---
v3:
- Added new qtest as per Cedric's comment.
V4:
- Remove MAINTAINER and documentation changes from this commit
v6:
- Incorporated review comments by Thomas Huth.
---
tests/qtest/fsi-test.c | 207
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang
Added maintainer for IBM FSI model
Signed-off-by: Ninad Palsule
---
V4:
- Added separate commit for MAINTAINER change.
V5:
- Use * instead of listing all files in dir
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Documentation for IBM FSI model.
Signed-off-by: Ninad Palsule
---
v4:
- Added separate commit for documentation
---
docs/specs/fsi.rst | 141 +
1 file changed, 141 insertions(+)
create mode 100644 docs/specs/fsi.rst
diff --git a/docs/specs/fsi.rst
Hello,
Please review the patch-set version 6.
I have incorporated review comments from Cedric, Daniel and Thomas.
Ninad Palsule (10):
hw/fsi: Introduce IBM's Local bus
hw/fsi: Introduce IBM's scratchpad
hw/fsi: Introduce IBM's cfam,fsi-slave
hw/fsi: Introduce IBM's FSI
hw/fsi: IBM's
This patchset introduces IBM's Flexible Service Interface(FSI).
Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.
FSI has long existed in POWER processes and so comes with
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration block presents engines in the
order they are
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
is model such a way that it is embedded inside the FSI master which is a
bus controller.
The FSI master: A controller in the platform service
Didn't spot this one first time around. :-)
The code looks fine to me, and in my test, it does indeed fix the
immediate crash.
There's still something making OVMF from Qemu 8.1 very, very unhappy
even with this patch - I'm getting memory allocation errors from it
and can't get anywhere near
Hello Cedric,
On 10/19/23 03:16, Cédric Le Goater wrote:
Hello Ninad,
On 10/11/23 17:13, Ninad Palsule wrote:
Hello,
Please review the patch-set version 5.
I have incorporated review comments from Cedric.
Ninad Palsule (10):
hw/fsi: Introduce IBM's Local bus
hw/fsi: Introduce IBM's
Hello Cedric,
On 10/19/23 02:16, Cédric Le Goater wrote:
On 10/11/23 17:13, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the
Hello Daniel,
On 10/19/23 03:30, Daniel P. Berrangé wrote:
On Wed, Oct 11, 2023 at 10:13:34AM -0500, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors.
Hello Cedric,
On 10/19/23 02:26, Cédric Le Goater wrote:
On 10/11/23 17:13, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an
Hello Daniel,
On 10/19/23 03:28, Daniel P. Berrangé wrote:
On Wed, Oct 11, 2023 at 10:13:33AM -0500, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
is model such a
Hello Cedric,
On 10/19/23 02:44, Cédric Le Goater wrote:
On 10/11/23 17:13, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
is model such a way that it is embedded
Hello Cedric,
On 10/19/23 12:28, Cédric Le Goater wrote:
On 10/11/23 17:13, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses
Hello Daniel,
On 10/19/23 03:26, Daniel P. Berrangé wrote:
On Wed, Oct 11, 2023 at 10:13:32AM -0500, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that
Hello Cedric,
On 10/19/23 03:00, Cédric Le Goater wrote:
On 10/11/23 17:13, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses
Hello Daniel,
On 10/19/23 03:20, Daniel P. Berrangé wrote:
On Wed, Oct 11, 2023 at 10:13:31AM -0500, Ninad Palsule wrote:
This is a part of patchset where scratchpad is introduced.
The scratchpad provides a set of non-functional registers. The firmware
is free to use them, hardware does not
Hello Daniel,
On 10/19/23 11:09, Daniel P. Berrangé wrote:
On Thu, Oct 19, 2023 at 10:34:52AM -0500, Ninad Palsule wrote:
Hello Daniel,
On 10/19/23 03:14, Daniel P. Berrangé wrote:
On Wed, Oct 11, 2023 at 10:13:30AM -0500, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible
Hello Cedric,
On 10/19/23 03:08, Cédric Le Goater wrote:
On 10/11/23 17:13, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically
Hello Cedric,
On 10/19/23 03:03, Cédric Le Goater wrote:
On 10/11/23 17:13, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically
When using x86 macOS Hypervisor.framework as accelerator, detection of
dirty memory regions is implemented by marking logged memory region
slots as read-only in the EPT, then setting the dirty flag when a
guest write causes a fault. The area marked dirty should then be marked
writable in order for
macOS Hypervisor.framework uses different types for identifying vCPUs,
hv_vcpu_t or hv_vcpuid_t, depending on host architecture. They are not just
differently named typedefs for the same primitive type, but reference
different-width integers.
Instead of using an integer type and casting where
This is a series of semi-related patches for the x86 macOS Hypervisor.framework
(hvf) accelerator backend. The intention is to (1) fix bugs and (2) move the
hvf backend to use more modern and efficient APIs in Hypervisor.framework.
The eventual goal is to replace the main hv_vcpu_run() call with
A bunch of function definitions used empty parentheses instead of (void)
syntax, yielding the following warning when building with clang on macOS:
warning: a function declaration without a prototype is deprecated in all
versions of C [-Wstrict-prototypes]
In addition to fixing these function
This patch adds the INVTSC bit to the Hypervisor.framework accelerator's
CPUID bit passthrough allow-list. Previously, specifying +invtsc in the CPU
configuration would fail with the following warning despite the host CPU
advertising the feature:
qemu-system-x86_64: warning: host doesn't support
Am 20.10.23 um 11:07 schrieb Juan Quintela:
> We can have more than one audio card.
Hi Juan,
I wouldn't use the term "audio card" here. In QEMU speak, Audiodev is an
"audio backend".
With best regards,
Volker
>
> void audio_init_audiodevs(void)
> {
> AudiodevListEntry *e;
>
>
* Alex Bennée (alex.ben...@linaro.org) wrote:
> While reviewing the tb-stats series I was confused by the different
> between physical and ram address. This implements the RAM dump so I
> can replicate the disassembly of "info tb". Whether or not that is a
> good idea remains to be discussed.
Do
On 21/10/2023 06:30, Richard Henderson wrote:
Changes for v3:
* Relax v8 simm13 checking for Tcc.
* Split gen_op_addx_int and reorganize to not clobber current cc_op.
* Do not replicate decoding for insns that can set cc_op.
Changes for v2:
* Fixes for JMPL, RETT, SAVE and RESTORE.
On Fri, 20 Oct 2023 03:29:19 +0900,
Richard Henderson wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Yoshinori Sato
> ---
> target/rx/translate.c | 11 +++
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/target/rx/translate.c b/target/rx/translate.c
>
Some analysis greatly benefits, or depends on, information about
interrupts. For example, we may need to handle the execution of a new
translation block differently if it is not the result of normal program
flow but of an interrupt.
Even with the existing interfaces, it is more or less possible
This allows passing the KVM device node to use as a file
descriptor via /dev/fdset/XX. Passing the device node to
use as a file descriptor allows running qemu unprivileged
even when the user running qemu is not in the kvm group
on distributions where access to /dev/kvm is gated behind
membership
On Thu, Oct 19, 2023 at 5:23 PM Alexander Ivanov
wrote:
>
> We will need these functions in parallels-ext.c too. Let them be global
> functions parallels_mark_used() and parallels_mark_unused().
>
> Signed-off-by: Alexander Ivanov
> ---
> block/parallels.c | 22 --
>
13.09.2023 14:57, Fabian Vogt :
Just like d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit
handles SCR_EL3.FGTEn for FEAT_FGT:
When we direct boot a kernel on a CPU which emulates EL3, we need to
set up the EL3 system registers as the Linux kernel documentation
specifies:
From: Thomas Huth
It's a .c file, not a header!
Fixes: ff8cdbbd7e ("MAINTAINERS: Add information for OpenPIC")
Signed-off-by: Thomas Huth
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+),
From: Thomas Huth
The or1k-sim machine is the only one using the ompic, so let's add
this file to the corresponding sections in the MAINTAINERS file.
Signed-off-by: Thomas Huth
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index af1fc5d76d..ddac1eea9d 100644
--- a/MAINTAINERS
From: Cédric Le Goater
Cc: "Edgar E. Iglesias" (odd fixer:virtex_ml507)
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: Michael Tokarev
---
hw/ppc/ppc440_bamboo.c | 1 -
hw/ppc/virtex_ml507.c | 1 -
2 files changed, 2 deletions(-)
diff --git
From: Thomas Huth
i8259.c is already listed here, so the corresponding header should
be mentioned in this section, too.
Signed-off-by: Thomas Huth
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
From: Cédric Le Goater
The hw/ppc/fw_cfg.c file contains the implementation of
fw_cfg_arch_key_name(), used by the common nvram model. List it under
mac99 machine next to the mac_nvram model.
Cc: Mark Cave-Ayland
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Mark Cave-Ayland
From: Thomas Huth
This doc file obviously belongs to the EBPF section.
Signed-off-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ab95af5be2..27e5b882ae
From: Eric Farman
These are simple typos, since the directories don't exist but the
files themselves do in hw/s390x/
Fixes: 56e3483402 ("MAINTAINERS: split out s390x sections")
Signed-off-by: Eric Farman
Reviewed-by: Claudio Imbrenda
Reviewed-by: Thomas Huth
Reviewed-by: Philippe
From: Peter Maydell
In query_port() we pass the address of a local pvrdma_port_attr
struct to the rdma_query_backend_port() function. Unfortunately,
rdma_backend_query_port() wants a pointer to a struct ibv_port_attr,
and the two are not the same length.
Coverity spotted this (CID 1507146):
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 543a6be00d..6b1f9747d4 100644
--- a/MAINTAINERS
+++
From: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
From: Cédric Le Goater
The fdt.{c.h} files provide a helper routine used by the pseries and
pnv machines. Attached it to the list of the larger one: pseries.
Protected Execution Facility (PEF) is the confidential guest support
for PPC pseries machines.
Reviewed-by: Daniel Henrique Barboza
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ddac1eea9d..da5bff8ec0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
From: Philippe Mathieu-Daudé
hw/ppc/ppc440_uc.c implements the TYPE_PPC460EX_PCIE_HOST
device, which is used by the aCube Sam460ex board.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: BALATON Zoltan
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff
From: Thomas Huth
Some subfolders in tests/tcg/ are already listed in the MAINTAINERS
file, some others aren't listed yet. Add the missing ones now to the
MAINTAINERS file, too, to make sure that get_maintainers.pl reports
the correct maintainer.
Signed-off-by: Thomas Huth
Reviewed-by:
The following changes since commit 384dbdda94c0bba55bf186cccd3714bbb9b737e9:
Merge tag 'migration-20231020-pull-request' of
https://gitlab.com/juan.quintela/qemu into staging (2023-10-20 06:46:53 -0700)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git
From: Thomas Huth
These files obviously belong to the nios2 target, so they should
be listed in the nios2 section in the MAINTAINERS file.
Signed-off-by: Thomas Huth
Signed-off-by: Michael Tokarev
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
From: Philippe Mathieu-Daudé
Apparently l2sram_update_mappings() bit-rotted over time,
when defining MAP_L2SRAM we get:
hw/ppc/ppc440_uc.c:83:17: error: no member named 'isarc' in 'struct
ppc4xx_l2sram_t'
if (l2sram->isarc != isarc ||
~~ ^
hw/ppc/ppc440_uc.c:84:18:
18.10.2023 09:38, Cédric Le Goater :
Adding Cc: qemu-triv...@nongnu.org because these changes don't need to go
through the ppc tree.
Heh. You guys puzzled me quite a bit ;)
Now this puzzle is complete.
Okay, let's pick whole bunch (together with follow-up changes by Thomas)
in the
19.10.2023 18:58, Thomas Huth :
It's a .c file, not a header!
Fixes: ff8cdbbd7e ("MAINTAINERS: Add information for OpenPIC")
Signed-off-by: Thomas Huth
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c12511c73b..a110a0c7a4
[Trim recipient list]
18.10.2023 09:24, Thomas Huth:
Some subfolders in tests/tcg/ are already listed in the MAINTAINERS
file, some others aren't listed yet. Add the missing ones now to the
MAINTAINERS file, too, to make sure that get_maintainers.pl reports
the correct maintainer.
diff --git
On Thu, Oct 19, 2023 at 4:06 PM Alexander Ivanov
wrote:
>
> After used bitmap freeng s->used_bmap points to the freed memory. If we try
> to free used bitmap one more time it leads to double free error.
>
> Set s->used_bmap to NULL to exclude double free error.
>
> Signed-off-by: Alexander Ivanov
On Thu, Oct 19, 2023 at 4:05 PM Alexander Ivanov
wrote:
>
> Now dirty bitmaps can be loaded but there is no their saving. Add code for
> dirty bitmap storage.
>
> Signed-off-by: Alexander Ivanov
> ---
> block/parallels-ext.c | 167 ++
> block/parallels.c
Am 19.10.23 um 12:03 schrieb Emmanouil Pitsidianakis:
> This patch adds a PCI wrapper device for the virtio-sound device.
> It is necessary to instantiate a virtio-snd device in a guest.
> All sound logic will be added to the virtio-snd device in the following
> commits.
>
> To add this device
On 9/12/23 14:06, Ani Sinha wrote:
PAE mode in x86 supports 36 bit address space. Check the PAE CPUID on the
guest processor and set phys_bits to 36 if PAE feature is set. This is in
addition to checking the presence of PSE36 CPUID feature for setting 36 bit
phys_bits.
Signed-off-by: Ani Sinha
On 10/19/23 23:57, Philippe Mathieu-Daudé wrote:
On 19/10/23 20:29, Richard Henderson wrote:
- default:
+ if (memop_size(size) == TARGET_LONG_BITS) {
return src;
}
Any opinions about adding something like this on top?
- 8<
22.09.2023 05:03, Lu Gao:
Block Size Register bits [14:12] is SDMA Buffer Boundary, it is missed
in register write, but it is needed in SDMA transfer. e.g. it will be
used in sdhci_sdma_transfer_multi_blocks to calculate boundary_ variables.
Missing this field will cause wrong operation for
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